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Merge pull request #20960 from alexrp/size-align-fixes

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`std.Target`: A bunch of C type size/alignment fixes
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Andrew Kelley 2024-08-06 14:55:15 -07:00 committed by GitHub
commit c8a226a429
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1 changed files with 21 additions and 29 deletions
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50
lib/std/Target.zig
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@ -1852,14 +1852,15 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
.kalimba,
.lanai,
.wasm32,
.sparc,
.spirv32,
.loongarch32,
.dxil,
.xtensa,
=> 32,
.aarch64,
.aarch64_be,
.dxil,
.mips64,
.mips64el,
.powerpc64,
@ -1874,13 +1875,10 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
.sparc64,
.s390x,
.ve,
.spirv,
.spirv64,
.loongarch64,
=> 64,
.sparc => if (std.Target.sparc.featureSetHas(cpu.features, .v9)) 64 else 32,
.spirv => @panic("TODO what should this value be?"),
};
}
@ -2061,12 +2059,12 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
.aarch64,
.aarch64_be,
.s390x,
.sparc,
.sparc64,
.wasm32,
.wasm64,
.loongarch32,
.loongarch64,
.ve,
=> return 128,
else => return 64,
@ -2167,12 +2165,12 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
.s390x,
.mips64,
.mips64el,
.sparc,
.sparc64,
.wasm32,
.wasm64,
.loongarch32,
.loongarch64,
.ve,
=> return 128,
else => return 64,
@ -2252,23 +2250,20 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
.longdouble => return 64,
},
.amdhsa, .amdpal => switch (c_type) {
.amdhsa, .amdpal, .mesa3d => switch (c_type) {
.char => return 8,
.short, .ushort => return 16,
.int, .uint, .float => return 32,
.long, .ulong, .longlong, .ulonglong, .double => return 64,
.longdouble => return 128,
.longdouble => return 64,
},
.opencl, .vulkan => switch (c_type) {
.char => return 8,
.short, .ushort => return 16,
.int, .uint, .float => return 32,
.long, .ulong, .double => return 64,
.longlong, .ulonglong => return 128,
// Note: The OpenCL specification does not guarantee a particular size for long double,
// but clang uses 128 bits.
.longdouble => return 128,
.long, .ulong, .longlong, .ulonglong, .double => return 64,
.longdouble => return 64,
},
.ps4, .ps5 => switch (c_type) {
@ -2285,7 +2280,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
.rtems,
.aix,
.elfiamcu,
.mesa3d,
.contiki,
.hermit,
.hurd,
@ -2344,11 +2338,8 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.csky,
.x86,
.xcore,
.dxil,
.loongarch32,
.spirv32,
.kalimba,
.ve,
.spu_2,
.xtensa,
=> 4,
@ -2356,22 +2347,24 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.amdgcn,
.bpfel,
.bpfeb,
.dxil,
.hexagon,
.loongarch64,
.m68k,
.mips,
.mipsel,
.sparc,
.sparc64,
.lanai,
.nvptx,
.nvptx64,
.s390x,
.spirv,
.spirv32,
.spirv64,
=> 8,
.aarch64,
.aarch64_be,
.loongarch64,
.mips64,
.mips64el,
.powerpc,
@ -2380,12 +2373,12 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.powerpc64le,
.riscv32,
.riscv64,
.sparc64,
.x86_64,
.ve,
.wasm32,
.wasm64,
=> 16,
.spirv => @panic("TODO what should this value be?"),
}),
);
}
@ -2449,11 +2442,8 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.csky,
.xcore,
.dxil,
.loongarch32,
.spirv32,
.kalimba,
.ve,
.spu_2,
.xtensa,
=> 4,
@ -2467,23 +2457,25 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.amdgcn,
.bpfel,
.bpfeb,
.dxil,
.hexagon,
.x86,
.loongarch64,
.m68k,
.mips,
.mipsel,
.sparc,
.sparc64,
.lanai,
.nvptx,
.nvptx64,
.s390x,
.spirv,
.spirv32,
.spirv64,
=> 8,
.aarch64,
.aarch64_be,
.loongarch64,
.mips64,
.mips64el,
.powerpc,
@ -2492,12 +2484,12 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.powerpc64le,
.riscv32,
.riscv64,
.sparc64,
.x86_64,
.ve,
.wasm32,
.wasm64,
=> 16,
.spirv => @panic("TODO what should this value be?"),
}),
);
}