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allow in-memory coercion of differently-named floats with same bits
For example, this allows passing a `*c_longdouble` where a `*f80` is expected, provided that `c_longdouble` maps to `f80` for this target.
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@ -18673,6 +18673,15 @@ fn coerceInMemoryAllowed(
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}
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}
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// Differently-named floats with the same number of bits.
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if (dest_ty.zigTypeTag() == .Float and src_ty.zigTypeTag() == .Float) {
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const dest_bits = dest_ty.floatBits(target);
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const src_bits = src_ty.floatBits(target);
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if (dest_bits == src_bits) {
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return .ok;
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}
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}
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// Pointers / Pointer-like Optionals
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var dest_buf: Type.Payload.ElemType = undefined;
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var src_buf: Type.Payload.ElemType = undefined;
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@ -4480,6 +4480,12 @@ static ConstCastOnly types_match_const_cast_only(IrAnalyze *ira, ZigType *wanted
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return result;
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}
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if (wanted_type->id == ZigTypeIdFloat && actual_type->id == ZigTypeIdFloat) {
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if (wanted_type->data.floating.bit_count == actual_type->data.floating.bit_count) {
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return result;
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}
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}
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if (wanted_type->id == ZigTypeIdVector && actual_type->id == ZigTypeIdVector) {
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if (actual_type->data.vector.len != wanted_type->data.vector.len) {
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result.id = ConstCastResultIdVectorLength;
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@ -1426,3 +1426,23 @@ test "pointer to empty struct literal to mutable slice" {
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var x: []i32 = &.{};
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try expect(x.len == 0);
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}
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test "coerce between pointers of compatible differently-named floats" {
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if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
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const F = switch (@typeInfo(c_longdouble).Float.bits) {
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16 => f16,
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32 => f32,
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64 => f64,
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80 => f80,
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128 => f128,
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else => @compileError("unreachable"),
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};
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var f1: F = 12.34;
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var f2: *c_longdouble = &f1;
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f2.* += 1;
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try expect(f1 == @as(F, 12.34) + 1);
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}
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