add m68k target CPU features

lib/std/target.zig

@@ -456,6 +456,7 @@ pub const Target = struct {
     pub const bpf = @import("target/bpf.zig");
     pub const csky = @import("target/csky.zig");
     pub const hexagon = @import("target/hexagon.zig");
+    pub const m68k = @import("target/m68k.zig");
     pub const mips = @import("target/mips.zig");
     pub const msp430 = @import("target/msp430.zig");
     pub const nvptx = @import("target/nvptx.zig");
@@ -1353,6 +1354,7 @@ pub const Target = struct {
                     .avr => &avr.cpu.avr2,
                     .bpfel, .bpfeb => &bpf.cpu.generic,
                     .hexagon => &hexagon.cpu.generic,
+                    .m68k => &m68k.cpu.generic,
                     .mips, .mipsel => &mips.cpu.mips32,
                     .mips64, .mips64el => &mips.cpu.mips64,
                     .msp430 => &msp430.cpu.generic,

lib/std/target/m68k.zig

@@ -0,0 +1,213 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
+const std = @import("../std.zig");
+const CpuFeature = std.Target.Cpu.Feature;
+const CpuModel = std.Target.Cpu.Model;
+
+pub const Feature = enum {
+    isa_68000,
+    isa_68010,
+    isa_68020,
+    isa_68030,
+    isa_68040,
+    isa_68060,
+    reserve_a0,
+    reserve_a1,
+    reserve_a2,
+    reserve_a3,
+    reserve_a4,
+    reserve_a5,
+    reserve_a6,
+    reserve_d0,
+    reserve_d1,
+    reserve_d2,
+    reserve_d3,
+    reserve_d4,
+    reserve_d5,
+    reserve_d6,
+    reserve_d7,
+};
+
+pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
+pub const featureSetHas = CpuFeature.feature_set_fns(Feature).featureSetHas;
+pub const featureSetHasAny = CpuFeature.feature_set_fns(Feature).featureSetHasAny;
+pub const featureSetHasAll = CpuFeature.feature_set_fns(Feature).featureSetHasAll;
+
+pub const all_features = blk: {
+    const len = @typeInfo(Feature).Enum.fields.len;
+    std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+    var result: [len]CpuFeature = undefined;
+    result[@enumToInt(Feature.isa_68000)] = .{
+        .llvm_name = "isa-68000",
+        .description = "Is M68000 ISA supported",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.isa_68010)] = .{
+        .llvm_name = "isa-68010",
+        .description = "Is M68010 ISA supported",
+        .dependencies = featureSet(&[_]Feature{
+            .isa_68000,
+        }),
+    };
+    result[@enumToInt(Feature.isa_68020)] = .{
+        .llvm_name = "isa-68020",
+        .description = "Is M68020 ISA supported",
+        .dependencies = featureSet(&[_]Feature{
+            .isa_68010,
+        }),
+    };
+    result[@enumToInt(Feature.isa_68030)] = .{
+        .llvm_name = "isa-68030",
+        .description = "Is M68030 ISA supported",
+        .dependencies = featureSet(&[_]Feature{
+            .isa_68020,
+        }),
+    };
+    result[@enumToInt(Feature.isa_68040)] = .{
+        .llvm_name = "isa-68040",
+        .description = "Is M68040 ISA supported",
+        .dependencies = featureSet(&[_]Feature{
+            .isa_68030,
+        }),
+    };
+    result[@enumToInt(Feature.isa_68060)] = .{
+        .llvm_name = "isa-68060",
+        .description = "Is M68060 ISA supported",
+        .dependencies = featureSet(&[_]Feature{
+            .isa_68040,
+        }),
+    };
+    result[@enumToInt(Feature.reserve_a0)] = .{
+        .llvm_name = "reserve-a0",
+        .description = "Reserve A0 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_a1)] = .{
+        .llvm_name = "reserve-a1",
+        .description = "Reserve A1 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_a2)] = .{
+        .llvm_name = "reserve-a2",
+        .description = "Reserve A2 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_a3)] = .{
+        .llvm_name = "reserve-a3",
+        .description = "Reserve A3 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_a4)] = .{
+        .llvm_name = "reserve-a4",
+        .description = "Reserve A4 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_a5)] = .{
+        .llvm_name = "reserve-a5",
+        .description = "Reserve A5 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_a6)] = .{
+        .llvm_name = "reserve-a6",
+        .description = "Reserve A6 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_d0)] = .{
+        .llvm_name = "reserve-d0",
+        .description = "Reserve D0 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_d1)] = .{
+        .llvm_name = "reserve-d1",
+        .description = "Reserve D1 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_d2)] = .{
+        .llvm_name = "reserve-d2",
+        .description = "Reserve D2 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_d3)] = .{
+        .llvm_name = "reserve-d3",
+        .description = "Reserve D3 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_d4)] = .{
+        .llvm_name = "reserve-d4",
+        .description = "Reserve D4 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_d5)] = .{
+        .llvm_name = "reserve-d5",
+        .description = "Reserve D5 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_d6)] = .{
+        .llvm_name = "reserve-d6",
+        .description = "Reserve D6 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.reserve_d7)] = .{
+        .llvm_name = "reserve-d7",
+        .description = "Reserve D7 register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    const ti = @typeInfo(Feature);
+    for (result) |*elem, i| {
+        elem.index = i;
+        elem.name = ti.Enum.fields[i].name;
+    }
+    break :blk result;
+};
+
+pub const cpu = struct {
+    pub const generic = CpuModel{
+        .name = "generic",
+        .llvm_name = "generic",
+        .features = featureSet(&[_]Feature{
+            .isa_68000,
+        }),
+    };
+    pub const M68000 = CpuModel{
+        .name = "M68000",
+        .llvm_name = "M68000",
+        .features = featureSet(&[_]Feature{
+            .isa_68000,
+        }),
+    };
+    pub const M68010 = CpuModel{
+        .name = "M68010",
+        .llvm_name = "M68010",
+        .features = featureSet(&[_]Feature{
+            .isa_68010,
+        }),
+    };
+    pub const M68020 = CpuModel{
+        .name = "M68020",
+        .llvm_name = "M68020",
+        .features = featureSet(&[_]Feature{
+            .isa_68020,
+        }),
+    };
+    pub const M68030 = CpuModel{
+        .name = "M68030",
+        .llvm_name = "M68030",
+        .features = featureSet(&[_]Feature{
+            .isa_68030,
+        }),
+    };
+    pub const M68040 = CpuModel{
+        .name = "M68040",
+        .llvm_name = "M68040",
+        .features = featureSet(&[_]Feature{
+            .isa_68040,
+        }),
+    };
+    pub const M68060 = CpuModel{
+        .name = "M68060",
+        .llvm_name = "M68060",
+        .features = featureSet(&[_]Feature{
+            .isa_68060,
+        }),
+    };
+};

tools/update_cpu_features.zig

@@ -753,6 +753,11 @@ const llvm_targets = [_]LlvmTarget{
         .llvm_name = "Lanai",
         .td_name = "Lanai.td",
     },
+    .{
+        .zig_name = "m68k",
+        .llvm_name = "M68k",
+        .td_name = "M68k.td",
+    },
     .{
         .zig_name = "msp430",
         .llvm_name = "MSP430",