mirror of
https://github.com/NationalSecurityAgency/ghidra.git
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185 lines
7.9 KiB
Plaintext
185 lines
7.9 KiB
Plaintext
###############################################################################
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# BPF Processor Specification for Ghidra
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###############################################################################
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define space ram type=ram_space size=4 default;
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define space packet type=ram_space size=4;
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define space mem type=ram_space size=4;
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define space register type=register_space size=4;
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define register offset=0 size=4 [ A X RS R PC ];
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define register offset=0 size=2 [ AH _ XH _ RSH _ RH _ PCH _ ];
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define register offset=0 size=1 [ AB _ _ _ XB _ _ _ RSB _ _ _ RB _ _ _ PCB _ _ _ ];
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# Instruction encoding: Insop:8, dst_reg:4, src_reg:4, off:16, imm:32 - from lsb to msb
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define token instr(64)
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imm=(32, 63)
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jf=(24, 31) signed
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jt=(16, 23) signed
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op_src_K_X=(3, 3)
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op_alu_jmp_opcode=(4, 7)
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op_alu_jmp_source=(3, 3)
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op_alu_mode=(4, 7)
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op_ld_st_mode=(5, 7)
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op_ld_st_size=(3, 4)
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op_insn_class=(0, 2)
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;
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:LD imm is imm & op_ld_st_mode=0x0 & op_ld_st_size=0x0 & op_insn_class=0x0 { A=imm; }
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:LDH imm is imm & op_ld_st_mode=0x0 & op_ld_st_size=0x1 & op_insn_class=0x0 { AH=imm:2; A = A & 0xffff; }
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:LDB imm is imm & op_ld_st_mode=0x0 & op_ld_st_size=0x2 & op_insn_class=0x0 { AB=imm:1; A = A & 0xff;}
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:LDX imm is imm & op_ld_st_mode=0x0 & op_ld_st_size=0x0 & op_insn_class=0x1 { X=imm; }
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:LDXH imm is imm & op_ld_st_mode=0x0 & op_ld_st_size=0x1 & op_insn_class=0x1 { XH=imm:2; X = X & 0xffff; }
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:LDXB imm is imm & op_ld_st_mode=0x0 & op_ld_st_size=0x2 & op_insn_class=0x1 { XB=imm:1; X = X & 0xff;}
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:LD imm is imm & op_ld_st_mode=0x1 & op_ld_st_size=0x0 & op_insn_class=0x0 { A=*[packet]:4 imm:4; }
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:LDH imm is imm & op_ld_st_mode=0x1 & op_ld_st_size=0x1 & op_insn_class=0x0 { A=*[packet]:2 imm:4; A = A & 0xffff; }
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:LDB imm is imm & op_ld_st_mode=0x1 & op_ld_st_size=0x2 & op_insn_class=0x0 { A=*[packet]:1 imm:4; A = A & 0xff;}
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:LDX imm is imm & op_ld_st_mode=0x1 & op_ld_st_size=0x0 & op_insn_class=0x1 { X=*[packet]:4 imm:4; }
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:LDXH imm is imm & op_ld_st_mode=0x1 & op_ld_st_size=0x1 & op_insn_class=0x1 { X=*[packet]:2 imm:4; X = X & 0xffff; }
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:LDXB imm is imm & op_ld_st_mode=0x1 & op_ld_st_size=0x2 & op_insn_class=0x1 { X=*[packet]:1 imm:4; X = X & 0xff;}
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:ST imm is imm & op_insn_class=0x2 { *[mem]:4 imm:4=A:4; }
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:STX imm is imm & op_insn_class=0x3 { *[mem]:4 imm:4=X:4; }
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:LDI imm is imm & op_ld_st_mode=0x2 & op_ld_st_size=0x0 & op_insn_class=0x0 { A=*[packet]:4 (imm:4 + X); }
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:LDIH imm is imm & op_ld_st_mode=0x2 & op_ld_st_size=0x1 & op_insn_class=0x0 { A=*[packet]:2 (imm:4 + X); A = A & 0xffff; }
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:LDIB imm is imm & op_ld_st_mode=0x2 & op_ld_st_size=0x2 & op_insn_class=0x0 { A=*[packet]:1 (imm:4 + X); A = A & 0xff; }
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:LD imm is imm & op_ld_st_mode=0x3 & op_ld_st_size=0x0 & op_insn_class=0x0 { A=*[mem]:4 imm:4; }
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:LDH imm is imm & op_ld_st_mode=0x3 & op_ld_st_size=0x1 & op_insn_class=0x0 { A=*[mem]:2 imm:4; A = A & 0xffff; }
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:LDB imm is imm & op_ld_st_mode=0x3 & op_ld_st_size=0x2 & op_insn_class=0x0 { A=*[mem]:1 imm:4; A = A & 0xff; }
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:LDX imm is imm & op_ld_st_mode=0x3 & op_ld_st_size=0x0 & op_insn_class=0x1 { X=*[mem]:4 imm:4; }
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:LDXH imm is imm & op_ld_st_mode=0x3 & op_ld_st_size=0x1 & op_insn_class=0x1 { X=*[mem]:2 imm:4; X = X & 0xffff; }
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:LDXB imm is imm & op_ld_st_mode=0x3 & op_ld_st_size=0x2 & op_insn_class=0x1 { X=*[mem]:1 imm:4; X = X & 0xff; }
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# ALU
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:ADD imm is imm & op_alu_mode=0x0 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A + imm; }
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:ADD X is X & op_alu_mode=0x0 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A + X; }
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:SUB imm is imm & op_alu_mode=0x1 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A - imm; }
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:SUB X is X & op_alu_mode=0x1 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A - X; }
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:MUL imm is imm & op_alu_mode=0x2 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A * imm; }
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:MUL X is X & op_alu_mode=0x2 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A * X; }
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:DIV imm is imm & op_alu_mode=0x3 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A / imm; }
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:DIV X is X & op_alu_mode=0x3 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A / X; }
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:OR imm is imm & op_alu_mode=0x4 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A | imm; }
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:OR X is X & op_alu_mode=0x4 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A | X; }
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:AND imm is imm & op_alu_mode=0x5 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A & imm; }
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:AND X is X & op_alu_mode=0x5 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A & X; }
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:LSH imm is imm & op_alu_mode=0x6 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A << imm; }
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:LSH X is X & op_alu_mode=0x6 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A << X; }
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:RSH imm is imm & op_alu_mode=0x7 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A >> imm; }
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:RSH X is X & op_alu_mode=0x7 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A >> X; }
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:NEG is op_alu_mode=0x8 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= -A; }
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:MOD imm is imm & op_alu_mode=0x9 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A % imm; }
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:MOD X is X & op_alu_mode=0x9 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A % X; }
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:XOR imm is imm & op_alu_mode=0xa & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A ^ imm; }
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:XOR X is X & op_alu_mode=0xa & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A ^ X; }
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:TAX is op_insn_class=0x7 & op_src_K_X = 0x0 { A= X; }
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:TXA is op_insn_class=0x7 & op_src_K_X = 0x1 { X= A; }
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:LD_MSH imm is imm & op_ld_st_mode=0x5 & op_ld_st_size=0x0 & op_insn_class=0x0 {
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local t_val = *[packet]:4 imm:4;
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t_val = t_val&0xf;
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t_val = t_val << 2;
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A = t_val;
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}
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:LDH_MSH imm is imm & op_ld_st_mode=0x5 & op_ld_st_size=0x1 & op_insn_class=0x0 {
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local t_val = *[packet]:2 imm:4;
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t_val = t_val&0xf;
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t_val = t_val << 2;
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AH = t_val;
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}
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:LDB_MSH imm is imm & op_ld_st_mode=0x5 & op_ld_st_size=0x2 & op_insn_class=0x0 {
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local t_val = *[packet]:1 imm:4;
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t_val = t_val&0xf;
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t_val = t_val << 2;
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AB = t_val;
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}
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:LDX_MSH imm is imm & op_ld_st_mode=0x5 & op_ld_st_size=0x0 & op_insn_class=0x1 {
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local t_val = *[packet]:4 imm:4;
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t_val = t_val&0xf;
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t_val = t_val << 2;
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X = t_val;
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}
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:LDXH_MSH imm is imm & op_ld_st_mode=0x5 & op_ld_st_size=0x1 & op_insn_class=0x1 {
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local t_val = *[packet]:2 imm:4;
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t_val = t_val&0xf;
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t_val = t_val << 2;
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XH = t_val;
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X = X & 0xffff;
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}
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:LDXB_MSH imm is imm & op_ld_st_mode=0x5 & op_ld_st_size=0x2 & op_insn_class=0x1 {
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local t_val = *[packet]:1 imm:4;
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t_val = t_val&0xf;
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t_val = t_val << 2;
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XB = t_val;
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X = X & 0xff;
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}
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#Branch instructions
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###############################################################################
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joff: reloc is imm [ reloc = inst_next + imm * 8; ] { export *:8 reloc; }
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jtoff: reloc is jt [ reloc = inst_next + jt * 8; ] { export *:8 reloc; }
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jfoff: reloc is jf [ reloc = inst_next + jf * 8; ] { export *:8 reloc; }
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:JA joff is joff & op_alu_jmp_opcode=0x0 & op_alu_jmp_source=0 & op_insn_class=0x5 {
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goto joff;
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}
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:JEQ jtoff, jfoff, imm is imm & jtoff & jfoff & op_alu_jmp_opcode=0x1 & op_alu_jmp_source=0 & op_insn_class=0x5 {
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if (A==imm) goto jtoff;
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goto jfoff;
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}
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:JEQ jtoff, jfoff, X is X & jtoff & jfoff & op_alu_jmp_opcode=0x1 & op_alu_jmp_source=1 & op_insn_class=0x5 {
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if (A==X) goto jtoff;
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goto jfoff;
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}
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:JGT jtoff, jfoff, imm is imm & jtoff & jfoff & op_alu_jmp_opcode=0x2 & op_alu_jmp_source=0 & op_insn_class=0x5 {
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if (A > imm) goto jtoff;
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goto jfoff;
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}
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:JGT jtoff, jfoff, X is X & jtoff & jfoff & op_alu_jmp_opcode=0x2 & op_alu_jmp_source=1 & op_insn_class=0x5 {
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if (A > X) goto jtoff;
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goto jfoff;
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}
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:JGE jtoff, jfoff, imm is imm & jtoff & jfoff & op_alu_jmp_opcode=0x3 & op_alu_jmp_source=0 & op_insn_class=0x5 {
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if (A >= imm) goto jtoff;
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goto jfoff;
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}
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:JGE jtoff, jfoff, X is X & jtoff & jfoff & op_alu_jmp_opcode=0x3 & op_alu_jmp_source=1 & op_insn_class=0x5 {
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if (A >= X) goto jtoff;
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goto jfoff;
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}
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:JSET jtoff, jfoff, imm is imm & jtoff & jfoff & op_alu_jmp_opcode=0x4 & op_alu_jmp_source=0 & op_insn_class=0x5 {
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if ((A&imm) != 0) goto jtoff;
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goto jfoff;
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}
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:JSET jtoff, jfoff, X is X & jtoff & jfoff & op_alu_jmp_opcode=0x4 & op_alu_jmp_source=1 & op_insn_class=0x5 {
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if ((A&X) != 0) goto jtoff;
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goto jfoff;
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}
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:RETW imm is imm & op_ld_st_size=0 & op_insn_class=0x6 {
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R = imm;
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return [*:8 RS];
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}
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