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Macros and cspec fixes

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This commit is contained in:
Aleckaj 2020-02-24 20:28:58 +01:00
parent 798c94f36a
commit f317ada6a8
15 changed files with 20 additions and 18 deletions
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2
Ghidra/Processors/V850/data/languages/Helpers/Conditions.sinc
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@ -35,4 +35,4 @@ c1720: "sa" is op1720=0xD { tmp:1 = ($(SAT)) == 1; export tmp; }
c1720: "lt" is op1720=0x6 { tmp:1 = ($(S) ^^ $(OV)) == 1; export tmp; }
c1720: "ge" is op1720=0xE { tmp:1 = ($(S) ^^ $(OV)) == 0; export tmp; }
c1720: "le" is op1720=0x7 { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 1; export tmp; }
c1720: "gt" is op1720=0xF { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; }
c1720: "gt" is op1720=0xF { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; }

2
Ghidra/Processors/V850/data/languages/Helpers/Extras.sinc
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@ -122,4 +122,4 @@ DispList21: r21,DispList22 is DispList22 & prep26=1 & r21 { pop(r21); }
DispList21: DispList22 is DispList22 & prep26=0 { }
DispList: { r20,DispList21 } is DispList21 & prep27=1 & r20 { pop(r20); }
DispList: { DispList21 } is DispList21 & prep27=0 { }
DispList: { DispList21 } is DispList21 & prep27=0 { }

8
Ghidra/Processors/V850/data/languages/Helpers/Macros.sinc
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@ -133,7 +133,7 @@ macro either_or1(res, cond, true, false) # if condition is == 1
macro shift_right_logic(res, var, shift_)
{
local shift = shift_ & 0x1f;
local mask = (zext(shift != 0) * (var & (1 << (shift - 1)))) + (zext(shift == 0) * 0);
local mask = (zext(shift != 0) * var) & (1 << (shift - 1));
res = var >> shift;
set_OV0_S_Z(res);
$(CY) = ((mask != 0) && (shift != 0));
@ -142,7 +142,7 @@ macro shift_right_logic(res, var, shift_)
macro shift_right_arith(res, var, shift_)
{
local shift = shift_ & 0x1f;
local mask = (zext(shift != 0) * (var & (1 << (shift - 1)))) + (zext(shift == 0) * 0);
local mask = (zext(shift != 0) * var) & (1 << (shift - 1));
res = var s>> shift;
set_OV0_S_Z(res);
$(CY) = ((mask != 0) && (shift != 0));
@ -151,7 +151,7 @@ macro shift_right_arith(res, var, shift_)
macro shift_left_logic(res, var, shift_)
{
local shift = shift_ & 0x1f;
local mask = (zext(shift != 0) * (var & (1 << (32 - shift)))) + (zext(shift == 0) * 0);
local mask = (zext(shift != 0) * var) & (1 << (32 - shift));
res = var << shift;
set_OV0_S_Z(res);
$(CY) = ((mask != 0) && (shift != 0));
@ -249,4 +249,4 @@ macro compare_float(res, fcond, reg1, reg2)
#local ex = (fcond & 8) & ((nan(reg2) || nan(reg1)));
res = zext(un|eq|le);
}
}

2
Ghidra/Processors/V850/data/languages/Helpers/Register.sinc
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@ -33,4 +33,4 @@ define register offset=0x0 size=0x8
_
];
define register offset=0x100 size=0x4 [ PC ]; # offset = 0x100(256) = PreOffset+PreRegister*Size = 128+32*4 = 256
define register offset=0x100 size=0x4 [ PC ]; # offset = 0x100(256) = PreOffset+PreRegister*Size = 128+32*4 = 256

2
Ghidra/Processors/V850/data/languages/Helpers/Tokens.sinc
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@ -102,4 +102,4 @@ define token prep(32)
prep2627 = (26,27)
prep30 = (30,30)
prep31 = (31,31)
;
;

2
Ghidra/Processors/V850/data/languages/Helpers/Variables.sinc
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@ -46,4 +46,4 @@ attach names [fcond2730]
@define Z "PSW[0,1]"
@define EICC "ECR[0,16]"
@define FECC "ECR[16,16]"
@define FECC "ECR[16,16]"

2
Ghidra/Processors/V850/data/languages/Instructions/Arithmetic.sinc
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@ -333,4 +333,4 @@ define pcodeop __saturate;
set_S(R1115);
R2731 = mod;
R1115 = quot;
}
}

2
Ghidra/Processors/V850/data/languages/Instructions/Float.sinc
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@ -471,4 +471,4 @@
:trncf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b00000
{
R2731 = trunc(R1115);
}
}

2
Ghidra/Processors/V850/data/languages/Instructions/Load_Store.sinc
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@ -365,4 +365,4 @@
:zxh R0004 is op0515=0x006 & R0004
{
R0004 = zext(R0004:2);
}
}

2
Ghidra/Processors/V850/data/languages/Instructions/Logic.sinc
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@ -164,4 +164,4 @@
{
local tkn = *:1 R0004;
set_Z(tkn & (1 << R1115));
}
}

2
Ghidra/Processors/V850/data/languages/Instructions/Special.sinc
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@ -375,4 +375,4 @@ define pcodeop __synchronize;
$(ID) = 1;
either_or(PC, (vector5 <= 15), 0x40, 0x50);
call [PC];
}
}

4
Ghidra/Processors/V850/data/languages/V850.cspec
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@ -50,9 +50,11 @@
<register name="r27"/>
<register name="r28"/>
<register name="r29"/>
<register name="ep"/>
<register name="lp"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>
</compiler_spec>

2
Ghidra/Processors/V850/data/languages/V850.ldefs
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@ -13,4 +13,4 @@
<description>Renesas V850 family</description>
<compiler name="default" spec="V850.cspec" id="default"/>
</language>
</language_definitions>
</language_definitions>

2
Ghidra/Processors/V850/data/languages/V850.pspec
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@ -10,4 +10,4 @@
<range space="ram" first="0x0" last="0x20"/>
</volatile>
</processor_spec>
</processor_spec>

2
Ghidra/Processors/V850/data/languages/V850.slaspec
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@ -34,4 +34,4 @@ define space register type=register_space size=4;
@include "Instructions/Float.sinc"
@include "Instructions/Load_Store.sinc"
@include "Instructions/Logic.sinc"
@include "Instructions/Special.sinc"
@include "Instructions/Special.sinc"