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Fix FDIVRP freg,ST0 too

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AltimorTASDK 2024-03-01 04:39:55 -05:00 committed by GitHub
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Ghidra/Processors/x86/data/languages/ia.sinc
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@ -4195,7 +4195,7 @@ define pcodeop fcos;
:FDIVR spec_m64 is vexMode=0 & byte=0xDC; reg_opcode=7 ... & spec_m64 { ST0 = float2float(spec_m64) f/ ST0; }
:FDIVR ST0,freg is vexMode=0 & byte=0xD8; frow=15 & fpage=1 & freg & ST0 { ST0 = freg f/ ST0; }
:FDIVR freg,ST0 is vexMode=0 & byte=0xDC; frow=15 & fpage=0 & freg & ST0 { freg = ST0 f/ freg; }
:FDIVRP freg,ST0 is vexMode=0 & byte=0xDE; frow=15 & fpage=0 & freg & ST0 { freg = freg f/ ST0; fpop(); }
:FDIVRP freg,ST0 is vexMode=0 & byte=0xDE; frow=15 & fpage=0 & freg & ST0 { freg = ST0 f/ freg; fpop(); }
:FDIVRP is vexMode=0 & byte=0xDE; byte=0xF1 { ST1 = ST0 f/ ST1; fpop(); }
:FIDIVR spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=7 ... & spec_m32 { ST0 = int2float(spec_m32) f/ ST0; }
:FIDIVR spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=7 ... & spec_m16 { ST0 = int2float(spec_m16) f/ ST0; }