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Merge branch 'GP-2272_ghidra_PowerPCe500' into patch

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ghidra1 2022-07-22 10:51:58 -04:00
commit dedaaf6cd5
7 changed files with 279 additions and 5 deletions
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4
Ghidra/Processors/PowerPC/certification.manifest
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@ -23,6 +23,10 @@ data/languages/ppc_32_4xx_le.slaspec||GHIDRA||||END|
data/languages/ppc_32_be.cspec||GHIDRA||||END|
data/languages/ppc_32_be.slaspec||GHIDRA||||END|
data/languages/ppc_32_be_Mac.cspec||GHIDRA||||END|
data/languages/ppc_32_e500_be.cspec||GHIDRA||||END|
data/languages/ppc_32_e500_be.slaspec||GHIDRA||||END|
data/languages/ppc_32_e500_le.cspec||GHIDRA||||END|
data/languages/ppc_32_e500_le.slaspec||GHIDRA||||END|
data/languages/ppc_32_le.cspec||GHIDRA||||END|
data/languages/ppc_32_le.slaspec||GHIDRA||||END|
data/languages/ppc_32_mpc8270.pspec||GHIDRA||||END|

36
Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
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@ -158,7 +158,7 @@
<external_name tool="IDA-PRO" name="ppc"/>
<external_name tool="DWARF.register.mapping.file" name="ppc.dwarf"/>
</language>
<language processor="PowerPC"
<language processor="PowerPC"
endian="little"
size="32"
variant="PowerQUICC-III"
@ -173,7 +173,39 @@
<external_name tool="gnu" name="powerpc:MPC8XX"/>
<external_name tool="IDA-PRO" name="ppcl"/>
<external_name tool="DWARF.register.mapping.file" name="ppc.dwarf"/>
</language>
</language>
<language processor="PowerPC"
endian="big"
size="32"
variant="PowerQUICC-III-e500"
version="1.5"
slafile="ppc_32_e500_be.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"
id="PowerPC:BE:32:e500">
<description>PowerQUICC-III e500 32-bit big-endian family</description>
<truncate_space space="ram" size="4"/>
<compiler name="default" spec="ppc_32_e500_be.cspec" id="default"/>
<external_name tool="gnu" name="powerpc:e500"/>
<external_name tool="IDA-PRO" name="ppc"/>
<external_name tool="DWARF.register.mapping.file" name="ppc.dwarf"/>
</language>
<language processor="PowerPC"
endian="little"
size="32"
variant="PowerQUICC-III-e500"
version="1.5"
slafile="ppc_32_e500_le.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"
id="PowerPC:LE:32:e500">
<description>PowerQUICC-III e500 32-bit little-endian family</description>
<truncate_space space="ram" size="4"/>
<compiler name="default" spec="ppc_32_e500_le.cspec" id="default"/>
<external_name tool="gnu" name="powerpc:e500"/>
<external_name tool="IDA-PRO" name="ppc"/>
<external_name tool="DWARF.register.mapping.file" name="ppc.dwarf"/>
</language>
<language processor="PowerPC"
endian="big"
size="32"

80
Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_be.cspec Normal file
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@ -0,0 +1,80 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="ram"/>
</global>
<stackpointer register="r1" space="ram"/>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input pointermax="8">
<pentry minsize="1" maxsize="4">
<register name="_r3"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r4"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r5"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r6"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r7"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r8"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r9"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r10"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="8" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="_r3"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="_r3" piece2="_r4"/>
</pentry>
</output>
<unaffected>
<register name="r14"/>
<register name="r15"/>
<register name="r16"/>
<register name="r17"/>
<register name="r18"/>
<register name="r19"/>
<register name="r20"/>
<register name="r21"/>
<register name="r22"/>
<register name="r23"/>
<register name="r24"/>
<register name="r25"/>
<register name="r26"/>
<register name="r27"/>
<register name="r28"/>
<register name="r29"/>
<register name="r30"/>
<register name="r31"/>
<register name="r1"/>
<register name="cr4"/>
</unaffected>
</prototype>
</default_proto>
<callfixup name="get_pc_thunk_lr">
<pcode>
<body><![CDATA[
LR = inst_dest + 4;
]]></body>
</pcode>
</callfixup>
</compiler_spec>

29
Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_be.slaspec Normal file
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@ -0,0 +1,29 @@
# SLA specification file for IBM PowerPC e500 series core
# NOTE: This language variant includes some registers and instructions not supported
# by the actual processor (e.g., floating pointer registers and associated instructions).
# The actual processor only supports a subset of the registers and instructions implemented.
@define E500
@define ENDIAN "big"
# Although a 32-bit architecture, 64-bit general purpose registers are supported.
# Language has been modeled using a 64-bit implementation with a 32-bit truncated
# memory space (see ldefs).
@define REGISTER_SIZE "8"
@define BIT_64 "64"
@define EATRUNC "ea"
@define CTR_OFFSET "32"
@define NoLegacyIntegerMultiplyAccumulate
@include "ppc_common.sinc"
@include "quicciii.sinc"
@include "evx.sinc"
@include "SPEF_SCR.sinc"
@include "SPE_EFSD.sinc"
@include "SPE_EFV.sinc"

79
Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.cspec Normal file
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@ -0,0 +1,79 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="ram"/>
</global>
<stackpointer register="r1" space="ram"/>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input pointermax="8">
<pentry minsize="1" maxsize="4">
<register name="_r3"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r4"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r5"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r6"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r7"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r8"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r9"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="_r10"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="8" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="_r3"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="_r4" piece2="_r3"/>
</pentry>
</output>
<unaffected>
<register name="r14"/>
<register name="r15"/>
<register name="r16"/>
<register name="r17"/>
<register name="r18"/>
<register name="r19"/>
<register name="r20"/>
<register name="r21"/>
<register name="r22"/>
<register name="r23"/>
<register name="r24"/>
<register name="r25"/>
<register name="r26"/>
<register name="r27"/>
<register name="r28"/>
<register name="r29"/>
<register name="r30"/>
<register name="r31"/>
<register name="r1"/>
</unaffected>
</prototype>
</default_proto>
<callfixup name="get_pc_thunk_lr">
<pcode>
<body><![CDATA[
LR = inst_dest + 4;
]]></body>
</pcode>
</callfixup>
</compiler_spec>

29
Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.slaspec Normal file
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@ -0,0 +1,29 @@
# SLA specification file for IBM PowerPC e500 series core
# NOTE: This language variant includes some registers and instructions not supported
# by the actual processor (e.g., floating pointer registers and associated instructions).
# The actual processor only supports a subset of the registers and instructions implemented.
@define E500
@define ENDIAN "little"
# Although a 32-bit architecture, 64-bit general purpose registers are supported.
# Language has been modeled using a 64-bit implementation with a 32-bit truncated
# memory space (see ldefs).
@define REGISTER_SIZE "8"
@define BIT_64 "64"
@define EATRUNC "ea"
@define CTR_OFFSET "32"
@define NoLegacyIntegerMultiplyAccumulate
@include "ppc_common.sinc"
@include "quicciii.sinc"
@include "evx.sinc"
@include "SPEF_SCR.sinc"
@include "SPE_EFSD.sinc"
@include "SPE_EFV.sinc"

27
Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
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@ -18,6 +18,24 @@ define space register type=register_space size=4;
define register offset=0 size=$(REGISTER_SIZE) [
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 ];
@ifdef E500
# Define 4-byte general purpose sub-registers (LSB) to be used by E500 compiler specification
# which must restrict parameter/return passing to low 4-bytes of the 8-byte general purpose registers.
@if ENDIAN == "big"
define register offset=0 size=4 [
_ _r0 _ _r1 _ _r2 _ _r3 _ _r4 _ _r5 _ _r6 _ _r7
_ _r8 _ _r9 _ _r10 _ _r11 _ _r12 _ _r13 _ _r14 _ _r15
_ _r16 _ _r17 _ _r18 _ _r19 _ _r20 _ _r21 _ _r22 _ _r23
_ _r24 _ _r25 _ _r26 _ _r27 _ _r28 _ _r29 _ _r30 _ _r31 ];
@else
define register offset=0 size=4 [
_r0 _ _r1 _ _r2 _ _r3 _ _r4 _ _r5 _ _r6 _ _r7 _
_r8 _ _r9 _ _r10 _ _r11 _ _r12 _ _r13 _ _r14 _ _r15 _
_r16 _ _r17 _ _r18 _ _r19 _ _r20 _ _r21 _ _r22 _ _r23 _
_r24 _ _r25 _ _r26 _ _r27 _ _r28 _ _r29 _ _r30 _ _r31 _ ];
@endif
@endif
# XER flags
define register offset=0x400 size=1 [ xer_so xer_ov xer_ov32 xer_ca xer_ca32 xer_count ];
@ -1730,7 +1748,8 @@ macro loadRegisterPartial(reg, ea, sa) {
macro storeRegister(reg, ea) {
@ifdef BIT_64
*:4(ea) = reg:4;
tmp:8 = reg; # workaround
*:4(ea) = tmp:4;
@else
*:4(ea) = reg;
@endif
@ -1739,7 +1758,8 @@ macro storeRegister(reg, ea) {
macro storeReg(reg) {
@ifdef BIT_64
*:4(tea) = reg:4;
tmp:8 = reg; # workaround
*:4(tea) = tmp:4;
@else
*:4(tea) = reg;
@endif
@ -1748,7 +1768,8 @@ macro storeReg(reg) {
macro storeRegisterPartial(reg, ea, sa) {
@ifdef BIT_64
*:4(ea) = reg:4;
tmp:8 = reg; # workaround
*:4(ea) = tmp:4;
@else
*:4(ea) = reg;
@endif