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'origin/GP-1716_emteere_HC12_support--SQUASHED' into patch
(Closes #1570, Closes #4016)
This commit is contained in:
Ryan Kurtz 2022-07-25 01:14:44 -04:00
commit d940355bde
16 changed files with 1326 additions and 871 deletions
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6
Ghidra/Processors/HCS12/certification.manifest
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@ -1,11 +1,17 @@
##VERSION: 2.0
Module.manifest||GHIDRA||||END|
data/build.xml||GHIDRA||||END|
data/languages/HC12.cspec||GHIDRA||||END|
data/languages/HC12.pspec||GHIDRA||||END|
data/languages/HC12.slaspec||GHIDRA||||END|
data/languages/HCS12.cspec||GHIDRA||||END|
data/languages/HCS12.ldefs||GHIDRA||||END|
data/languages/HCS12.opinion||GHIDRA||||END|
data/languages/HCS12.pspec||GHIDRA||||END|
data/languages/HCS12.slaspec||GHIDRA||||END|
data/languages/HCS12X.cspec||GHIDRA||||END|
data/languages/HCS12X.pspec||GHIDRA||||END|
data/languages/HCS12X.slaspec||GHIDRA||||END|
data/languages/HCS_HC12.sinc||GHIDRA||||END|
data/languages/XGATE.sinc||GHIDRA||||END|
data/manuals/HCS12.idx||GHIDRA||||END|

58
Ghidra/Processors/HCS12/data/languages/HC12.cspec Normal file
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@ -0,0 +1,58 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization> <!-- These tags need to be verified -->
<absolute_max_alignment value="0" />
<machine_alignment value="1" />
<default_alignment value="1" />
<pointer_size value="2" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
</data_organization>
<global>
<range space="RAM"/>
</global>
<stackpointer register="SP" space="RAM" growth="negative"/>
<default_proto>
<prototype name="__asmA" extrapop="2" stackshift="2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="B"/>
</pentry>
<pentry minsize="2" maxsize="2">
<register name="D"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IY"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="1">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="D"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>

75
Ghidra/Processors/HCS12/data/languages/HC12.pspec Normal file
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@ -0,0 +1,75 @@
<?xml version="1.0" encoding="UTF-8"?>
<!--
This is the processor specification for the MC9S12C and MC9S12GC processor families.
It is based upon the MC9S12C128 and MC9S12GC128 variants.
-->
<processor_spec>
<programcounter register="PC"/>
<default_symbols>
<symbol name="VECTOR_Reset" address="FFFE" entry="true" type="code_ptr"/>
<symbol name="VECTOR_ClockMonitorFailReset" address="FFFC" entry="true" type="code_ptr"/>
<symbol name="VECTOR_COPFailureReset" address="FFFA" entry="true" type="code_ptr"/>
<symbol name="VECTOR_UnimplementedInstructionTrap" address="FFF8" entry="true" type="code_ptr"/>
<symbol name="VECTOR_SWI" address="FFF6" entry="true" type="code_ptr"/>
<symbol name="VECTOR_XIRQ" address="FFF4" entry="true" type="code_ptr"/>
<symbol name="VECTOR_IRQ" address="FFF2" entry="true" type="code_ptr"/>
<symbol name="VECTOR_RealTimeInterrupt" address="FFF0" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel0" address="FFEE" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel1" address="FFEC" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel2" address="FFEA" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel3" address="FFE8" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel4" address="FFE6" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel5" address="FFE4" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel6" address="FFE2" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel7" address="FFE0" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerOverflow" address="FFDE" entry="true" type="code_ptr"/>
<symbol name="VECTOR_PulseAccumulatorAOverflow" address="FFDC" entry="true" type="code_ptr"/>
<symbol name="VECTOR_PulseAccumulatorInputEdge" address="FFDA" entry="true" type="code_ptr"/>
<symbol name="VECTOR_SPI" address="FFD8" entry="true" type="code_ptr"/>
<symbol name="VECTOR_SCI" address="FFD6" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFD4" address="FFD4" entry="true" type="code_ptr"/>
<symbol name="VECTOR_ATD" address="FFD2" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFD0" address="FFD0" entry="true" type="code_ptr"/>
<symbol name="VECTOR_PortJ" address="FFCE" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFCC" address="FFCC" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFCA" address="FFCA" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFC8" address="FFC8" entry="true" type="code_ptr"/>
<symbol name="VECTOR_CRG_PLL_Lock" address="FFC6" entry="true" type="code_ptr"/>
<symbol name="VECTOR_CRGSelfClockMode" address="FFC4" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFC2" address="FFC2" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFC0" address="FFC0" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFBE" address="FFBE" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFBC" address="FFBC" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFBA" address="FFBA" entry="true" type="code_ptr"/>
<symbol name="VECTOR_FLASH" address="FFB8" entry="true" type="code_ptr"/>
<symbol name="VECTOR_CANwake-up" address="FFB6" entry="true" type="code_ptr"/>
<symbol name="VECTOR_CANerrors" address="FFB4" entry="true" type="code_ptr"/>
<symbol name="VECTOR_CANreceive" address="FFB2" entry="true" type="code_ptr"/>
<symbol name="VECTOR_CANtransmit" address="FFB0" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFAE" address="FFAE" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFAC" address="FFAC" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFAA" address="FFAA" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFA8" address="FFA8" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFA6" address="FFA6" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFA4" address="FFA4" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFA2" address="FFA2" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFA0" address="FFA0" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF9E" address="FF9E" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF9C" address="FF9C" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF9A" address="FF9A" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF98" address="FF98" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF96" address="FF96" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF94" address="FF94" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF92" address="FF92" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF90" address="FF90" entry="true" type="code_ptr"/>
<symbol name="VECTOR_PortP" address="FF8E" entry="true" type="code_ptr"/>
<symbol name="VECTOR_PWM_EmergencyShutdown" address="FF8C" entry="true" type="code_ptr"/>
<symbol name="VECTOR_VREG_LVI" address="FF8A" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF88" address="FF88" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF86" address="FF86" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF84" address="FF84" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF82" address="FF82" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF80" address="FF80" entry="true" type="code_ptr"/>
</default_symbols>
</processor_spec>

9
Ghidra/Processors/HCS12/data/languages/HC12.slaspec Normal file
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@ -0,0 +1,9 @@
# sleigh specification file for Freescale HC12 (68HC12)
@define HC12 "1"
@define SIZE "2"
@define MAXFLASHPage "0xFF"
@include "HCS_HC12.sinc"

62
Ghidra/Processors/HCS12/data/languages/HCS12.cspec
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@ -17,9 +17,9 @@
</data_organization>
<global>
<range space="RAM" first="0x00" last="0x0f"/>
<range space="RAM" first="0x11" last="0x15"/>
<range space="RAM" first="0x18" last="0x2f"/>
<!-- The following cut out page register so that the decompiler can use them as registers -->
<range space="RAM" first="0x00" last="0x2f"/>
<!-- PPAGE -->
<range space="RAM" first="0x31" last="0xffff"/>
</global>
@ -54,14 +54,11 @@
</output>
<unaffected>
<register name="SP"/>
<register name="EPAGE"/>
<register name="PPAGE"/>
<register name="RPAGE"/>
<register name="GPAGE"/>
</unaffected>
</prototype>
</default_proto>
<prototype name="__asmA_longcall" extrapop="3" stackshift="3" strategy="register">
<input>
@ -91,62 +88,15 @@
</output>
<unaffected>
<register name="SP"/>
<register name="EPAGE"/>
<register name="PPAGE"/>
<register name="RPAGE"/>
<register name="GPAGE"/>
</unaffected>
</prototype>
<resolveprototype name="__asmA_longcall/__asmA">
<model name="__asmA_longcall"/> <!-- The default case -->
<model name="__asmA"/>
</resolveprototype>
<eval_current_prototype name="__asmA_longcall/__asmA"/>
<prototype name="__asm_xgate" extrapop="0" stackshift="0" strategy="register">
<input>
<pentry minsize="1" maxsize="2">
<register name="R2"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="R3"/>
</pentry>
<pentry minsize="3" maxsize="4">
<addr space="join" piece1="R2" piece2="R3"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="R4"/>
</pentry>
<pentry minsize="3" maxsize="4">
<addr space="join" piece1="R3" piece2="R4"/>
</pentry>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="R2"/>
</pentry>
<pentry minsize="4" maxsize="4">
<addr space="join" piece1="R2" piece2="R3"/>
</pentry>
</output>
<unaffected>
<register name="R1"/>
<register name="SP"/>
<register name="R7"/>
<register name="PPAGE"/>
</unaffected>
<pcode inject="uponentry">
<!-- Special injection at start of function, really R7 is the stack pointer, but
decompiler can only handle one stack pointer. (Hack) -->
<body>
R7 = SP;
</body>
</pcode>
</prototype>
<eval_current_prototype name="__asmA_longcall/__asmA"/>
</compiler_spec>

50
Ghidra/Processors/HCS12/data/languages/HCS12.ldefs
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@ -1,17 +1,59 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="HCS12"
<language processor="HC-12"
endian="big"
size="16"
variant="default"
version="2.0"
slafile="HC12.sla"
processorspec="HC12.pspec"
manualindexfile="../manuals/HCS12.idx"
id="HC-12:BE:16:default">
<description>HC12 Microcontroller Family</description>
<compiler name="default" spec="HC12.cspec" id="default"/>
<external_name tool="gnu" name="m68hc12"/>
</language>
<language processor="HCS-12"
endian="big"
size="24"
variant="default"
version="1.0"
version="2.0"
slafile="HCS12.sla"
processorspec="HCS12.pspec"
manualindexfile="../manuals/HCS12.idx"
id="HCS12:BE:24:default">
<description>HCS12X Microcontroller Family</description>
id="HCS-12:BE:24:default">
<description>HCS12 Microcontroller Family</description>
<compiler name="default" spec="HCS12.cspec" id="default"/>
<external_name tool="gnu" name="m9s12x"/>
</language>
<language processor="HCS-12X"
endian="big"
size="24"
variant="default"
version="2.0"
slafile="HCS12X.sla"
processorspec="HCS12X.pspec"
manualindexfile="../manuals/HCS12.idx"
id="HCS-12X:BE:24:default">
<description>HCS12X Microcontroller Family</description>
<compiler name="default" spec="HCS12X.cspec" id="default"/>
<external_name tool="gnu" name="m9s12x"/>
</language>
<!-- deprecated HCS12, which was equivalent to HCS12X, allows opening of existing Programs which use the old ID -->
<language processor="HCS-12X"
deprecated="true"
endian="big"
size="24"
variant="default"
version="2.0"
slafile="HCS12X.sla"
processorspec="HCS12X.pspec"
manualindexfile="../manuals/HCS12.idx"
id="HCS12:BE:24:default">
<description>HCS12X Microcontroller Family</description>
<compiler name="default" spec="HCS12X.cspec" id="default"/>
<external_name tool="gnu" name="m9s12x"/>
</language>
</language_definitions>

4
Ghidra/Processors/HCS12/data/languages/HCS12.opinion
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@ -1,6 +1,8 @@
<opinions>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="53" processor="HCS12" endian="big" size="24" variant="default"/>
<constraint primary="53" processor="HCS-12" endian="big" size="24" variant="default"/>
<constraint primary="53" processor="HC-12" endian="big" size="16" variant="default"/>
<constraint primary="53" processor="HCS-12X" endian="big" size="24" variant="default"/>
</constraint>
</opinions>

4
Ghidra/Processors/HCS12/data/languages/HCS12.pspec
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@ -22,9 +22,7 @@
<context_data>
<tracked_set space="RAM">
<set name="PPAGE" val="0xfe"/>
<set name="RPAGE" val="0xfd"/>
<set name="EPAGE" val="0xfe"/>
<set name="PPAGE" val="0x3e"/>
</tracked_set>
</context_data>
<default_symbols>

6
Ghidra/Processors/HCS12/data/languages/HCS12.slaspec
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@ -1,9 +1,9 @@
# sleigh specification file for Freescale HCS12 (68HCS12)
@define HCS12 "1"
@define HCS12X "1"
@define SIZE "3"
@define MAXFLASHPage "0xFF"
@include "HCS_HC12.sinc"
@include "XGATE.sinc"
@include "HCS_HC12.sinc"

156
Ghidra/Processors/HCS12/data/languages/HCS12X.cspec Normal file
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@ -0,0 +1,156 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization> <!-- These tags need to be verified -->
<absolute_max_alignment value="0" />
<machine_alignment value="1" />
<default_alignment value="1" />
<pointer_size value="2" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
</data_organization>
<global>
<!-- The following cut out page register so that the decompiler can use them as registers -->
<range space="RAM" first="0x00" last="0x0f"/>
<!-- GPAGE -->
<range space="RAM" first="0x11" last="0x15"/>
<!-- EPAGE, RPAGE -->
<range space="RAM" first="0x18" last="0x2f"/>
<!-- PPAGE -->
<range space="RAM" first="0x31" last="0xffff"/>
</global>
<stackpointer register="SP" space="RAM" growth="negative"/>
<default_proto>
<prototype name="__asmA" extrapop="2" stackshift="2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="B"/>
</pentry>
<pentry minsize="2" maxsize="2">
<register name="D"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IY"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="1">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="D"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="EPAGE"/>
<register name="PPAGE"/>
<register name="RPAGE"/>
<register name="GPAGE"/>
</unaffected>
</prototype>
</default_proto>
<prototype name="__asmA_longcall" extrapop="3" stackshift="3" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="B"/>
</pentry>
<pentry minsize="2" maxsize="2">
<register name="D"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IY"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="1">
<addr offset="3" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="D"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="EPAGE"/>
<register name="PPAGE"/>
<register name="RPAGE"/>
<register name="GPAGE"/>
</unaffected>
</prototype>
<resolveprototype name="__asmA_longcall/__asmA">
<model name="__asmA_longcall"/> <!-- The default case -->
<model name="__asmA"/>
</resolveprototype>
<eval_current_prototype name="__asmA_longcall/__asmA"/>
<prototype name="__asm_xgate" extrapop="0" stackshift="0" strategy="register">
<input>
<pentry minsize="1" maxsize="2">
<register name="R2"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="R3"/>
</pentry>
<pentry minsize="3" maxsize="4">
<addr space="join" piece1="R2" piece2="R3"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="R4"/>
</pentry>
<pentry minsize="3" maxsize="4">
<addr space="join" piece1="R3" piece2="R4"/>
</pentry>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="R2"/>
</pentry>
<pentry minsize="4" maxsize="4">
<addr space="join" piece1="R2" piece2="R3"/>
</pentry>
</output>
<unaffected>
<register name="R1"/>
<register name="SP"/>
<register name="R7"/>
<register name="PPAGE"/>
</unaffected>
<pcode inject="uponentry">
<!-- Special injection at start of function, really R7 is the stack pointer, but
decompiler can only handle one stack pointer. (Hack) -->
<body>
R7 = SP;
</body>
</pcode>
</prototype>
</compiler_spec>

96
Ghidra/Processors/HCS12/data/languages/HCS12X.pspec Normal file
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@ -0,0 +1,96 @@
<?xml version="1.0" encoding="UTF-8"?>
<!--
This is the processor specification for the MC9S12C and MC9S12GC processor families.
It is based upon the MC9S12C128 and MC9S12GC128 variants.
-->
<processor_spec>
<programcounter register="PC"/>
<segmentop space="RAM" userop="segment" farpointer="no">
<pcode>
<input name="base" size="3"/>
<input name="inner" size="2"/>
<output name="res" size="3"/>
<body><![CDATA[
res = base ^ zext(inner);
]]></body>
</pcode>
<constresolve>
<register name="physPage"/>
</constresolve>
</segmentop>
<context_data>
<tracked_set space="RAM">
<set name="PPAGE" val="0xfe"/>
<set name="RPAGE" val="0xfd"/>
<set name="EPAGE" val="0xfe"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="VECTOR_Reset" address="FFFE" entry="true" type="code_ptr"/>
<symbol name="VECTOR_ClockMonitorFailReset" address="FFFC" entry="true" type="code_ptr"/>
<symbol name="VECTOR_COPFailureReset" address="FFFA" entry="true" type="code_ptr"/>
<symbol name="VECTOR_UnimplementedInstructionTrap" address="FFF8" entry="true" type="code_ptr"/>
<symbol name="VECTOR_SWI" address="FFF6" entry="true" type="code_ptr"/>
<symbol name="VECTOR_XIRQ" address="FFF4" entry="true" type="code_ptr"/>
<symbol name="VECTOR_IRQ" address="FFF2" entry="true" type="code_ptr"/>
<symbol name="VECTOR_RealTimeInterrupt" address="FFF0" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel0" address="FFEE" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel1" address="FFEC" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel2" address="FFEA" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel3" address="FFE8" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel4" address="FFE6" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel5" address="FFE4" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel6" address="FFE2" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerChannel7" address="FFE0" entry="true" type="code_ptr"/>
<symbol name="VECTOR_StandardTimerOverflow" address="FFDE" entry="true" type="code_ptr"/>
<symbol name="VECTOR_PulseAccumulatorAOverflow" address="FFDC" entry="true" type="code_ptr"/>
<symbol name="VECTOR_PulseAccumulatorInputEdge" address="FFDA" entry="true" type="code_ptr"/>
<symbol name="VECTOR_SPI" address="FFD8" entry="true" type="code_ptr"/>
<symbol name="VECTOR_SCI" address="FFD6" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFD4" address="FFD4" entry="true" type="code_ptr"/>
<symbol name="VECTOR_ATD" address="FFD2" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFD0" address="FFD0" entry="true" type="code_ptr"/>
<symbol name="VECTOR_PortJ" address="FFCE" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFCC" address="FFCC" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFCA" address="FFCA" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFC8" address="FFC8" entry="true" type="code_ptr"/>
<symbol name="VECTOR_CRG_PLL_Lock" address="FFC6" entry="true" type="code_ptr"/>
<symbol name="VECTOR_CRGSelfClockMode" address="FFC4" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFC2" address="FFC2" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFC0" address="FFC0" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFBE" address="FFBE" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFBC" address="FFBC" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFBA" address="FFBA" entry="true" type="code_ptr"/>
<symbol name="VECTOR_FLASH" address="FFB8" entry="true" type="code_ptr"/>
<symbol name="VECTOR_CANwake-up" address="FFB6" entry="true" type="code_ptr"/>
<symbol name="VECTOR_CANerrors" address="FFB4" entry="true" type="code_ptr"/>
<symbol name="VECTOR_CANreceive" address="FFB2" entry="true" type="code_ptr"/>
<symbol name="VECTOR_CANtransmit" address="FFB0" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFAE" address="FFAE" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFAC" address="FFAC" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFAA" address="FFAA" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFA8" address="FFA8" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFA6" address="FFA6" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFA4" address="FFA4" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFA2" address="FFA2" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FFA0" address="FFA0" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF9E" address="FF9E" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF9C" address="FF9C" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF9A" address="FF9A" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF98" address="FF98" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF96" address="FF96" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF94" address="FF94" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF92" address="FF92" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF90" address="FF90" entry="true" type="code_ptr"/>
<symbol name="VECTOR_PortP" address="FF8E" entry="true" type="code_ptr"/>
<symbol name="VECTOR_PWM_EmergencyShutdown" address="FF8C" entry="true" type="code_ptr"/>
<symbol name="VECTOR_VREG_LVI" address="FF8A" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF88" address="FF88" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF86" address="FF86" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF84" address="FF84" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF82" address="FF82" entry="true" type="code_ptr"/>
<symbol name="VECTOR_Reserved_FF80" address="FF80" entry="true" type="code_ptr"/>
</default_symbols>
</processor_spec>

10
Ghidra/Processors/HCS12/data/languages/HCS12X.slaspec Normal file
View File

@ -0,0 +1,10 @@
# sleigh specification file for Freescale HCS12 (68HCS12)
@define HCS12 "1"
@define HCS12X "1"
@define SIZE "3"
@define MAXFLASHPage "0xFF"
@include "HCS_HC12.sinc"
@include "XGATE.sinc"

1436
Ghidra/Processors/HCS12/data/languages/HCS_HC12.sinc
View File

File diff suppressed because it is too large Load Diff

4
Ghidra/Processors/HCS12/data/languages/XGATE.sinc
View File

@ -139,10 +139,10 @@ macro computePage(addr) {
#rel9 defined in HCS_HC12.sinc
# range -256 through +255
with : XGATE=1 {
rel9: reloc is immrel8 [ reloc = inst_next + (immrel8 * 2); ] { export * reloc; }
rel9: reloc is immrel8 [ reloc = inst_next + (immrel8 * 2); ] { export *:1 reloc; }
# range -512 through +512
rel10: reloc is immrel9 [ reloc = inst_next + (immrel9 * 2); ] { export * reloc; }
rel10: reloc is immrel9 [ reloc = inst_next + (immrel9 * 2); ] { export *:1 reloc; }
rd : reg8 is reg8 { export reg8; }

165
Ghidra/Processors/HCS12/src/main/java/ghidra/app/plugin/core/analysis/HCS12ConstantAnalyzer.java
View File

@ -1,165 +0,0 @@
/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.app.plugin.core.analysis;
import ghidra.program.model.address.Address;
import ghidra.program.model.address.AddressSetView;
import ghidra.program.model.lang.Processor;
import ghidra.program.model.listing.Instruction;
import ghidra.program.model.listing.Program;
import ghidra.program.model.pcode.PcodeOp;
import ghidra.program.model.symbol.RefType;
import ghidra.program.model.symbol.SourceType;
import ghidra.program.util.ContextEvaluator;
import ghidra.program.util.SymbolicPropogator;
import ghidra.program.util.VarnodeContext;
import ghidra.util.exception.CancelledException;
import ghidra.util.task.TaskMonitor;
public class HCS12ConstantAnalyzer extends ConstantPropagationAnalyzer {
private final static String PROCESSOR_NAME = "HCS12";
public HCS12ConstantAnalyzer() {
super(PROCESSOR_NAME);
}
@Override
public boolean canAnalyze(Program program) {
boolean canAnalyze = program.getLanguage().getProcessor()
.equals(Processor.findOrPossiblyCreateProcessor(PROCESSOR_NAME));
if (!canAnalyze) {
return false;
}
return true;
}
private long hcs12TranslatePagedAddress(long addrWordOffset) {
long page = (addrWordOffset >> 16) & 0xff;
long addr = addrWordOffset & 0xffff;
// Register address
if ( (addr & 0xfC00) == 0x0) {
return addr;
}
// EPage address
if ((addr & 0xfc00) ==0x800) {
return 0x100000 | ((page << 10) | (addr & 0x3ff));
}
// EPage FF fixed address
if ((addr & 0xfc00) ==0xC00) {
return (0x4FF << 10) | (addr & 0x3ff);
}
// RPage address
if ((addr & 0xf000) ==0x1000) {
return (page << 12) | (addr & 0xfff);
}
// RPage FE fixed address
if ((addr & 0xf000) ==0x2000) {
return (0xFE << 12) | (addr & 0xfff);
}
// RPage FF fixed address
if ((addr & 0xf000) ==0x3000) {
return (0xFF << 12) | (addr & 0xfff);
}
// PPage FD fixed address
if ((addr & 0xc000) ==0x4000) {
return 0x400000 | (0xFD << 14) | (addr & 0x3fff);
}
// PPage address
if ((addr & 0xc000) ==0x8000) {
return 0x400000 | (page << 14) | (addr & 0x3fff);
}
// PPage FF fixed address
if ((addr & 0xc000) ==0xC000) {
return 0x400000 | (0xFF << 14) | (addr & 0x3fff);
}
return addr;
}
@Override
public AddressSetView flowConstants(final Program program, Address flowStart, AddressSetView flowSet,
final SymbolicPropogator symEval, final TaskMonitor monitor) throws CancelledException {
// follow all flows building up context
// use context to fill out addresses on certain instructions
ContextEvaluator eval = new ConstantPropagationContextEvaluator(trustWriteMemOption) {
@Override
public boolean evaluateReference(VarnodeContext context, Instruction instr, int pcodeop,
Address address, int size, RefType refType) {
if ((refType.isRead() || refType.isWrite()) &&
adjustPagedAddress(instr, address, refType)) {
return false;
}
return super.evaluateReference(context, instr, pcodeop, address, size, refType);
}
@Override
public Address evaluateConstant(VarnodeContext context, Instruction instr, int pcodeop, Address constant,
int size, RefType refType) {
// TODO Auto-generated method stub
return super.evaluateConstant(context, instr, pcodeop, constant, size, refType);
}
private boolean adjustPagedAddress(Instruction instr, Address address, RefType refType) {
PcodeOp[] pcode = instr.getPcode();
for (PcodeOp op : pcode) {
int numin = op.getNumInputs();
if (numin < 1) {
continue;
}
if (op.getOpcode() != PcodeOp.CALLOTHER) {
continue;
}
String opName = instr.getProgram().getLanguage().getUserDefinedOpName(
(int) op.getInput(0).getOffset());
if (opName != null && opName.equals("segment") && numin > 2) {
// assume this is a poorly created segment op addr
long high = address.getOffset() >> 16;
long low = address.getOffset() & 0xffff;
address = address.getNewAddress((high << 14) | (low & 0x3fff));
makeReference(instr, address, refType);
return true;
}
}
return false;
}
// handle the reference on the correct read or write operand
private void makeReference(Instruction instr, Address address, RefType refType) {
int index = (refType.isRead() ? 1 : 0);
instr.addOperandReference(index, address, refType, SourceType.ANALYSIS);
}
};
return symEval.flowConstants(flowStart, flowSet, eval, true, monitor);
}
}

56
Ghidra/Processors/HCS12/src/main/java/ghidra/app/util/bin/format/elf/extend/HCS12X_ElfExtension.java
View File

@ -39,14 +39,22 @@ public class HCS12X_ElfExtension extends ElfExtension {
@Override
public boolean canHandle(ElfLoadHelper elfLoadHelper) {
Language language = elfLoadHelper.getProgram().getLanguage();
return canHandle(elfLoadHelper.getElfHeader()) &&
"HCS12".equals(language.getProcessor().toString());
boolean isSpecialHCSMemory = isHCS12(language) || isHCS12X(language);
return canHandle(elfLoadHelper.getElfHeader()) && isSpecialHCSMemory;
}
@Override
public String getDataTypeSuffix() {
return "_HCS12";
}
private boolean isHCS12(Language language) {
return "HCS-12".equals(language.getProcessor().toString());
}
private boolean isHCS12X(Language language) {
return "HCS-12X".equals(language.getProcessor().toString());
}
@Override
public Address getPreferredSegmentAddress(ElfLoadHelper elfLoadHelper,
@ -62,7 +70,7 @@ public class HCS12X_ElfExtension extends ElfExtension {
addrWordOffset += elfLoadHelper.getImageBaseWordAdjustmentOffset();
}
addrWordOffset = hcs12TranslatePagedAddress(addrWordOffset);
addrWordOffset = hcs12TranslatePagedAddress(elfLoadHelper, addrWordOffset);
return space.getTruncatedAddress(addrWordOffset, true);
}
@ -81,12 +89,46 @@ public class HCS12X_ElfExtension extends ElfExtension {
addrWordOffset += elfLoadHelper.getImageBaseWordAdjustmentOffset();
}
addrWordOffset = hcs12TranslatePagedAddress(addrWordOffset);
addrWordOffset = hcs12TranslatePagedAddress(elfLoadHelper, addrWordOffset);
return space.getTruncatedAddress(addrWordOffset, true);
}
private long hcs12TranslatePagedAddress(long addrWordOffset) {
private long hcs12TranslatePagedAddress(ElfLoadHelper elfLoaderHelper, long addrWordOffset) {
Language lang = elfLoaderHelper.getProgram().getLanguage();
if (isHCS12X(lang)) {
return hcs12xTranslatePagedAddress(addrWordOffset);
}
long page = (addrWordOffset >> 16) & 0xff;
long addr = addrWordOffset & 0xffff;
// PPage 3D address
if ((addr & 0xc000) == 0x0000) {
return ((0x3d << 14) | (addr & 0x3fff));
}
// PPage 3E address
if ((addr & 0xc000) == 0x4000) {
return (0x3e << 14) | (addr & 0x3fff);
}
// PPAGE
if ((addr & 0xc000) == 0x8000) {
return (page << 14) | (addr & 0x3fff);
}
// PPAGE 3F address
if ((addr & 0xc000) == 0xc000) {
return (0x3f << 14) | (addr & 0x3fff);
}
return addr;
}
private long hcs12xTranslatePagedAddress(long addrWordOffset) {
long page = (addrWordOffset >> 16) & 0xff;
@ -148,11 +190,9 @@ public class HCS12X_ElfExtension extends ElfExtension {
return address;
}
String symName = elfSymbol.getNameAsString();
long laddr = address.getOffset();
laddr = hcs12TranslatePagedAddress(laddr);
laddr = hcs12TranslatePagedAddress(elfLoadHelper, laddr);
Address mappedAddr = address.getNewAddress(laddr);