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RISC-V processor

Browse Source 
[riscv] Added context register for extensions

[riscv] missed a define in refactor

[riscv] got 100% on RV32IMC

[riscv] Add throw away script to generate SLEIGH

[riscv]

Fixes from SleighDevTools

- R4-type were using a bad bit pattern that broke the rs3 operand
- mul had a copy/paste typo that ignored the rs2 operand
- bad define guard for compressesed instruction
This commit is contained in:
mumbel 2019-08-21 18:36:45 -05:00
parent 01c43efb2c
commit d7e51ee515
60 changed files with 9735 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

0
Ghidra/Processors/RISCV/Module.manifest Normal file
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11
Ghidra/Processors/RISCV/build.gradle Normal file
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apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle"
apply from: "$rootProject.projectDir/gradle/javaProject.gradle"
apply from: "$rootProject.projectDir/gradle/processorProject.gradle"
apply from: "$rootProject.projectDir/gradle/jacocoProject.gradle"
apply from: "$rootProject.projectDir/gradle/javaTestProject.gradle"
apply plugin: 'eclipse'
eclipse.project.name = 'Processors RISCV'
dependencies {
compile project(':Base')
}

37
Ghidra/Processors/RISCV/certification.manifest Normal file
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##VERSION: 2.0
Module.manifest||GHIDRA||||END|
build.gradle||GHIDRA||||END|
data/languages/riscv.ldefs||GHIDRA||||END|
data/languages/riscv.opinion||GHIDRA||||END|
data/languages/riscv.pspec||GHIDRA||||END|
data/languages/riscv32.cspec||GHIDRA||||END|
data/languages/riscv64.cspec||GHIDRA||||END|
data/languages/riscv32.dwarf||GHIDRA||||END|
data/languages/riscv64.dwarf||GHIDRA||||END|
data/languages/RV32I.slaspec||GHIDRA||||END|
data/languages/RV32IC.slaspec||GHIDRA||||END|
data/languages/RV32G.slaspec||GHIDRA||||END|
data/languages/RV32GC.slaspec||GHIDRA||||END|
data/languages/RV64I.slaspec||GHIDRA||||END|
data/languages/RV64IC.slaspec||GHIDRA||||END|
data/languages/RV64G.slaspec||GHIDRA||||END|
data/languages/RV64GC.slaspec||GHIDRA||||END|
data/languages/riscv.instr.sinc||GHIDRA||||END|
data/languages/riscv.reg.sinc||GHIDRA||||END|
data/languages/riscv.table.sinc||GHIDRA||||END|
data/languages/riscv.csr.sinc||GHIDRA||||END|
data/languages/riscv.priv.sinc||GHIDRA||||END|
data/languages/riscv.rv32a.sinc||GHIDRA||||END|
data/languages/riscv.rv32d.sinc||GHIDRA||||END|
data/languages/riscv.rv32f.sinc||GHIDRA||||END|
data/languages/riscv.rv32i.sinc||GHIDRA||||END|
data/languages/riscv.rv32m.sinc||GHIDRA||||END|
data/languages/riscv.rv32q.sinc||GHIDRA||||END|
data/languages/riscv.rv64a.sinc||GHIDRA||||END|
data/languages/riscv.rv64d.sinc||GHIDRA||||END|
data/languages/riscv.rv64f.sinc||GHIDRA||||END|
data/languages/riscv.rv64i.sinc||GHIDRA||||END|
data/languages/riscv.rv64m.sinc||GHIDRA||||END|
data/languages/riscv.rv64q.sinc||GHIDRA||||END|
data/languages/riscv.rvc.sinc||GHIDRA||||END|
data/languages/riscv.zi.sinc||GHIDRA||||END|

11
Ghidra/Processors/RISCV/data/languages/RV32G.pspec Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="RV32" val="1"/>
<set name="RVG" val="0x1F"/>
</context_set>
</context_data>
</processor_spec>

12
Ghidra/Processors/RISCV/data/languages/RV32GC.pspec Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="RV32" val="1"/>
<set name="RVG" val="0x1F"/>
<set name="RVC" val="1"/>
</context_set>
</context_data>
</processor_spec>

11
Ghidra/Processors/RISCV/data/languages/RV32I.pspec Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="RV32" val="1"/>
<set name="RVI" val="1"/>
</context_set>
</context_data>
</processor_spec>

12
Ghidra/Processors/RISCV/data/languages/RV32IC.pspec Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="RV32" val="1"/>
<set name="RVI" val="1"/>
<set name="RVC" val="1"/>
</context_set>
</context_data>
</processor_spec>

13
Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="RV32" val="1"/>
<set name="RVI" val="1"/>
<set name="RVM" val="1"/>
<set name="RVC" val="1"/>
</context_set>
</context_data>
</processor_spec>

11
Ghidra/Processors/RISCV/data/languages/RV64G.pspec Normal file
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@ -0,0 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="RV64" val="1"/>
<set name="RVG" val="0x1F"/>
</context_set>
</context_data>
</processor_spec>

12
Ghidra/Processors/RISCV/data/languages/RV64GC.pspec Normal file
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@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="RV64" val="1"/>
<set name="RVG" val="0x1F"/>
<set name="RVC" val="1"/>
</context_set>
</context_data>
</processor_spec>

11
Ghidra/Processors/RISCV/data/languages/RV64I.pspec Normal file
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@ -0,0 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="RV64" val="1"/>
<set name="RVI" val="1"/>
</context_set>
</context_data>
</processor_spec>

12
Ghidra/Processors/RISCV/data/languages/RV64IC.pspec Normal file
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@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="RV64" val="1"/>
<set name="RVI" val="1"/>
<set name="RVC" val="1"/>
</context_set>
</context_data>
</processor_spec>

172
Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc Normal file
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# RV32/RV64 Zicsr Standard Extension
# csrrc d,E,s 00003073 0000707f SIMPLE (0, 0)
:csrrc rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op1519
{
#TODO Size restriction error
# local tmprs1:$(XLEN) = rs1;
# local oldcsr:$(XLEN) = csr:$(XLEN);
# rd = oldcsr;
# local tmp:$(XLEN) = op1519;
# if (tmp == 0) goto inst_next;
# local newcsr:$(XLEN) = oldcsr & ~tmprs1;
# csr = zext(newcsr);
}
# csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0)
:csrrci rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7
{
#TODO Size restriction error
# local oldcsr:$(XLEN) = csr:$(XLEN);
# rd = oldcsr;
# local tmp:$(XLEN) = op1519;
# if (tmp == 0) goto inst_next;
# csr = csr & ~tmp;
}
# csrrs d,E,s 00002073 0000707f SIMPLE (0, 0)
:csrrs rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519
{
#TODO Size restriction error
# local tmprs1 = rs1;
# local oldcsr:$(XLEN) = csr:$(XLEN);
# rd = oldcsr;
# local tmp:$(XLEN) = op1519;
# if (tmp == 0) goto inst_next;
# csr = csr | tmprs1;
}
# csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0)
:csrrsi rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6
{
#TODO Size restriction error
# local oldcsr:$(XLEN) = csr:$(XLEN);
# rd = oldcsr;
# local tmp:$(XLEN) = op1519;
# if (tmp == 0) goto inst_next;
# csr = csr | tmp;
}
# csrrw d,E,s 00001073 0000707f SIMPLE (0, 0)
:csrrw rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op1519
{
#TODO Size restriction error
# local tmprs1:$(XLEN) = rs1;
# local oldcsr:$(XLEN) = csr:$(XLEN);
# local tmp:$(XLEN) = op1519;
# csr = tmprs1;
# if (tmp == 0) goto inst_next;
# rd = oldcsr;
}
# csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0)
:csrrwi rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5
{
#TODO Size restriction error
# local oldcsr:$(XLEN) = csr:$(XLEN);
# local tmp:$(XLEN) = op1519;
# csr = tmp;
# if (tmp == 0) goto inst_next;
# rd = oldcsr;
}
# frcsr d 00302073 fffff07f SIMPLE (0, 0)
:frcsr rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x60
{
rd = fcsr;
}
# frflags d 00102073 fffff07f SIMPLE (0, 0)
:frflags rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x20
{
rd = zext(fflags[0,5]);
}
# frrm d 00202073 fffff07f SIMPLE (0, 0)
:frrm rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x40
{
rd = frm;
}
# fscsr s 00301073 fff07fff SIMPLE (0, 0)
:fscsr rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x3
{
zero = fcsr;
fcsr = rs1;
}
# fscsr d,s 00301073 fff0707f SIMPLE (0, 0)
:fscsr rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x3
{
rd = fcsr;
fcsr = rs1;
}
# fsflags s 00101073 fff07fff SIMPLE (0, 0)
:fsflags rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x1
{
zero = zext(fflags[0,5]);
fflags[0,5] = rs1[0,5];
}
# fsflags d,s 00101073 fff0707f SIMPLE (0, 0)
:fsflags rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x1
{
rd = zext(fflags[0,5]);
fflags[0,5] = rs1[0,5];
}
# fsflagsi d,Z 00105073 fff0707f SIMPLE (0, 0)
:fsflagsi rd,op1519 is op1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x1
{
rd = zext(fflags[0,5]);
local tmp:1 = op1519:1;
fflags[0,5] = tmp[0,5];
}
# fsflagsi Z 00105073 fff07fff SIMPLE (0, 0)
:fsflagsi op1519 is op1519 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0 & op2031=0x1
{
zero = zext(fflags[0,5]);
local tmp:1 = op1519:1;
fflags[0,5] = tmp[0,5];
}
# fsrm s 00201073 fff07fff SIMPLE (0, 0)
:fsrm rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x2
{
zero = zext(frm[0,3]);
frm[0,3] = rs1[0,3];
}
# fsrm d,s 00201073 fff0707f SIMPLE (0, 0)
:fsrm rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x2
{
rd = zext(frm[0,3]);
frm[0,3] = rs1[0,3];
}
# fsrmi d,Z 00205073 fff0707f SIMPLE (0, 0)
:fsrmi rd,op1519 is op1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x2
{
rd = zext(frm[0,3]);
local tmp:1 = op1519:1;
frm[0,3] = tmp[0,3];
}
# fsrmi Z 00205073 fff07fff SIMPLE (0, 0)
:fsrmi op1519 is op1519 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0 & op2031=0x2
{
zero = zext(frm[0,3]);
local tmp:1 = op1519:1;
frm[0,3] = tmp[0,3];
}

12
Ghidra/Processors/RISCV/data/languages/riscv.ilp32.slaspec Normal file
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define endian=little;
@define XLEN 4
@define XLEN2 8
@define FLEN 0
@define ADDRSIZE "32"
@define FPSIZE ""
@include "riscv.reg.sinc"
@include "riscv.table.sinc"
@include "riscv.instr.sinc"

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Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec Normal file
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define endian=little;
@define XLEN 4
@define XLEN2 8
@define FLEN 8
@define ADDRSIZE "32"
@define FPSIZE "64"
@include "riscv.reg.sinc"
@include "riscv.table.sinc"
@include "riscv.instr.sinc"

12
Ghidra/Processors/RISCV/data/languages/riscv.ilp32f.slaspec Normal file
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define endian=little;
@define XLEN 4
@define XLEN2 8
@define FLEN 4
@define ADDRSIZE "32"
@define FPSIZE "32"
@include "riscv.reg.sinc"
@include "riscv.table.sinc"
@include "riscv.instr.sinc"

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Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="RISCV"
endian="little"
size="64"
variant="RV64I"
version="1.0"
slafile="riscv.lp64.sla"
processorspec="RV64I.pspec"
id="RISCV:LE:64:RV64I">
<description>RISC-V 64 little base</description>
<compiler name="gcc" spec="riscv64.cspec" id="gcc"/>
<external_name tool="DWARF.register.mapping.file" name="riscv64.dwarf"/>
</language>
<language processor="RISCV"
endian="little"
size="64"
variant="RV64IC"
version="1.0"
slafile="riscv.lp64.sla"
processorspec="RV64IC.pspec"
id="RISCV:LE:64:RV64IC">
<description>RISC-V 64 little base compressed</description>
<compiler name="gcc" spec="riscv64.cspec" id="gcc"/>
<external_name tool="DWARF.register.mapping.file" name="riscv64.dwarf"/>
</language>
<language processor="RISCV"
endian="little"
size="64"
variant="RV64G"
version="1.0"
slafile="riscv.lp64d.sla"
processorspec="RV64G.pspec"
id="RISCV:LE:64:RV64G">
<description>RISC-V 64 little general purpose</description>
<compiler name="gcc" spec="riscv64-fp.cspec" id="gcc"/>
<external_name tool="DWARF.register.mapping.file" name="riscv64-fp.dwarf"/>
</language>
<language processor="RISCV"
endian="little"
size="64"
variant="RV64GC"
version="1.0"
slafile="riscv.lp64d.sla"
processorspec="RV64GC.pspec"
id="RISCV:LE:64:RV64GC">
<description>RISC-V 64 little general purpose compressed</description>
<compiler name="gcc" spec="riscv64-fp.cspec" id="gcc"/>
<external_name tool="DWARF.register.mapping.file" name="riscv64-fp.dwarf"/>
</language>
<language processor="RISCV"
endian="little"
size="64"
variant="default"
version="1.0"
slafile="riscv.lp64d.sla"
processorspec="RV64GC.pspec"
id="RISCV:LE:64:default">
<description>RISC-V 32 little default</description>
<compiler name="gcc" spec="riscv64-fp.cspec" id="gcc"/>
<external_name tool="DWARF.register.mapping.file" name="riscv64-fp.dwarf"/>
</language>
<language processor="RISCV"
endian="little"
size="32"
variant="RV32I"
version="1.0"
slafile="riscv.ilp32.sla"
processorspec="RV32I.pspec"
id="RISCV:LE:32:RV32I">
<description>RISC-V 32 little base</description>
<compiler name="gcc" spec="riscv32.cspec" id="gcc"/>
<external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
</language>
<language processor="RISCV"
endian="little"
size="32"
variant="RV32IC"
version="1.0"
slafile="riscv.ilp32.sla"
processorspec="RV32IC.pspec"
id="RISCV:LE:32:RV32IC">
<description>RISC-V 32 little base compressed</description>
<compiler name="gcc" spec="riscv32.cspec" id="gcc"/>
<external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
</language>
<language processor="RISCV"
endian="little"
size="32"
variant="RV32IMC"
version="1.0"
slafile="riscv.ilp32.sla"
processorspec="RV32IMC.pspec"
id="RISCV:LE:32:RV32IMC">
<description>RISC-V 32 little base compressed</description>
<compiler name="gcc" spec="riscv32.cspec" id="gcc"/>
<external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
</language>
<language processor="RISCV"
endian="little"
size="32"
variant="RV32G"
version="1.0"
slafile="riscv.ilp32d.sla"
processorspec="RV32G.pspec"
id="RISCV:LE:32:RV32G">
<description>RISC-V 32 little general purpose</description>
<compiler name="gcc" spec="riscv32-fp.cspec" id="gcc"/>
<external_name tool="DWARF.register.mapping.file" name="riscv32-fp.dwarf"/>
</language>
<language processor="RISCV"
endian="little"
size="32"
variant="RV32GC"
version="1.0"
slafile="riscv.ilp32d.sla"
processorspec="RV32GC.pspec"
id="RISCV:LE:32:RV32GC">
<description>RISC-V 32 little general purpose compressed</description>
<compiler name="gcc" spec="riscv32-fp.cspec" id="gcc"/>
<external_name tool="DWARF.register.mapping.file" name="riscv32-fp.dwarf"/>
</language>
<language processor="RISCV"
endian="little"
size="32"
variant="default"
version="1.0"
slafile="riscv.ilp32d.sla"
processorspec="RV32GC.pspec"
id="RISCV:LE:32:default">
<description>RISC-V 32 little default</description>
<compiler name="gcc" spec="riscv32-fp.cspec" id="gcc"/>
<external_name tool="DWARF.register.mapping.file" name="riscv32-fp.dwarf"/>
</language>
</language_definitions>

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Ghidra/Processors/RISCV/data/languages/riscv.lp64.slaspec Normal file
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define endian=little;
@define XLEN 8
@define XLEN2 16
@define FLEN 0
@define ADDRSIZE "64"
@define FPSIZE ""
@include "riscv.reg.sinc"
@include "riscv.table.sinc"
@include "riscv.instr.sinc"

12
Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec Normal file
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@ -0,0 +1,12 @@
define endian=little;
@define XLEN 8
@define XLEN2 16
@define FLEN 8
@define ADDRSIZE "64"
@define FPSIZE "64"
@include "riscv.reg.sinc"
@include "riscv.table.sinc"
@include "riscv.instr.sinc"

12
Ghidra/Processors/RISCV/data/languages/riscv.lp64f.slaspec Normal file
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@ -0,0 +1,12 @@
define endian=little;
@define XLEN 8
@define XLEN2 16
@define FLEN 4
@define ADDRSIZE "64"
@define FPSIZE "32"
@include "riscv.reg.sinc"
@include "riscv.table.sinc"
@include "riscv.instr.sinc"

25
Ghidra/Processors/RISCV/data/languages/riscv.opinion Normal file
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<opinions>
<constraint loader="Executable and Linking Format (ELF)">
<constraint compilerSpecID="gcc">
<!-- e_ident: ELFCLASS64 or ELFCLASS32 -->
<!-- e_type: nothing specific -->
<!-- e_machine: EM_RISCV, primary -->
<!-- e_flags: used as secondary -->
<!-- EF_RISCV_RVC 0x0001 -->
<!-- EF_RISCV_FLOAT_ABI_SINGLE 0x0002 -->
<!-- EF_RISCV_FLOAT_ABI_DOUBLE 0x0004 -->
<!-- EF_RISCV_ABI_QUAD 0x0006 -->
<!-- EF_RISCV_RVE 0x0008 -->
<!-- EF_RISCV_TSO 0x0010 -->
<constraint primary="243" secondary="0" processor="RISCV" endian="little" variant="RV32I"/>
<constraint primary="243" secondary="0" processor="RISCV" endian="little" variant="RV64I"/>
<constraint primary="243" secondary="1" processor="RISCV" endian="little" variant="RV32IMC"/>
<constraint primary="243" secondary="1" processor="RISCV" endian="little" variant="RV64IC"/>
<constraint primary="243" secondary="2" processor="RISCV" endian="little" variant="RV32IF"/>
<constraint primary="243" secondary="4" processor="RISCV" endian="little" variant="RV32G"/>
<constraint primary="243" secondary="4" processor="RISCV" endian="little" variant="RV64G"/>
<constraint primary="243" secondary="5" processor="RISCV" endian="little" variant="RV32GC"/>
<constraint primary="243" secondary="5" processor="RISCV" endian="little" variant="RV64GC"/>
</constraint>
</constraint>
</opinions>

63
Ghidra/Processors/RISCV/data/languages/riscv.priv.sinc Normal file
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# RISC-V Privileged Instructions
# Trap-Return
# dret 7b200073 ffffffff SIMPLE (0, 0)
:dret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0xf640
{
}
# hret 20200073 ffffffff SIMPLE (0, 0)
:hret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x4040
{
}
# mret 30200073 ffffffff SIMPLE (0, 0)
:mret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x6040
{
}
# sret 10200073 ffffffff SIMPLE (0, 0)
:sret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2040
{
}
# uret 00200073 ffffffff SIMPLE (0, 0)
:uret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x40
{
}
# Interrupt-Management
# wfi 10500073 ffffffff SIMPLE (0, 0)
:wfi is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x20a0
{
}
# Supervisor Memory-Management
# sfence.vm 10400073 ffffffff SIMPLE (0, 0)
:sfence.vm is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2080
{
}
# sfence.vm s 10400073 fff07fff SIMPLE (0, 0)
:sfence.vm rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x104
{
}
# sfence.vma s,t 12000073 fe007fff SIMPLE (0, 0)
:sfence.vma rs1,rs2 is rs2 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2531=0x9
{
}
# Hypervisor Memory-Management
#TODO

793
Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc Normal file
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@ -0,0 +1,793 @@
define alignment=2;
define space ram type=ram_space size=$(XLEN) default;
define space register type=register_space size=4;
# A - Atomic instructions
# B - Bit manipulation instructions
# C - Compressed instructions
# D - Double-precision floating-point instructions
# E - Embedded applications, resource-constrained subset
# F - Single-precision floating-point instructions
# G - General (I + M + A + F + D)
# I - Integer base instructions
# J - Dynamically translated languages
# L - Decimal floating point instructions
# M - Integer multiplication and division instructions
# N - User-level interrupt instructions
# P - Packed-SIMD instructions
# Q - Quad-precision floating-point instructions
# T - Transactional Memory instructions
# V - Vector operations instructions
# RV [32, 64, 128] I, M, A, F, D, G, Q, L, C, B, J, T, P, V, N
define register offset=0x1020 size=8 extensions;
define context extensions
RVI=(0,0)
RVM=(1,1)
RVA=(2,2)
RVF=(3,3)
RVD=(4,4)
RVG=(0,4)
RVQ=(5,5)
RVL=(6,6)
RVC=(7,7)
RVB=(8,8)
RVJ=(9,9)
RVT=(10,10)
RVP=(11,11)
RVV=(12,12)
RVN=(13,13)
RV128=(61,61)
RV64=(62,62)
RV32=(63,63)
;
define register offset=0x1000 size=$(XLEN) [ pc ];
# 08-31 reserved
# 05-07 frm
# 000 - RNE - round to nearest, ties to even
# 001 - RTZ - round towards zero
# 010 - RDN - round down (towards -inf)
# 011 - RUP - round up (towards +inf)
# 100 - RMM - round to nearest, ties to max magnitude
# 101 - invalid
# 110 - invalid
# 111 - DYN - in rm field, selects dynamic rounding mode
# in rounding mode register, invalid
# 04 NV - invalid operation
# 03 DZ - divide by zero
# 02 OF - overflow
# 01 UF - underflow
# 00 NX - inexact
#define register offset=0x1008 size=4 [ fcsr ];
#TODO FIXME
#TODO This is really broken
#NOTE This is stolen from ppc_common, so it has something similar
define register offset=0x1010 size=$(XLEN) [ RESERVE_ADDRESS ];
define register offset=0x1018 size=1 [ RESERVE ];
define register offset=0x101C size=1 [ RESERVE_LENGTH ];
#TODO FIXME
# x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15
# z ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5
# x16 x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 x31
# a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6
define register offset=0x2000 size=$(XLEN) [ zero ra sp gp tp t0 t1 t2
s0 s1 a0 a1 a2 a3 a4 a5
a6 a7 s2 s3 s4 s5 s6 s7
s8 s9 s10 s11 t3 t4 t5 t6 ];
@if FPSIZE != ""
define register offset=0x3000 size=$(FLEN) [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7
fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5
fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7
fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];
@endif
define token instr (32)
op0001=(0,1)
op0204=(2,4)
op0506=(5,6)
op0707=(7,7)
op0711=(7,11)
r0711=(7,11)
fr0711=(7,11)
op0811=(8,11)
op1214=(12,14)
funct3=(12,14)
op1219=(12,19)
op1231=(12,31)
sop1231=(12,31) signed
op1519=(15,19)
r1519=(15,19)
fr1519=(15,19)
op1527=(15,27)
op1531=(15,31)
op2020=(20,20)
succ=(20,23)
op2024=(20,24)
r2024=(20,24)
fr2024=(20,24)
csr_0=(20,27)
csr_1=(20,27)
csr_2=(20,27)
csr_3=(20,27)
csr_4=(20,27)
csr_50=(20,26)
csr_58=(20,25)
csr_5C=(20,25)
csr_60=(20,26)
csr_68=(20,25)
csr_6C=(20,25)
csr_70=(20,26)
csr_78=(20,24)
csr_7A=(20,23)
csr_7B=(20,23)
csr_7C=(20,25)
csr_8=(20,27)
csr_90=(20,26)
csr_98=(20,25)
csr_9C=(20,25)
csr_A0=(20,26)
csr_A8=(20,25)
csr_AC=(20,25)
csr_B0=(20,26)
csr_B8=(20,25)
csr_BC=(20,25)
csr_C0=(20,26)
csr_C8=(20,25)
csr_CC=(20,25)
csr_D0=(20,26)
csr_D8=(20,25)
csr_DC=(20,25)
csr_E0=(20,26)
csr_E8=(20,25)
csr_EC=(20,25)
csr_F0=(20,26)
csr_F8=(20,25)
csr_FC=(20,25)
op2031=(20,31)
sop2031=(20,31) signed
op2130=(21,30)
op2427=(24,27)
pred=(24,27)
op2525=(25,25)
op2526=(25,26)
op2527=(25,27)
op2530=(25,30)
op2531=(25,31)
sop2531=(25,31) signed
funct7=(25,31)
op2627=(26,27)
op2631=(26,31)
op2731=(27,31)
funct5=(27,31)
op2727=(27,27)
r2731=(27,31)
fr2731=(27,31)
op2829=(28,29)
fm=(28,31)
op3031=(30,31)
sop3131=(31,31) signed
;
define token cinstr (16)
cop0001=(0,1)
cop0202=(2,2)
cop0203=(2,3)
cop0204=(2,4)
cr0204s=(2,4)
cfr0204s=(2,4)
cop0205=(2,5)
cop0206=(2,6)
cr0206=(2,6)
cfr0206=(2,6)
cop0212=(2,12)
cop0304=(3,4)
cop0305=(3,5)
cop0406=(4,6)
cop0505=(5,5)
cop0506=(5,6)
cop0512=(5,12)
cop0606=(6,6)
cop0707=(7,7)
cop0708=(7,8)
cop0709=(7,9)
cr0709s=(7,9)
cd0709s=(7,9)
cfr0709s=(7,9)
cop0710=(7,10)
cop0711=(7,11)
cr0711=(7,11)
cd0711=(7,11)
cfr0711=(7,11)
cop0712=(7,12)
cop0808=(8,8)
cop0910=(9,10)
cop0912=(9,12)
cop1010=(10,10)
cop1011=(10,11)
cop1012=(10,12)
cop1111=(11,11)
cop1112=(11,12)
cop1212=(12,12)
scop1212=(12,12) signed
cop1315=(13,15)
;
attach variables [ r0711 r1519 r2024 r2731 ]
[ zero ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5
a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ];
attach variables [ cr0206 cr0711 cd0711 ]
[ zero ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5
a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ];
attach variables [ cr0204s cr0709s cd0709s ]
[ s0 s1 a0 a1 a2 a3 a4 a5 ];
@if FPSIZE != ""
attach variables [ fr0711 fr1519 fr2024 fr2731 ]
[ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5
fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];
attach variables [ cfr0206 cfr0711 ]
[ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5
fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];
attach variables [ cfr0204s cfr0709s ]
[ fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 ];
@endif
#TODO this approach is probably incorrect
define register offset=0x90000000 size=$(XLEN) [ ustatus ];
define register offset=0x90000010 size=$(XLEN) [ fflags ];
define register offset=0x90000020 size=$(XLEN) [ frm ];
define register offset=0x90000030 size=$(XLEN) [ fcsr ];
define register offset=0x90000040 size=$(XLEN) [ uie ];
define register offset=0x90000050 size=$(XLEN) [ utvec ];
define register offset=0x90000400 size=$(XLEN) [ uscratch ];
define register offset=0x90000410 size=$(XLEN) [ uepc ];
define register offset=0x90000420 size=$(XLEN) [ ucause ];
define register offset=0x90000430 size=$(XLEN) [ utval ];
define register offset=0x90000440 size=$(XLEN) [ uip ];
define register offset=0x90001000 size=$(XLEN) [ sstatus ];
define register offset=0x90001020 size=$(XLEN) [ sedeleg ];
define register offset=0x90001030 size=$(XLEN) [ sideleg ];
define register offset=0x90001040 size=$(XLEN) [ sie ];
define register offset=0x90001050 size=$(XLEN) [ stvec ];
define register offset=0x90001060 size=$(XLEN) [ scounteren ];
define register offset=0x90001400 size=$(XLEN) [ sscratch ];
define register offset=0x90001410 size=$(XLEN) [ sepc ];
define register offset=0x90001420 size=$(XLEN) [ scause ];
define register offset=0x90001430 size=$(XLEN) [ stval ];
define register offset=0x90001440 size=$(XLEN) [ sip ];
define register offset=0x90001800 size=$(XLEN) [ satp ];
define register offset=0x90002000 size=$(XLEN) [ vsstatus ];
define register offset=0x90002040 size=$(XLEN) [ vsie ];
define register offset=0x90002050 size=$(XLEN) [ vstvec ];
define register offset=0x90002400 size=$(XLEN) [ vsscratch ];
define register offset=0x90002410 size=$(XLEN) [ vsepc ];
define register offset=0x90002420 size=$(XLEN) [ vscause ];
define register offset=0x90002430 size=$(XLEN) [ vstval ];
define register offset=0x90002440 size=$(XLEN) [ vsip ];
define register offset=0x90002800 size=$(XLEN) [ vsatp ];
define register offset=0x90003000 size=$(XLEN) [ mstatus ];
define register offset=0x90003010 size=$(XLEN) [ misa ];
define register offset=0x90003020 size=$(XLEN) [ medeleg ];
define register offset=0x90003030 size=$(XLEN) [ mideleg ];
define register offset=0x90003040 size=$(XLEN) [ mie ];
define register offset=0x90003050 size=$(XLEN) [ mtvec ];
define register offset=0x90003060 size=$(XLEN) [ mcounteren ];
define register offset=0x90003100 size=$(XLEN) [ mstatush ];
define register offset=0x90003200 size=$(XLEN) [ mucounteren ];
define register offset=0x90003210 size=$(XLEN) [ mscounteren ];
define register offset=0x90003220 size=$(XLEN) [ mhcounteren ];
define register offset=0x90003400 size=$(XLEN) [ mscratch ];
define register offset=0x90003410 size=$(XLEN) [ mepc ];
define register offset=0x90003420 size=$(XLEN) [ mcause ];
define register offset=0x90003430 size=$(XLEN) [ mtval ];
define register offset=0x90003440 size=$(XLEN) [ mip ];
define register offset=0x90003800 size=$(XLEN) [ mbase ];
define register offset=0x90003810 size=$(XLEN) [ mbound ];
define register offset=0x90003820 size=$(XLEN) [ mibase ];
define register offset=0x90003830 size=$(XLEN) [ mibound ];
define register offset=0x90003840 size=$(XLEN) [ mdbase ];
define register offset=0x90003850 size=$(XLEN) [ mdbound ];
define register offset=0x90003a00 size=$(XLEN) [ pmpcfg0 ];
define register offset=0x90003a10 size=$(XLEN) [ pmpcfg1 ];
define register offset=0x90003a20 size=$(XLEN) [ pmpcfg2 ];
define register offset=0x90003a30 size=$(XLEN) [ pmpcfg3 ];
define register offset=0x90003b00 size=$(XLEN) [ pmpaddr0 ];
define register offset=0x90003b10 size=$(XLEN) [ pmpaddr1 ];
define register offset=0x90003b20 size=$(XLEN) [ pmpaddr2 ];
define register offset=0x90003b30 size=$(XLEN) [ pmpaddr3 ];
define register offset=0x90003b40 size=$(XLEN) [ pmpaddr4 ];
define register offset=0x90003b50 size=$(XLEN) [ pmpaddr5 ];
define register offset=0x90003b60 size=$(XLEN) [ pmpaddr6 ];
define register offset=0x90003b70 size=$(XLEN) [ pmpaddr7 ];
define register offset=0x90003b80 size=$(XLEN) [ pmpaddr8 ];
define register offset=0x90003b90 size=$(XLEN) [ pmpaddr9 ];
define register offset=0x90003ba0 size=$(XLEN) [ pmpaddr10 ];
define register offset=0x90003bb0 size=$(XLEN) [ pmpaddr11 ];
define register offset=0x90003bc0 size=$(XLEN) [ pmpaddr12 ];
define register offset=0x90003bd0 size=$(XLEN) [ pmpaddr13 ];
define register offset=0x90003be0 size=$(XLEN) [ pmpaddr14 ];
define register offset=0x90003bf0 size=$(XLEN) [ pmpaddr15 ];
define register offset=0x90006000 size=$(XLEN) [ hstatus ];
define register offset=0x90006020 size=$(XLEN) [ hedeleg ];
define register offset=0x90006030 size=$(XLEN) [ hideleg ];
define register offset=0x90006060 size=$(XLEN) [ hcounteren ];
define register offset=0x90006800 size=$(XLEN) [ hgatp ];
define register offset=0x90007a00 size=$(XLEN) [ tselect ];
define register offset=0x90007a10 size=$(XLEN) [ tdata1 ];
define register offset=0x90007a20 size=$(XLEN) [ tdata2 ];
define register offset=0x90007a30 size=$(XLEN) [ tdata3 ];
define register offset=0x90007b00 size=$(XLEN) [ dcsr ];
define register offset=0x90007b10 size=$(XLEN) [ dpc ];
define register offset=0x90007b20 size=$(XLEN) [ dscratch0 ];
define register offset=0x90007b30 size=$(XLEN) [ dscratch1 ];
define register offset=0x9000b000 size=$(XLEN) [ mcycle ];
define register offset=0x9000b020 size=$(XLEN) [ minstret ];
define register offset=0x9000b030 size=$(XLEN) [ mhpmcounter3 ];
define register offset=0x9000b040 size=$(XLEN) [ mhpmcounter4 ];
define register offset=0x9000b050 size=$(XLEN) [ mhpmcounter5 ];
define register offset=0x9000b060 size=$(XLEN) [ mhpmcounter6 ];
define register offset=0x9000b070 size=$(XLEN) [ mhpmcounter7 ];
define register offset=0x9000b080 size=$(XLEN) [ mhpmcounter8 ];
define register offset=0x9000b090 size=$(XLEN) [ mhpmcounter9 ];
define register offset=0x9000b0a0 size=$(XLEN) [ mhpmcounter10 ];
define register offset=0x9000b0b0 size=$(XLEN) [ mhpmcounter11 ];
define register offset=0x9000b0c0 size=$(XLEN) [ mhpmcounter12 ];
define register offset=0x9000b0d0 size=$(XLEN) [ mhpmcounter13 ];
define register offset=0x9000b0e0 size=$(XLEN) [ mhpmcounter14 ];
define register offset=0x9000b0f0 size=$(XLEN) [ mhpmcounter15 ];
define register offset=0x9000b100 size=$(XLEN) [ mhpmcounter16 ];
define register offset=0x9000b110 size=$(XLEN) [ mhpmcounter17 ];
define register offset=0x9000b120 size=$(XLEN) [ mhpmcounter18 ];
define register offset=0x9000b130 size=$(XLEN) [ mhpmcounter19 ];
define register offset=0x9000b140 size=$(XLEN) [ mhpmcounter20 ];
define register offset=0x9000b150 size=$(XLEN) [ mhpmcounter21 ];
define register offset=0x9000b160 size=$(XLEN) [ mhpmcounter22 ];
define register offset=0x9000b170 size=$(XLEN) [ mhpmcounter23 ];
define register offset=0x9000b180 size=$(XLEN) [ mhpmcounter24 ];
define register offset=0x9000b190 size=$(XLEN) [ mhpmcounter25 ];
define register offset=0x9000b1a0 size=$(XLEN) [ mhpmcounter26 ];
define register offset=0x9000b1b0 size=$(XLEN) [ mhpmcounter27 ];
define register offset=0x9000b1c0 size=$(XLEN) [ mhpmcounter28 ];
define register offset=0x9000b1d0 size=$(XLEN) [ mhpmcounter29 ];
define register offset=0x9000b1e0 size=$(XLEN) [ mhpmcounter30 ];
define register offset=0x9000b1f0 size=$(XLEN) [ mhpmcounter31 ];
define register offset=0x9000b200 size=$(XLEN) [ mcountinhibit ];
define register offset=0x9000b230 size=$(XLEN) [ mhpmevent3 ];
define register offset=0x9000b240 size=$(XLEN) [ mhpmevent4 ];
define register offset=0x9000b250 size=$(XLEN) [ mhpmevent5 ];
define register offset=0x9000b260 size=$(XLEN) [ mhpmevent6 ];
define register offset=0x9000b270 size=$(XLEN) [ mhpmevent7 ];
define register offset=0x9000b280 size=$(XLEN) [ mhpmevent8 ];
define register offset=0x9000b290 size=$(XLEN) [ mhpmevent9 ];
define register offset=0x9000b2a0 size=$(XLEN) [ mhpmevent10 ];
define register offset=0x9000b2b0 size=$(XLEN) [ mhpmevent11 ];
define register offset=0x9000b2c0 size=$(XLEN) [ mhpmevent12 ];
define register offset=0x9000b2d0 size=$(XLEN) [ mhpmevent13 ];
define register offset=0x9000b2e0 size=$(XLEN) [ mhpmevent14 ];
define register offset=0x9000b2f0 size=$(XLEN) [ mhpmevent15 ];
define register offset=0x9000b300 size=$(XLEN) [ mhpmevent16 ];
define register offset=0x9000b310 size=$(XLEN) [ mhpmevent17 ];
define register offset=0x9000b320 size=$(XLEN) [ mhpmevent18 ];
define register offset=0x9000b330 size=$(XLEN) [ mhpmevent19 ];
define register offset=0x9000b340 size=$(XLEN) [ mhpmevent20 ];
define register offset=0x9000b350 size=$(XLEN) [ mhpmevent21 ];
define register offset=0x9000b360 size=$(XLEN) [ mhpmevent22 ];
define register offset=0x9000b370 size=$(XLEN) [ mhpmevent23 ];
define register offset=0x9000b380 size=$(XLEN) [ mhpmevent24 ];
define register offset=0x9000b390 size=$(XLEN) [ mhpmevent25 ];
define register offset=0x9000b3a0 size=$(XLEN) [ mhpmevent26 ];
define register offset=0x9000b3b0 size=$(XLEN) [ mhpmevent27 ];
define register offset=0x9000b3c0 size=$(XLEN) [ mhpmevent28 ];
define register offset=0x9000b3d0 size=$(XLEN) [ mhpmevent29 ];
define register offset=0x9000b3e0 size=$(XLEN) [ mhpmevent30 ];
define register offset=0x9000b3f0 size=$(XLEN) [ mhpmevent31 ];
define register offset=0x9000b800 size=$(XLEN) [ mcycleh ];
define register offset=0x9000b820 size=$(XLEN) [ minstreth ];
define register offset=0x9000b830 size=$(XLEN) [ mhpmcounter3h ];
define register offset=0x9000b840 size=$(XLEN) [ mhpmcounter4h ];
define register offset=0x9000b850 size=$(XLEN) [ mhpmcounter5h ];
define register offset=0x9000b860 size=$(XLEN) [ mhpmcounter6h ];
define register offset=0x9000b870 size=$(XLEN) [ mhpmcounter7h ];
define register offset=0x9000b880 size=$(XLEN) [ mhpmcounter8h ];
define register offset=0x9000b890 size=$(XLEN) [ mhpmcounter9h ];
define register offset=0x9000b8a0 size=$(XLEN) [ mhpmcounter10h ];
define register offset=0x9000b8b0 size=$(XLEN) [ mhpmcounter11h ];
define register offset=0x9000b8c0 size=$(XLEN) [ mhpmcounter12h ];
define register offset=0x9000b8d0 size=$(XLEN) [ mhpmcounter13h ];
define register offset=0x9000b8e0 size=$(XLEN) [ mhpmcounter14h ];
define register offset=0x9000b8f0 size=$(XLEN) [ mhpmcounter15h ];
define register offset=0x9000b900 size=$(XLEN) [ mhpmcounter16h ];
define register offset=0x9000b910 size=$(XLEN) [ mhpmcounter17h ];
define register offset=0x9000b920 size=$(XLEN) [ mhpmcounter18h ];
define register offset=0x9000b930 size=$(XLEN) [ mhpmcounter19h ];
define register offset=0x9000b940 size=$(XLEN) [ mhpmcounter20h ];
define register offset=0x9000b950 size=$(XLEN) [ mhpmcounter21h ];
define register offset=0x9000b960 size=$(XLEN) [ mhpmcounter22h ];
define register offset=0x9000b970 size=$(XLEN) [ mhpmcounter23h ];
define register offset=0x9000b980 size=$(XLEN) [ mhpmcounter24h ];
define register offset=0x9000b990 size=$(XLEN) [ mhpmcounter25h ];
define register offset=0x9000b9a0 size=$(XLEN) [ mhpmcounter26h ];
define register offset=0x9000b9b0 size=$(XLEN) [ mhpmcounter27h ];
define register offset=0x9000b9c0 size=$(XLEN) [ mhpmcounter28h ];
define register offset=0x9000b9d0 size=$(XLEN) [ mhpmcounter29h ];
define register offset=0x9000b9e0 size=$(XLEN) [ mhpmcounter30h ];
define register offset=0x9000b9f0 size=$(XLEN) [ mhpmcounter31h ];
define register offset=0x9000c000 size=$(XLEN) [ cycle ];
define register offset=0x9000c010 size=$(XLEN) [ time ];
define register offset=0x9000c020 size=$(XLEN) [ instret ];
define register offset=0x9000c030 size=$(XLEN) [ hpmcounter3 ];
define register offset=0x9000c040 size=$(XLEN) [ hpmcounter4 ];
define register offset=0x9000c050 size=$(XLEN) [ hpmcounter5 ];
define register offset=0x9000c060 size=$(XLEN) [ hpmcounter6 ];
define register offset=0x9000c070 size=$(XLEN) [ hpmcounter7 ];
define register offset=0x9000c080 size=$(XLEN) [ hpmcounter8 ];
define register offset=0x9000c090 size=$(XLEN) [ hpmcounter9 ];
define register offset=0x9000c0a0 size=$(XLEN) [ hpmcounter10 ];
define register offset=0x9000c0b0 size=$(XLEN) [ hpmcounter11 ];
define register offset=0x9000c0c0 size=$(XLEN) [ hpmcounter12 ];
define register offset=0x9000c0d0 size=$(XLEN) [ hpmcounter13 ];
define register offset=0x9000c0e0 size=$(XLEN) [ hpmcounter14 ];
define register offset=0x9000c0f0 size=$(XLEN) [ hpmcounter15 ];
define register offset=0x9000c100 size=$(XLEN) [ hpmcounter16 ];
define register offset=0x9000c110 size=$(XLEN) [ hpmcounter17 ];
define register offset=0x9000c120 size=$(XLEN) [ hpmcounter18 ];
define register offset=0x9000c130 size=$(XLEN) [ hpmcounter19 ];
define register offset=0x9000c140 size=$(XLEN) [ hpmcounter20 ];
define register offset=0x9000c150 size=$(XLEN) [ hpmcounter21 ];
define register offset=0x9000c160 size=$(XLEN) [ hpmcounter22 ];
define register offset=0x9000c170 size=$(XLEN) [ hpmcounter23 ];
define register offset=0x9000c180 size=$(XLEN) [ hpmcounter24 ];
define register offset=0x9000c190 size=$(XLEN) [ hpmcounter25 ];
define register offset=0x9000c1a0 size=$(XLEN) [ hpmcounter26 ];
define register offset=0x9000c1b0 size=$(XLEN) [ hpmcounter27 ];
define register offset=0x9000c1c0 size=$(XLEN) [ hpmcounter28 ];
define register offset=0x9000c1d0 size=$(XLEN) [ hpmcounter29 ];
define register offset=0x9000c1e0 size=$(XLEN) [ hpmcounter30 ];
define register offset=0x9000c1f0 size=$(XLEN) [ hpmcounter31 ];
define register offset=0x9000c800 size=$(XLEN) [ cycleh ];
define register offset=0x9000c810 size=$(XLEN) [ timeh ];
define register offset=0x9000c820 size=$(XLEN) [ instreth ];
define register offset=0x9000c830 size=$(XLEN) [ hpmcounter3h ];
define register offset=0x9000c840 size=$(XLEN) [ hpmcounter4h ];
define register offset=0x9000c850 size=$(XLEN) [ hpmcounter5h ];
define register offset=0x9000c860 size=$(XLEN) [ hpmcounter6h ];
define register offset=0x9000c870 size=$(XLEN) [ hpmcounter7h ];
define register offset=0x9000c880 size=$(XLEN) [ hpmcounter8h ];
define register offset=0x9000c890 size=$(XLEN) [ hpmcounter9h ];
define register offset=0x9000c8a0 size=$(XLEN) [ hpmcounter10h ];
define register offset=0x9000c8b0 size=$(XLEN) [ hpmcounter11h ];
define register offset=0x9000c8c0 size=$(XLEN) [ hpmcounter12h ];
define register offset=0x9000c8d0 size=$(XLEN) [ hpmcounter13h ];
define register offset=0x9000c8e0 size=$(XLEN) [ hpmcounter14h ];
define register offset=0x9000c8f0 size=$(XLEN) [ hpmcounter15h ];
define register offset=0x9000c900 size=$(XLEN) [ hpmcounter16h ];
define register offset=0x9000c910 size=$(XLEN) [ hpmcounter17h ];
define register offset=0x9000c920 size=$(XLEN) [ hpmcounter18h ];
define register offset=0x9000c930 size=$(XLEN) [ hpmcounter19h ];
define register offset=0x9000c940 size=$(XLEN) [ hpmcounter20h ];
define register offset=0x9000c950 size=$(XLEN) [ hpmcounter21h ];
define register offset=0x9000c960 size=$(XLEN) [ hpmcounter22h ];
define register offset=0x9000c970 size=$(XLEN) [ hpmcounter23h ];
define register offset=0x9000c980 size=$(XLEN) [ hpmcounter24h ];
define register offset=0x9000c990 size=$(XLEN) [ hpmcounter25h ];
define register offset=0x9000c9a0 size=$(XLEN) [ hpmcounter26h ];
define register offset=0x9000c9b0 size=$(XLEN) [ hpmcounter27h ];
define register offset=0x9000c9c0 size=$(XLEN) [ hpmcounter28h ];
define register offset=0x9000c9d0 size=$(XLEN) [ hpmcounter29h ];
define register offset=0x9000c9e0 size=$(XLEN) [ hpmcounter30h ];
define register offset=0x9000c9f0 size=$(XLEN) [ hpmcounter31h ];
define register offset=0x9000f110 size=$(XLEN) [ mvendorid ];
define register offset=0x9000f120 size=$(XLEN) [ marchid ];
define register offset=0x9000f130 size=$(XLEN) [ mimpid ];
define register offset=0x9000f140 size=$(XLEN) [ mhartid ];
attach variables [ csr_0 ]
[ ustatus fflags frm fcsr uie utvec _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
uscratch uepc ucause utval uip _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_1 ]
[ sstatus _ sedeleg sideleg sie stvec scounteren _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
sscratch sepc scause stval sip _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
satp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_2 ]
[ vsstatus _ _ _ vsie vstvec _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
vsscratch vsepc vscause vstval vsip _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
vsatp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_3 ]
[ mstatus misa medeleg mideleg mie mtvec mcounteren _ _ _ _ _ _ _ _ _
mstatush _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
mscratch mepc mcause mtval mip _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 _ _ _ _ _ _ _ _ _ _ _ _
pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7 pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_4 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_50 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_58 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_5C ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_60 ]
[ hstatus _ hedeleg hideleg _ _ hcounteren _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_68 ]
[ hgatp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_6C ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_70 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_78 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_7A ]
[ tselect tdata1 tdata2 tdata3 _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_7B ]
[ dcsr dpc dscratch0 dscratch1 _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_7C ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_8 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_90 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_98 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_9C ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_A0 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_A8 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_AC ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_B0 ]
[ mcycle _ minstret mhpmcounter3 mhpmcounter4 mhpmcounter5 mhpmcounter6 mhpmcounter7 mhpmcounter8 mhpmcounter9 mhpmcounter10 mhpmcounter11 mhpmcounter12 mhpmcounter13 mhpmcounter14 mhpmcounter15
mhpmcounter16 mhpmcounter17 mhpmcounter18 mhpmcounter19 mhpmcounter20 mhpmcounter21 mhpmcounter22 mhpmcounter23 mhpmcounter24 mhpmcounter25 mhpmcounter26 mhpmcounter27 mhpmcounter28 mhpmcounter29 mhpmcounter30 mhpmcounter31
mcountinhibit _ _ mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7 mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15
mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23 mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_B8 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_BC ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_C0 ]
[ cycle time instret hpmcounter3 hpmcounter4 hpmcounter5 hpmcounter6 hpmcounter7 hpmcounter8 hpmcounter9 hpmcounter10 hpmcounter11 hpmcounter12 hpmcounter13 hpmcounter14 hpmcounter15
hpmcounter16 hpmcounter17 hpmcounter18 hpmcounter19 hpmcounter20 hpmcounter21 hpmcounter22 hpmcounter23 hpmcounter24 hpmcounter25 hpmcounter26 hpmcounter27 hpmcounter28 hpmcounter29 hpmcounter30 hpmcounter31
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_C8 ]
[ cycleh timeh instreth hpmcounter3h hpmcounter4h hpmcounter5h hpmcounter6h hpmcounter7h hpmcounter8h hpmcounter9h hpmcounter10h hpmcounter11h hpmcounter12h hpmcounter13h hpmcounter14h hpmcounter15h
hpmcounter16h hpmcounter17h hpmcounter18h hpmcounter19h hpmcounter20h hpmcounter21h hpmcounter22h hpmcounter23h hpmcounter24h hpmcounter25h hpmcounter26h hpmcounter27h hpmcounter28h hpmcounter29h hpmcounter30h hpmcounter31h
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_CC ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_D0 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_D8 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_DC ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_E0 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_E8 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_EC ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_F0 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ mvendorid marchid mimpid mhartid _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_F8 ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
attach variables [ csr_FC ]
[ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];

134
Ghidra/Processors/RISCV/data/languages/riscv.rv32a.sinc Normal file
View File

@ -0,0 +1,134 @@
# RV32A Standard Extension
# amoadd.w d,t,0(s) 0000202f fe00707f DWORD|DREF (0, 4)
:amoadd.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp);
tmp = tmp + tmprs2;
*[ram]:4 tmprs1 = tmp;
}
# amoand.w d,t,0(s) 6000202f fe00707f DWORD|DREF (0, 4)
:amoand.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0xc & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp);
tmp = tmp & tmprs2;
*[ram]:4 tmprs1 = tmp;
}
# amomax.w d,t,0(s) a000202f fe00707f DWORD|DREF (0, 4)
:amomax.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x14 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp);
if (tmprs2 s<= tmp) goto inst_next;
*[ram]:4 tmprs1 = tmprs2;
}
# amomaxu.w d,t,0(s) e000202f fe00707f DWORD|DREF (0, 4)
:amomaxu.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1c & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp);
if (tmprs2 <= tmp) goto inst_next;
*[ram]:4 tmprs1 = tmprs2;
}
# amomin.w d,t,0(s) 8000202f fe00707f DWORD|DREF (0, 4)
:amomin.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x10 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp);
if (tmprs2 s>= tmp) goto inst_next;
*[ram]:4 tmprs1 = tmprs2;
}
# amominu.w d,t,0(s) c000202f fe00707f DWORD|DREF (0, 4)
:amominu.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x18 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp);
if (tmprs2 >= tmp) goto inst_next;
*[ram]:4 tmprs1 = tmprs2;
}
# amoor.w d,t,0(s) 4000202f fe00707f DWORD|DREF (0, 4)
:amoor.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x8 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp);
tmp = tmp | tmprs2;
*[ram]:4 tmprs1 = tmp;
}
# amoswap.w d,t,0(s) 0800202f fe00707f DWORD|DREF (0, 4)
:amoswap.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp);
*[ram]:4 tmprs1 = tmprs2;
}
# amoxor.w d,t,0(s) 2000202f fe00707f DWORD|DREF (0, 4)
:amoxor.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x4 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp);
tmp = tmp ^ tmprs2;
*[ram]:4 tmprs1 = tmp;
}
# lr.w d,0(s) 1000202f fff0707f DWORD|DREF (0, 4)
:lr.w^aqrl rd,(rs1) is RV32 & RVA & rs1 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x2 & op2024=0x0 & aqrl
{
RESERVE_ADDRESS = rs1;
RESERVE = 1;
RESERVE_LENGTH = 4;
assignW(rd, *[ram]:4 rs1);
}
# sc.w d,t,0(s) 1800202f fe00707f DWORD|DREF (0, 4)
:sc.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x3 & aqrl
{
local tmprs2 = rs2W;
local tmprs1 = rs1;
rd = 1;
if (RESERVE == 0) goto inst_next;
if (RESERVE_ADDRESS != rs1) goto inst_next;
if (RESERVE_LENGTH != 8) goto inst_next;
*[ram]:4 tmprs1 = tmprs2;
rd = 0;
RESERVE_ADDRESS = 0;
RESERVE = 0;
RESERVE_LENGTH = 0;
}

335
Ghidra/Processors/RISCV/data/languages/riscv.rv32d.sinc Normal file
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@ -0,0 +1,335 @@
# RV32D Standard Extension
@if FPSIZE == "64"
# fadd.d D,S,T 02007053 fe00707f SIMPLE (0, 0)
:fadd.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x1
{
frd = frs1D f+ frs2D;
}
# fadd.d D,S,T,m 02000053 fe00007f SIMPLE (0, 0)
:fadd.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x1
{
frd = frs1D f+ frs2D;
}
# fclass.d d,S e2001053 fff0707f SIMPLE (0, 0)
:fclass.d rd,frs1D is RV32 & RVD & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x71 & op2024=0x0
{
#TODO
# rd = 0;
# rd[0, 1] = 0; #TODO - inf
# rd[1, 1] = 0; #TODO - norm num
# rd[2, 1] = 0; #TODO - subnorm num
# rd[3, 1] = 0; #TODO - 0
# rd[4, 1] = 0; #TODO + 0
# rd[5, 1] = 0; #TODO + norm num
# rd[6, 1] = 0; #TODO + subnorm num
# rd[7, 1] = 0; #TODO + inf
# rd[8, 1] = 0; #TODO snan
# rd[9, 1] = 0; #TODO qnan
}
# fcvt.d.s D,S 42000053 fff0707f SIMPLE (0, 0)
:fcvt.d.s frd,frs1S is RV32 & RVD & frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x21 & op2024=0x0
{
local tmp:8 = float2float(frs1S);
frd = tmp;
}
# fcvt.d.w D,s d2000053 fff0707f SIMPLE (0, 0)
:fcvt.d.w frd,rs1W is RV32 & RVD & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x0
{
local tmp:8 = int2float(rs1W);
frd = tmp;
}
# fcvt.d.wu D,s d2100053 fff0707f SIMPLE (0, 0)
:fcvt.d.wu frd,rs1W is RV32 & RVD & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x1
{
#ATTN unsigned can be an issue here
local u32:$(XLEN2) = zext(rs1W);
local tmp:8 = int2float(u32);
frd = tmp;
}
# fcvt.s.d D,S 40107053 fff0707f SIMPLE (0, 0)
:fcvt.s.d frd,frs1D is RV32 & RVD & frs1D & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x20 & op2024=0x1
{
local tmp:4 = float2float(frs1D);
frd = zext(tmp);
}
# fcvt.s.d D,S,m 40100053 fff0007f SIMPLE (0, 0)
:fcvt.s.d frd,frs1D,FRM is RV32 & RVD & frs1D & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x1
{
local tmp:4 = float2float(frs1D);
frd = zext(tmp);
}
# fcvt.w.d d,S c2007053 fff0707f SIMPLE (0, 0)
:fcvt.w.d rdW,frs1D is RV32 & RVD & frs1D & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x61 & op2024=0x0
{
rdW = trunc(frs1D);
}
# fcvt.w.d d,S,m c2000053 fff0007f SIMPLE (0, 0)
:fcvt.w.d rdW,frs1D,FRM is RV32 & RVD & frs1D & FRM & op1214!=7 & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x0
{
rdW = trunc(frs1D);
}
# fcvt.wu.d d,S c2107053 fff0707f SIMPLE (0, 0)
:fcvt.wu.d rdW,frs1D is RV32 & RVD & frs1D & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x61 & op2024=0x1
{
#TODO unsigned
rdW = trunc(frs1D);
}
# fcvt.wu.d d,S,m c2100053 fff0007f SIMPLE (0, 0)
:fcvt.wu.d rdW,frs1D,FRM is RV32 & RVD & frs1D & FRM & op1214!=7 & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x1
{
#TODO unsigned
rdW = trunc(frs1D);
}
# fdiv.d D,S,T 1a007053 fe00707f SIMPLE (0, 0)
:fdiv.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0xd
{
frd = frs1D f/ frs2D;
}
# fdiv.d D,S,T,m 1a000053 fe00007f SIMPLE (0, 0)
:fdiv.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xd
{
frd = frs1D f/ frs2D;
}
# feq.d d,S,T a2002053 fe00707f SIMPLE (0, 0)
:feq.d rd,frs1D,frs2D is RV32 & RVD & frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x51
{
rd = zext(frs1D f== frs2D);
}
# fld D,o(s) 00003007 0000707f QWORD|DREF (0, 8)
:fld frd,immI(rs1) is RV32 & RVD & immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x3
{
local ea:$(XLEN) = immI + rs1;
frd = *[ram]:$(DFLEN) ea;
}
# fle.d d,S,T a2000053 fe00707f SIMPLE (0, 0)
:fle.d rd,frs1D,frs2D is RV32 & RVD & frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x51
{
rd = zext(frs1D f<= frs2D);
}
# flt.d d,S,T a2001053 fe00707f SIMPLE (0, 0)
:flt.d rd,frs1D,frs2D is RV32 & RVD & frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x51
{
rd = zext(frs1D f< frs2D);
}
#endif
# fmadd.d D,S,T,R 02007043 0600707f SIMPLE (0, 0)
:fmadd.d frd,frs1D,frs2D,frs3D is RV32 & RVD & frs1D & frd & frs2D & frs3D & op0001=0x3 & op0204=0x0 & op0506=0x2 & funct3=0x7 & op2526=0x1
{
frd = (frs1D f* frs2D) f+ frs3D;
}
# fmadd.d D,S,T,R,m 02000043 0600007f SIMPLE (0, 0)
:fmadd.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & frs3D & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x1
{
frd = (frs1D f* frs2D) f+ frs3D;
}
# fmax.d D,S,T 2a001053 fe00707f SIMPLE (0, 0)
:fmax.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x15
{
#TODO redo this
local tmpfrs1 = frs1D;
local tmpfrs2 = frs2D;
frd = tmpfrs1;
if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next;
if (nan(tmpfrs2)) goto inst_next;
frd = tmpfrs2;
if (nan(tmpfrs1)) goto inst_next;
if (tmpfrs2 f> tmpfrs1) goto inst_next;
frd = tmpfrs1;
}
# fmin.d D,S,T 2a000053 fe00707f SIMPLE (0, 0)
:fmin.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x15
{
#TODO redo this
local tmpfrs1 = frs1D;
local tmpfrs2 = frs2D;
frd = tmpfrs1;
if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next;
if (nan(tmpfrs2)) goto inst_next;
frd = tmpfrs2;
if (nan(tmpfrs1)) goto inst_next;
if (tmpfrs2 f<= tmpfrs1) goto inst_next;
frd = tmpfrs1;
}
# fmsub.d D,S,T,R 02007047 0600707f SIMPLE (0, 0)
:fmsub.d frd,frs1D,frs2D,frs3D is RV32 & RVD & frs1D & frd & frs2D & frs3D & op0001=0x3 & op0204=0x1 & op0506=0x2 & funct3=0x7 & op2526=0x1
{
frd = (frs1D f* frs2D) f- frs3D;
}
# fmsub.d D,S,T,R,m 02000047 0600007f SIMPLE (0, 0)
:fmsub.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & frs3D & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x1
{
frd = (frs1D f* frs2D) f- frs3D;
}
# fmul.d D,S,T 12007053 fe00707f SIMPLE (0, 0)
:fmul.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x9
{
frd = frs1D f* frs2D;
}
# fmul.d D,S,T,m 12000053 fe00007f SIMPLE (0, 0)
:fmul.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x9
{
frd = frs1D f* frs2D;
}
# fnmadd.d D,S,T,R 0200704f 0600707f SIMPLE (0, 0)
:fnmadd.d frd,frs1D,frs2D,frs3D is RV32 & RVD & frs1D & frd & frs2D & frs3D & op0001=0x3 & op0204=0x3 & op0506=0x2 & funct3=0x7 & op2526=0x1
{
frd = (f- (frs1D f* frs2D)) f- frs3D;
}
# fnmadd.d D,S,T,R,m 0200004f 0600007f SIMPLE (0, 0)
:fnmadd.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & frs3D & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x1
{
frd = (f- (frs1D f* frs2D)) f- frs3D;
}
# fnmsub.d D,S,T,R 0200704b 0600707f SIMPLE (0, 0)
:fnmsub.d frd,frs1D,frs2D,frs3D is RV32 & RVD & frs1D & frd & frs2D & frs3D & op0001=0x3 & op0204=0x2 & op0506=0x2 & funct3=0x7 & op2526=0x1
{
frd = (f- (frs1D f* frs2D)) f+ frs3D;
}
# fnmsub.d D,S,T,R,m 0200004b 0600007f SIMPLE (0, 0)
:fnmsub.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & frs3D & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x1
{
frd = (f- (frs1D f* frs2D)) f+ frs3D;
}
# fsd T,q(s) 00003027 0000707f QWORD|DREF (0, 8)
:fsd frs2D,immS(rs1) is RV32 & RVD & frs2D & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x3
{
local ea:$(XLEN) = immS + rs1;
*[ram]:$(DFLEN) ea = frs2D;
}
# fsgnj.d D,S,T 22000053 fe00707f SIMPLE (0, 0)
:fsgnj.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11 & op1519!=op2024
{
local tmp:$(DFLEN) = frs1D;
tmp[63,1] = frs2D[63,1];
frd = tmp;
}
# fmv.d D,U 22000053 fe00707f ALIAS (0, 0)
:fmv.d frd,frs1D is RV32 & RVD & frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11 & op1519=op2024
{
frd = frs1D;
}
# fsgnjn.d D,S,T 22001053 fe00707f SIMPLE (0, 0)
:fsgnjn.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11 & op1519!=op2024
{
local tmp:$(DFLEN) = frs1D;
tmp[63,1] = !frs2D[63,1];
frd = tmp;
}
# fneg.d D,U 22001053 fe00707f ALIAS (0, 0)
:fneg.d frd,frs1D is RV32 & RVD & frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11 & op1519=op2024
{
frd = f- frs1D;
}
# fsgnjx.d D,S,T 22002053 fe00707f SIMPLE (0, 0)
:fsgnjx.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11 & op1519!=op2024
{
local tmp:$(DFLEN) = frs1D;
tmp[63,1] = tmp[63,1] ^ frs2D[63,1];
frd = tmp;
}
# fabs.d D,U 22002053 fe00707f ALIAS (0, 0)
:fabs.d frd,frs1D is RV32 & RVD & frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11 & op1519=op2024
{
frd = abs(frs1D);
}
# fsqrt.d D,S 5a007053 fff0707f SIMPLE (0, 0)
:fsqrt.d frd,frs1D is RV32 & RVD & frs1D & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x2d & op2024=0x0
{
frd = sqrt(frs1D);
}
# fsqrt.d D,S,m 5a000053 fff0007f SIMPLE (0, 0)
:fsqrt.d frd,frs1D,FRM is RV32 & RVD & frs1D & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2d & op2024=0x0
{
frd = sqrt(frs1D);
}
# fsub.d D,S,T 0a007053 fe00707f SIMPLE (0, 0)
:fsub.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x5
{
frd = frs1D f- frs2D;
}
# fsub.d D,S,T,m 0a000053 fe00007f SIMPLE (0, 0)
:fsub.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x5
{
frd = frs1D f- frs2D;
}
@endif

358
Ghidra/Processors/RISCV/data/languages/riscv.rv32f.sinc Normal file
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@ -0,0 +1,358 @@
# RV32F Standard Extension
@if FPSIZE != ""
# fadd.s D,S,T 00007053 fe00707f SIMPLE (0, 0)
:fadd.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x0
{
local tmp:4 = frs1S f+ frs2S;
fassignS(frd, tmp);
}
# fadd.s D,S,T,m 00000053 fe00007f SIMPLE (0, 0)
:fadd.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x0
{
local tmp:4 = frs1S f+ frs2S;
fassignS(frd, tmp);
}
# fclass.s d,S e0001053 fff0707f SIMPLE (0, 0)
:fclass.s rd,frs1S is RV32 & RVF & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x70 & op2024=0x0
{
#TODO
# rd = 0;
# rd[0, 1] = 0; #TODO - inf
# rd[1, 1] = 0; #TODO - norm num
# rd[2, 1] = 0; #TODO - subnorm num
# rd[3, 1] = 0; #TODO - 0
# rd[4, 1] = 0; #TODO + 0
# rd[5, 1] = 0; #TODO + norm num
# rd[6, 1] = 0; #TODO + subnorm num
# rd[7, 1] = 0; #TODO + inf
# rd[8, 1] = 0; #TODO snan
# rd[9, 1] = 0; #TODO qnan
}
# fcvt.s.w D,s d0007053 fff0707f SIMPLE (0, 0)
:fcvt.s.w frd,rs1W is RV32 & RVF & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x68 & op2024=0x0
{
local tmp:4 = int2float(rs1W);
fassignS(frd, tmp);
}
# fcvt.s.w D,s,m d0000053 fff0007f SIMPLE (0, 0)
:fcvt.s.w frd,rs1W,FRM is RV32 & RVF & frd & FRM & op1214!=7 & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x0
{
local tmp:4 = int2float(rs1W);
fassignS(frd, tmp);
}
# fcvt.s.wu D,s d0107053 fff0707f SIMPLE (0, 0)
:fcvt.s.wu frd,rs1W is RV32 & RVF & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x68 & op2024=0x1
{
#ATTN unsigned can be an issue here
local u32:$(XLEN2) = zext(rs1W);
local tmp:4 = int2float(u32);
fassignS(frd, tmp);
}
# fcvt.s.wu D,s,m d0100053 fff0007f SIMPLE (0, 0)
:fcvt.s.wu frd,rs1W,FRM is RV32 & RVF & frd & FRM & op1214!=7 & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x1
{
#ATTN unsigned can be an issue here
local u32:$(XLEN2) = zext(rs1W);
local tmp:4 = int2float(u32);
fassignS(frd, tmp);
}
# fcvt.w.s d,S c0007053 fff0707f SIMPLE (0, 0)
:fcvt.w.s rdW,frs1S is RV32 & RVF & frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x60 & op2024=0x0
{
rdW = trunc(frs1S);
}
# fcvt.w.s d,S,m c0000053 fff0007f SIMPLE (0, 0)
:fcvt.w.s rdW,frs1S,FRM is RV32 & RVF & frs1S & FRM & op1214!=7 & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x0
{
rdW = trunc(frs1S);
}
# fcvt.wu.s d,S c0107053 fff0707f SIMPLE (0, 0)
:fcvt.wu.s rdW,frs1S is RV32 & RVF & frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x60 & op2024=0x1
{
#TODO unsigned
rdW = trunc(frs1S);
}
# fcvt.wu.s d,S,m c0100053 fff0007f SIMPLE (0, 0)
:fcvt.wu.s rdW,frs1S,FRM is RV32 & RVF & frs1S & FRM & op1214!=7 & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x1
{
#TODO unsigned
rdW = trunc(frs1S);
}
# fdiv.s D,S,T 18007053 fe00707f SIMPLE (0, 0)
:fdiv.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0xc
{
local tmp:4 = frs1S f/ frs2S;
fassignS(frd, tmp);
}
# fdiv.s D,S,T,m 18000053 fe00007f SIMPLE (0, 0)
:fdiv.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xc
{
local tmp:4 = frs1S f/ frs2S;
fassignS(frd, tmp);
}
# feq.s d,S,T a0002053 fe00707f SIMPLE (0, 0)
:feq.s rd,frs1S,frs2S is RV32 & RVF & frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x50
{
rd = zext(frs1S f== frs2S);
}
# fle.s d,S,T a0000053 fe00707f SIMPLE (0, 0)
:fle.s rd,frs1S,frs2S is RV32 & RVF & frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x50
{
rd = zext(frs1S f<= frs2S);
}
# flt.s d,S,T a0001053 fe00707f SIMPLE (0, 0)
:flt.s rd,frs1S,frs2S is RV32 & RVF & frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x50
{
rd = zext(frs1S f< frs2S);
}
# flw D,o(s) 00002007 0000707f DWORD|DREF (0, 4)
:flw frd,immI(rs1) is RV32 & RVF & immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x2
{
local ea:$(XLEN) = immI + rs1;
fassignS(frd, *[ram]:4 ea);
}
# fmadd.s D,S,T,R 00007043 0600707f SIMPLE (0, 0)
:fmadd.s frd,frs1S,frs2S,frs3S is RV32 & RVF & frs1S & frd & frs2S & frs3S & op0001=0x3 & op0204=0x0 & op0506=0x2 & funct3=0x7 & op2526=0x0
{
local tmp:4 = (frs1S f* frs2S) f+ frs3S;
fassignS(frd, tmp);
}
# fmadd.s D,S,T,R,m 00000043 0600007f SIMPLE (0, 0)
:fmadd.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & frs3S & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x0
{
local tmp:4 = (frs1S f* frs2S) f+ frs3S;
fassignS(frd, tmp);
}
# fmax.s D,S,T 28001053 fe00707f SIMPLE (0, 0)
:fmax.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x14
{
#TODO redo this
local tmpfrs1 = frs1S;
local tmpfrs2 = frs2S;
fassignS(frd, tmpfrs1);
if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next;
if (nan(tmpfrs2)) goto inst_next;
fassignS(frd, tmpfrs2);
if (nan(tmpfrs1)) goto inst_next;
if (tmpfrs2 f>= tmpfrs1) goto inst_next;
fassignS(frd, tmpfrs1);
}
# fmin.s D,S,T 28000053 fe00707f SIMPLE (0, 0)
:fmin.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x14
{
#TODO redo this
local tmpfrs1 = frs1S;
local tmpfrs2 = frs2S;
fassignS(frd, tmpfrs1);
if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next;
if (nan(tmpfrs2)) goto inst_next;
fassignS(frd, tmpfrs2);
if (nan(tmpfrs1)) goto inst_next;
if (tmpfrs2 f<= tmpfrs1) goto inst_next;
fassignS(frd, tmpfrs1);
}
# fmsub.s D,S,T,R 00007047 0600707f SIMPLE (0, 0)
:fmsub.s frd,frs1S,frs2S,frs3S is RV32 & RVF & frs1S & frd & frs2S & frs3S & op0001=0x3 & op0204=0x1 & op0506=0x2 & funct3=0x7 & op2526=0x0
{
local tmp:4 = (frs1S f* frs2S) f- frs3S;
fassignS(frd, tmp);
}
# fmsub.s D,S,T,R,m 00000047 0600007f SIMPLE (0, 0)
:fmsub.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & frs3S & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x0
{
local tmp:4 = (frs1S f* frs2S) f- frs3S;
fassignS(frd, tmp);
}
# fmul.s D,S,T 10007053 fe00707f SIMPLE (0, 0)
:fmul.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x8
{
local tmp:4 = frs1S f* frs2S;
fassignS(frd, tmp);
}
# fmul.s D,S,T,m 10000053 fe00007f SIMPLE (0, 0)
:fmul.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x8
{
local tmp:4 = frs1S f* frs2S;
fassignS(frd, tmp);
}
# fmv.w.x D,s f0000053 fff0707f SIMPLE (0, 0)
:fmv.w.x frd,rs1W is RV32 & RVF & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x78 & op2024=0x0
{
fassignS(frd, rs1W);
}
# fmv.x.w d,S e0000053 fff0707f SIMPLE (0, 0)
:fmv.x.w rdW,frs1S is RV32 & RVF & frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x70 & op2024=0x0
{
zassignW(rdW, frs1S);
}
# fnmadd.s D,S,T,R 0000704f 0600707f SIMPLE (0, 0)
:fnmadd.s frd,frs1S,frs2S,frs3S is RV32 & RVF & frs1S & frd & frs2S & frs3S & op0001=0x3 & op0204=0x3 & op0506=0x2 & funct3=0x7 & op2526=0x0
{
local tmp:4 = (f- (frs1S f* frs2S)) f- frs3S;
fassignS(frd, tmp);
}
# fnmadd.s D,S,T,R,m 0000004f 0600007f SIMPLE (0, 0)
:fnmadd.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & frs3S & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x0
{
local tmp:4 = (f- (frs1S f* frs2S)) f- frs3S;
fassignS(frd, tmp);
}
# fnmsub.s D,S,T,R 0000704b 0600707f SIMPLE (0, 0)
:fnmsub.s frd,frs1S,frs2S,frs3S is RV32 & RVF & frs1S & frd & frs2S & frs3S & op0001=0x3 & op0204=0x2 & op0506=0x2 & funct3=0x7 & op2526=0x0
{
local tmp:4 = (f- (frs1S f* frs2S)) f+ frs3S;
fassignS(frd, tmp);
}
# fnmsub.s D,S,T,R,m 0000004b 0600007f SIMPLE (0, 0)
:fnmsub.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & frs3S & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x0
{
local tmp:4 = (f- (frs1S f* frs2S)) f+ frs3S;
fassignS(frd, tmp);
}
# fsgnj.s D,S,T 20000053 fe00707f SIMPLE (0, 0)
:fsgnj.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10 & op1519!=op2024
{
local tmp:$(SFLEN) = frs1S;
tmp[31,1] = frs2S[31,1];
fassignS(frd, tmp);
}
# fmv.s D,U 20000053 fe00707f ALIAS (0, 0)
:fmv.s frd,frs1S is RV32 & RVF & frd & frs1S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10 & op1519=op2024
{
fassignS(frd, frs1S);
}
# fsgnjn.s D,S,T 20001053 fe00707f SIMPLE (0, 0)
:fsgnjn.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10 & op1519!=op2024
{
local tmp:$(SFLEN) = frs1S;
tmp[31,1] = !frs2S[31,1];
fassignS(frd, tmp);
}
# fneg.s D,U 20001053 fe00707f ALIAS (0, 0)
:fneg.s frd,frs1S is RV32 & RVF & frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10 & op1519=op2024
{
local tmp:4 = f- frs1S;
fassignS(frd, tmp);
}
# fsgnjx.s D,S,T 20002053 fe00707f SIMPLE (0, 0)
:fsgnjx.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10 & op1519!=op2024
{
local tmp:$(SFLEN) = frs1S;
tmp[31,1] = tmp[31,1] ^ frs2S[31,1];
fassignS(frd, tmp);
}
# fabs.s D,U 20002053 fe00707f ALIAS (0, 0)
:fabs.s frd,frs1S is RV32 & RVF & frd & frs1S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10 & op1519=op2024
{
local tmp:4 = abs(frs1S);
fassignS(frd, tmp);
}
# fsqrt.s D,S 58007053 fff0707f SIMPLE (0, 0)
:fsqrt.s frd,frs1S is RV32 & RVF & frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x2c & op2024=0x0
{
local tmp:4 = sqrt(frs1S);
fassignS(frd, tmp);
}
# fsqrt.s D,S,m 58000053 fff0007f SIMPLE (0, 0)
:fsqrt.s frd,frs1S,FRM is RV32 & RVF & frs1S & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2c & op2024=0x0
{
local tmp:4 = sqrt(frs1S);
fassignS(frd, tmp);
}
# fsub.s D,S,T 08007053 fe00707f SIMPLE (0, 0)
:fsub.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x4
{
local tmp:4 = frs1S f- frs2S;
fassignS(frd, tmp);
}
# fsub.s D,S,T,m 08000053 fe00007f SIMPLE (0, 0)
:fsub.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x4
{
local tmp:4 = frs1S f- frs2S;
fassignS(frd, tmp);
}
# fsw T,q(s) 00002027 0000707f DWORD|DREF (0, 4)
:fsw frs2S,immS(rs1) is RV32 & RVF & frs2S & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x2
{
local ea:$(XLEN) = immS + rs1;
*[ram]:$(SFLEN) ea = frs2S;
}
@endif

359
Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc Normal file
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@ -0,0 +1,359 @@
# RV32I Base Instruction Set
# add d,s,t 00000033 fe00707f SIMPLE (0, 0)
:add rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x0
{
rd = rs1 + rs2;
}
# addi d,s,j 00000013 0000707f SIMPLE (0, 0)
:addi rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op2031!=0 & op1519!=0
{
rd = rs1 + immI;
}
# nop 00000013 ffffffff ALIAS (0, 0)
:nop is RV32 & RVI & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op0711=0x0 & op1531=0x0
{
local NOP:1 = 0;
NOP = NOP;
}
# mv d,s 00000013 fff0707f ALIAS (0, 0)
:mv rd,rs1 is RV32 & RVI & rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op2031=0x0
{
rd = rs1;
}
# li d,j 00000013 000ff07f ALIAS (0, 0)
:li rd,immI is RV32 & RVI & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op1519=0x0 & op2031!=0
{
#TODO alias of addi rd,zero,0x0 is an issue
# choosing between: mv rd,zero and li rd,0x0
#ATTN this implementation uses mv rd,zero
rd = immI;
}
# and d,s,t 00007033 fe00707f SIMPLE (0, 0)
:and rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x0
{
rd = rs1 & rs2;
}
# andi d,s,j 00007013 0000707f SIMPLE (0, 0)
:andi rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x7
{
rd = rs1 & immI;
}
# auipc d,u 00000017 0000007f SIMPLE (0, 0)
:auipc rd,immU is RV32 & RVI & immU & rd & op0001=0x3 & op0204=0x5 & op0506=0x0
{
rd = (immU << 12) + inst_start;
}
# beq s,t,p 00000063 0000707f CONDBRANCH (0, 0)
:beq rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x0
{
if (rs1 == rs2) goto immSB;
}
# bge s,t,p 00005063 0000707f CONDBRANCH (0, 0)
:bge rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5
{
if (rs1 s>= rs2) goto immSB;
}
# bgeu s,t,p 00007063 0000707f CONDBRANCH (0, 0)
:bgeu rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x7
{
if (rs1 >= rs2) goto immSB;
}
# blt s,t,p 00004063 0000707f CONDBRANCH (0, 0)
:blt rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4
{
if (rs1 s< rs2) goto immSB;
}
# bltu s,t,p 00006063 0000707f CONDBRANCH (0, 0)
:bltu rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x6
{
if (rs1 < rs2) goto immSB;
}
# bne s,t,p 00001063 0000707f CONDBRANCH (0, 0)
:bne rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x1
{
if (rs1 != rs2) goto immSB;
}
# ebreak 00100073 ffffffff SIMPLE (0, 0)
:ebreak is RV32 & RVI & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x20
{
}
# ecall 00000073 ffffffff SIMPLE (0, 0)
:ecall is RV32 & RVI & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x0
{
}
# fence P,Q 0000000f f00fffff SIMPLE (0, 0)
:fence pred,succ is RV32 & RVI & pred & succ & op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x0 & fm=0x0 & op0711=0x0 & op1519=0x0
{
}
# jal d,a 0000006f 0000007f JSR (0, 0)
:jal rd,immUJ is RV32 & RVI & immUJ & rd & op0711!=0 & op0001=0x3 & op0204=0x3 & op0506=0x3
{
rd = inst_next;
call immUJ;
}
# j a 0000006f 00000fff BRANCH|ALIAS (0, 0)
:j immUJ is RV32 & RVI & immUJ & op0001=0x3 & op0204=0x3 & op0506=0x3 & op0711=0x0
{
call immUJ;
}
# jalr d,s,j 00000067 0000707f JSR (0, 0)
:jalr rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711!=0
{
local ea:$(XLEN) = (rs1 + immI) & ~1;
rd = inst_next;
call [ea];
}
# jr o(s) 00000067 00007fff BRANCH|ALIAS (0, 0)
:jr immI(rs1) is RV32 & RVI & immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031!=0
{
local ea:$(XLEN) = (rs1 + immI) & ~1;
call [ea];
}
# jr s 00000067 fff07fff BRANCH|ALIAS (0, 0)
:jr rs1 is RV32 & RVI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0 & op1519>1
{
local ea:$(XLEN) = rs1 & ~1;
call [ea];
}
# ret 00008067 ffffffff BRANCH|ALIAS (0, 0)
:ret is RV32 & RVI & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0 & op1519=1
{
local ea:$(XLEN) = ra & ~1;
return [ea];
}
# lb d,o(s) 00000003 0000707f BYTE|DREF (0, 1)
:lb rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x0
{
local ea:$(XLEN) = rs1 + immI;
rd = sext(*[ram]:1 ea);
}
# lbu d,o(s) 00004003 0000707f BYTE|DREF (0, 1)
:lbu rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x4
{
local ea:$(XLEN) = rs1 + immI;
rd = zext(*[ram]:1 ea);
}
# lh d,o(s) 00001003 0000707f WORD|DREF (0, 2)
:lh rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x1
{
local ea:$(XLEN) = rs1 + immI;
rd = sext(*[ram]:2 ea);
}
# lhu d,o(s) 00005003 0000707f WORD|DREF (0, 2)
:lhu rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x5
{
local ea:$(XLEN) = rs1 + immI;
rd = zext(*[ram]:2 ea);
}
# lui d,u 00000037 0000007f SIMPLE (0, 0)
:lui rd,immU is RV32 & RVI & immU & rd & op0001=0x3 & op0204=0x5 & op0506=0x1
{
rd = immU << 12;
}
# lw d,o(s) 00002003 0000707f DWORD|DREF (0, 4)
:lw rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x2
{
local ea:$(XLEN) = rs1 + immI;
assignW(rd, *[ram]:4 ea);
}
# or d,s,t 00006033 fe00707f SIMPLE (0, 0)
:or rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x0
{
rd = rs1 | rs2;
}
# ori d,s,j 00006013 0000707f SIMPLE (0, 0)
:ori rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x6
{
rd = rs1 | immI;
}
# sb t,q(s) 00000023 0000707f BYTE|DREF (0, 1)
:sb rs2,immS(rs1) is RV32 & RVI & immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x0
{
local ea:$(XLEN) = rs1 + immS;
*[ram]:1 ea = rs2:1;
}
# sh t,q(s) 00001023 0000707f WORD|DREF (0, 2)
:sh rs2,immS(rs1) is RV32 & RVI & immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x1
{
local ea:$(XLEN) = rs1 + immS;
*[ram]:2 ea = rs2:2;
}
# sll d,s,t 00001033 fe00707f SIMPLE (0, 0)
:sll rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x1 & funct7=0x0
{
local shift:$(XLEN) = rs2 & 0x3f;
rd = rs1 << shift;
}
# slli d,s,> 00001013 fc00707f SIMPLE (0, 0)
:slli rd,rs1,shamt6 is RV32 & RVI & rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x1 & op2631=0x0
{
rd = rs1 << shamt6;
}
# slt d,s,t 00002033 fe00707f SIMPLE (0, 0)
:slt rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0
{
rd = zext(rs1 s< rs2);
}
# slti d,s,j 00002013 0000707f SIMPLE (0, 0)
:slti rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x2
{
rd = zext(rs1 s< immI);
}
# sltiu d,s,j 00003013 0000707f SIMPLE (0, 0)
:sltiu rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x3
{
rd = zext(rs1 < immI);
}
# sltu d,s,t 00003033 fe00707f SIMPLE (0, 0)
:sltu rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x0
{
rd = zext(rs1 < rs2);
}
# sra d,s,t 40005033 fe00707f SIMPLE (0, 0)
:sra rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x20
{
local shift:$(XLEN) = rs2 & 0x3f;
rd = rs1 s>> shift;
}
# srai d,s,> 40005013 fc00707f SIMPLE (0, 0)
:srai rd,rs1,shamt6 is RV32 & RVI & rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x10
{
rd = rs1 s>> shamt6;
}
# srl d,s,t 00005033 fe00707f SIMPLE (0, 0)
:srl rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x0
{
local shift:$(XLEN) = rs2 & 0x3f;
rd = rs1 >> shift;
}
# srli d,s,> 00005013 fc00707f SIMPLE (0, 0)
:srli rd,rs1,shamt6 is RV32 & RVI & rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x0
{
rd = rs1 >> shamt6;
}
# sub d,s,t 40000033 fe00707f SIMPLE (0, 0)
:sub rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519!=0
{
rd = rs1 - rs2;
}
# neg d,t 40000033 fe0ff07f ALIAS (0, 0)
:neg rd,rs2 is RV32 & RVI & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0
{
rd = -rs2;
}
# sw t,q(s) 00002023 0000707f DWORD|DREF (0, 4)
:sw rs2,immS(rs1) is RV32 & RVI & immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x2
{
local ea:$(XLEN) = rs1 + immS;
*[ram]:4 ea = rs2:4;
}
# unimp c0001073 ffffffff SIMPLE (0, 0)
:unimp is RV32 & RVI & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op1531=0x18000
{
}
# xor d,s,t 00004033 fe00707f SIMPLE (0, 0)
:xor rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x0
{
rd = rs1 ^ rs2;
}
# xori d,s,j 00004013 0000707f SIMPLE (0, 0)
:xori rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4 & op2031!=0xfff
{
rd = rs1 ^ immI;
}
# not d,s fff04013 fff0707f ALIAS (0, 0)
:not rd,rs1 is RV32 & RVI & rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4 & op2031=0xfff
{
rd = ~rs1;
}

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# RV32M Standard Extension
# div d,s,t 02004033 fe00707f SIMPLE (0, 0)
:div rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x1
{
rd = rs1 s/ rs2;
}
# divu d,s,t 02005033 fe00707f SIMPLE (0, 0)
:divu rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x1
{
rd = rs1 / rs2;
}
# mul d,s,t 02000033 fe00707f SIMPLE (0, 0)
:mul rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x1
{
rd = rs1 * rs2;
}
# mulh d,s,t 02001033 fe00707f SIMPLE (0, 0)
:mulh rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x1 & funct7=0x1
{
local trs1:$(XLEN2) = sext(rs1);
local trs2:$(XLEN2) = sext(rs2);
local tmp:$(XLEN2) = trs1 * trs2;
rd = tmp($(XLEN));
}
# mulhsu d,s,t 02002033 fe00707f SIMPLE (0, 0)
:mulhsu rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x1
{
local trs1:$(XLEN2) = sext(rs1);
local trs2:$(XLEN2) = zext(rs2);
local tmp:$(XLEN2) = trs1 * trs2;
rd = tmp($(XLEN));
}
# mulhu d,s,t 02003033 fe00707f SIMPLE (0, 0)
:mulhu rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x1
{
local trs1:$(XLEN2) = zext(rs1);
local trs2:$(XLEN2) = zext(rs2);
local tmp:$(XLEN2) = trs1 * trs2;
rd = tmp($(XLEN));
}
# rem d,s,t 02006033 fe00707f SIMPLE (0, 0)
:rem rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x1
{
rd = rs1 s% rs2;
}
# remu d,s,t 02007033 fe00707f SIMPLE (0, 0)
:remu rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x1
{
rd = rs1 % rs2;
}

322
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# RV32Q Standard Extension
#TODO fix q
#FIXME fix q
@if FPSIZE == "128"
# fadd.q D,S,T 06007053 fe00707f SIMPLE (0, 0)
:fadd.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x3
{
frd = frs1 f+ frs2;
}
# fadd.q D,S,T,m 06000053 fe00007f SIMPLE (0, 0)
:fadd.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x3
{
frd = frs1 f+ frs2;
}
# fclass.q d,S e6001053 fff0707f SIMPLE (0, 0)
:fclass.q rd,frs1 is RV32 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x73 & op2024=0x0
{
#TODO
# rd = 0;
# rd[0, 1] = 0; #TODO - inf
# rd[1, 1] = 0; #TODO - norm num
# rd[2, 1] = 0; #TODO - subnorm num
# rd[3, 1] = 0; #TODO - 0
# rd[4, 1] = 0; #TODO + 0
# rd[5, 1] = 0; #TODO + norm num
# rd[6, 1] = 0; #TODO + subnorm num
# rd[7, 1] = 0; #TODO + inf
# rd[8, 1] = 0; #TODO snan
# rd[9, 1] = 0; #TODO qnan
}
# fcvt.d.q D,S 42307053 fff0707f SIMPLE (0, 0)
:fcvt.d.q frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x21 & op2024=0x3
{
#TODO quad to double
}
# fcvt.d.q D,S,m 42300053 fff0007f SIMPLE (0, 0)
:fcvt.d.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x21 & op2024=0x3
{
#TODO double to quad
}
# fcvt.q.d D,S 46100053 fff0707f SIMPLE (0, 0)
:fcvt.q.d frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x23 & op2024=0x1
{
frd = float2float(frs1);
}
# fcvt.q.s D,S 46000053 fff0707f SIMPLE (0, 0)
:fcvt.q.s frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x23 & op2024=0x0
{
frd = float2float(frs1);
}
# fcvt.q.w D,s d6000053 fff0707f SIMPLE (0, 0)
:fcvt.q.w frd,rs1 is RV32 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x6b & op2024=0x0
{
frd = int2float(rs1);
}
# fcvt.q.wu D,s d6100053 fff0707f SIMPLE (0, 0)
:fcvt.q.wu frd,rs1 is RV32 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x6b & op2024=0x1
{
frd = int2float(rs1);
}
# fcvt.s.q D,S 40307053 fff0707f SIMPLE (0, 0)
:fcvt.s.q frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x20 & op2024=0x3
{
frd = float2float(frs1);
}
# fcvt.s.q D,S,m 40300053 fff0007f SIMPLE (0, 0)
:fcvt.s.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x3
{
frd = float2float(frs1);
}
# fcvt.w.q d,S c6007053 fff0707f SIMPLE (0, 0)
:fcvt.w.q rd,frs1 is RV32 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x63 & op2024=0x0
{
rd = trunc(frs1);
}
# fcvt.w.q d,S,m c6000053 fff0007f SIMPLE (0, 0)
:fcvt.w.q rd,frs1,FRM is RV32 & RVQ & frs1 & FRM & op1214!=7 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x0
{
rd = trunc(frs1);
}
# fcvt.wu.q d,S c6107053 fff0707f SIMPLE (0, 0)
:fcvt.wu.q rd,frs1 is RV32 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x63 & op2024=0x1
{
rd = trunc(frs1);
}
# fcvt.wu.q d,S,m c6100053 fff0007f SIMPLE (0, 0)
:fcvt.wu.q rd,frs1,FRM is RV32 & RVQ & frs1 & FRM & op1214!=7 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x1
{
rd = trunc(frs1);
}
# fdiv.q D,S,T 1e007053 fe00707f SIMPLE (0, 0)
:fdiv.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0xf
{
local tfrs1:$(QFLEN) = frs1;
local tfrs2:$(QFLEN) = frs2;
local result:$(QFLEN) = tfrs1 f/ tfrs2;
frd = result;
}
# fdiv.q D,S,T,m 1e000053 fe00007f SIMPLE (0, 0)
:fdiv.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xf
{
local tfrs1:$(QFLEN) = frs1;
local tfrs2:$(QFLEN) = frs2;
local result:$(QFLEN) = tfrs1 f/ tfrs2;
frd = result;
}
# feq.q d,S,T a6002053 fe00707f SIMPLE (0, 0)
:feq.q rd,frs1,frs2 is RV32 & RVQ & frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x53
{
rd = zext(frs1 f== frs2);
}
# fle.q d,S,T a6000053 fe00707f SIMPLE (0, 0)
:fle.q rd,frs1,frs2 is RV32 & RVQ & frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x53
{
rd = zext(frs1 f<= frs2);
}
# flq D,o(s) 00004007 0000707f OWORD|DREF (0, 16)
:flq frd,immI(rs1) is RV32 & RVQ & immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x4
{
local ea:$(XLEN) = immI + rs1;
frd = *[ram]:16 ea;
}
# flt.q d,S,T a6001053 fe00707f SIMPLE (0, 0)
:flt.q rd,frs1,frs2 is RV32 & RVQ & frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x53
{
rd = zext(frs1 f< frs2);
}
# fmadd.q D,S,T,R 06007043 0600707f SIMPLE (0, 0)
:fmadd.q frd,frs1,frs2,frs3 is RV32 & RVQ & frs1 & frd & frs2 & frs3 & op0001=0x3 & op0204=0x0 & op0506=0x2 & funct3=0x7 & op2526=0x3
{
frd = (frs1 f* frs2) f+ frs3;
}
# fmadd.q D,S,T,R,m 06000043 0600007f SIMPLE (0, 0)
:fmadd.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & frs3 & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x3
{
frd = (frs1 f* frs2) f+ frs3;
}
# fmax.q D,S,T 2e001053 fe00707f SIMPLE (0, 0)
:fmax.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x17
{
local tmpfrs1 = frs1;
local tmpfrs2 = frs2;
frd = tmpfrs1;
if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next;
if (nan(tmpfrs2)) goto inst_next;
frd = tmpfrs2;
if (nan(tmpfrs1)) goto inst_next;
if (tmpfrs2 f> tmpfrs1) goto inst_next;
frd = tmpfrs1;
}
# fmin.q D,S,T 2e000053 fe00707f SIMPLE (0, 0)
:fmin.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x17
{
local tmpfrs1 = frs1;
local tmpfrs2 = frs2;
frd = tmpfrs1;
if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next;
if (nan(tmpfrs2)) goto inst_next;
frd = tmpfrs2;
if (nan(tmpfrs1)) goto inst_next;
if (tmpfrs2 f<= tmpfrs1) goto inst_next;
frd = tmpfrs1;
}
# fmsub.q D,S,T,R 06007047 0600707f SIMPLE (0, 0)
:fmsub.q frd,frs1,frs2,frs3 is RV32 & RVQ & frs1 & frd & frs2 & frs3 & op0001=0x3 & op0204=0x1 & op0506=0x2 & funct3=0x7 & op2526=0x3
{
frd = (frs1 f* frs2) f- frs3;
}
# fmsub.q D,S,T,R,m 06000047 0600007f SIMPLE (0, 0)
:fmsub.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & frs3 & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x3
{
frd = (frs1 f* frs2) f- frs3;
}
# fmul.q D,S,T 16007053 fe00707f SIMPLE (0, 0)
:fmul.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0xb
{
frd = frs1 f* frs2;
}
# fmul.q D,S,T,m 16000053 fe00007f SIMPLE (0, 0)
:fmul.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xb
{
frd = frs1 f* frs2;
}
# fmv.q.x D,s f6000053 fff0707f SIMPLE (64, 0)
:fmv.q.x frd,rs1 is RV32 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x7b & op2024=0x0
{
frd = int2float(rs1);
}
# fmv.x.q d,S e6000053 fff0707f SIMPLE (64, 0)
:fmv.x.q rd,frs1 is RV32 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x73 & op2024=0x0
{
rd = trunc(frs1);
}
# fnmadd.q D,S,T,R 0600704f 0600707f SIMPLE (0, 0)
:fnmadd.q frd,frs1,frs2,frs3 is RV32 & RVQ & frs1 & frd & frs2 & frs3 & op0001=0x3 & op0204=0x3 & op0506=0x2 & funct3=0x7 & op2526=0x3
{
frd = (f- (frs1 f* frs2)) f- frs3;
}
# fnmadd.q D,S,T,R,m 0600004f 0600007f SIMPLE (0, 0)
:fnmadd.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & frs3 & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x3
{
frd = (f- (frs1 f* frs2)) f- frs3;
}
# fnmsub.q D,S,T,R 0600704b 0600707f SIMPLE (0, 0)
:fnmsub.q frd,frs1,frs2,frs3 is RV32 & RVQ & frs1 & frd & frs2 & frs3 & op0001=0x3 & op0204=0x2 & op0506=0x2 & funct3=0x7 & op2526=0x3
{
frd = (f- (frs1 f* frs2)) f+ frs3;
}
# fnmsub.q D,S,T,R,m 0600004b 0600007f SIMPLE (0, 0)
:fnmsub.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & frs3 & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x3
{
frd = (f- (frs1 f* frs2)) f+ frs3;
}
# fsgnj.q D,S,T 26000053 fe00707f SIMPLE (0, 0)
:fsgnj.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x13
{ local tmp = frs1;
tmp[127,1] = frs2[127,1];
frd = tmp;
}
# fsgnjn.q D,S,T 26001053 fe00707f SIMPLE (0, 0)
:fsgnjn.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x13
{
local tmp = frs1;
tmp[127,1] = !frs2[127,1];
frd = tmp;
}
# fsgnjx.q D,S,T 26002053 fe00707f SIMPLE (0, 0)
:fsgnjx.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x13
{
local tmp = frs1;
tmp[127,1] = tmp[127,1] ^ frs2[127,1];
frd = tmp;
}
:fsq frs2,immS(rs1) is RV32 & RVQ & frs2 & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x4
{
local ea:$(XLEN) = immS + rs1;
*[ram]:$(QFLEN) ea = frs2;
}
# fsqrt.q D,S 5e007053 fff0707f SIMPLE (0, 0)
:fsqrt.q frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x2f & op2024=0x0
{
frd = sqrt(frs1);
}
# fsqrt.q D,S,m 5e000053 fff0007f SIMPLE (0, 0)
:fsqrt.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2f & op2024=0x0
{
frd = sqrt(frs1);
}
# fsub.q D,S,T 0e007053 fe00707f SIMPLE (0, 0)
:fsub.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x7
{
frd = frs1 f- frs2;
}
# fsub.q D,S,T,m 0e000053 fe00007f SIMPLE (0, 0)
:fsub.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x7
{
frd = frs1 f- frs2;
}
@endif

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# RV64A Standard Extension (in addition to RV32A)
# amoadd.d d,t,0(s) 0000302f fe00707f QWORD|DREF (64, 8)
:amoadd.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x0 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
local tmp:8 = *[ram]:8 tmprs1;
rdL = tmp;
tmp = tmp + tmprs2;
*[ram]:8 tmprs1 = tmp;
}
# amoand.d d,t,0(s) 6000302f fe00707f QWORD|DREF (64, 8)
:amoand.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0xc & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
local tmp:8 = *[ram]:8 tmprs1;
rdL = tmp;
tmp = tmp & tmprs2;
*[ram]:8 tmprs1 = tmp;
}
# amomax.d d,t,0(s) a000302f fe00707f QWORD|DREF (64, 8)
:amomax.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x14 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
local tmp:8 = *[ram]:8 tmprs1;
rdL = tmp;
if (tmprs2 s<= tmp) goto inst_next;
*[ram]:8 tmprs1 = tmprs2;
}
# amomaxu.d d,t,0(s) e000302f fe00707f QWORD|DREF (64, 8)
:amomaxu.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x1c & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
local tmp:8 = *[ram]:8 tmprs1;
rdL = tmp;
if (tmprs2 <= tmp) goto inst_next;
*[ram]:8 tmprs1 = tmprs2;
}
# amomin.d d,t,0(s) 8000302f fe00707f QWORD|DREF (64, 8)
:amomin.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x10 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
local tmp:8 = *[ram]:8 tmprs1;
rdL = tmp;
if (tmprs2 s>= tmp) goto inst_next;
*[ram]:8 tmprs1 = tmprs2;
}
# amominu.d d,t,0(s) c000302f fe00707f QWORD|DREF (64, 8)
:amominu.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x18 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
local tmp:8 = *[ram]:8 tmprs1;
rdL = tmp;
if (tmprs2 >= tmp) goto inst_next;
*[ram]:8 tmprs1 = tmprs2;
}
# amoor.d d,t,0(s) 4000302f fe00707f QWORD|DREF (64, 8)
:amoor.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x8 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
local tmp:8 = *[ram]:8 tmprs1;
rdL = tmp;
tmp = tmp | tmprs2;
*[ram]:8 tmprs1 = tmp;
}
# amoswap.d d,t,0(s) 0800302f fe00707f QWORD|DREF (64, 8)
:amoswap.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x1 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
local tmp:8 = *[ram]:8 tmprs1;
rdL = tmp;
*[ram]:8 tmprs1 = tmprs2;
}
# amoxor.d d,t,0(s) 2000302f fe00707f QWORD|DREF (64, 8)
:amoxor.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x4 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
local tmp:8 = *[ram]:8 tmprs1;
rdL = tmp;
tmp = tmp ^ tmprs2;
*[ram]:8 tmprs1 = tmp;
}
# lr.d d,0(s) 1000302f fff0707f QWORD|DREF (64, 8)
:lr.d^aqrl rdL,(rs1) is RV64 & RVA & rs1 & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x2 & op2024=0x0 & aqrl
{
RESERVE_ADDRESS = rs1;
RESERVE = 1;
RESERVE_LENGTH = 8;
rdL = *[ram]:8 rs1;
}
# sc.d d,t,0(s) 1800302f fe00707f QWORD|DREF (64, 8)
:sc.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x3 & aqrl
{
local tmprs2 = rs2L;
local tmprs1 = rs1;
rdL = 1;
if (RESERVE == 0) goto inst_next;
if (RESERVE_ADDRESS != rs1) goto inst_next;
if (RESERVE_LENGTH != 8) goto inst_next;
*[ram]:8 tmprs1 = tmprs2;
rdL = 0;
RESERVE_ADDRESS = 0;
RESERVE = 0;
RESERVE_LENGTH = 0;
}

82
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# RV64D Standard Extension (in addition to RV32D)
@if FPSIZE == "64"
# fcvt.d.l D,s d2207053 fff0707f SIMPLE (64, 0)
:fcvt.d.l frd,rs1L is RV64 & RVD & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x69 & op2024=0x2
{
local tmp:8 = int2float(rs1L);
frd = tmp;
}
# fcvt.d.l D,s,m d2200053 fff0007f SIMPLE (64, 0)
:fcvt.d.l frd,rs1L,FRM is RV64 & RVD & frd & FRM & op1214!=7 & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x2
{
local tmp:8 = int2float(rs1L);
frd = tmp;
}
# fcvt.d.lu D,s d2307053 fff0707f SIMPLE (64, 0)
:fcvt.d.lu frd,rs1L is RV64 & RVD & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x69 & op2024=0x3
{
#ATTN unsigned can be an issue here
local u64:$(XLEN2) = zext(rs1L);
local tmp:8 = int2float(u64);
frd = tmp;
}
# fcvt.d.lu D,s,m d2300053 fff0007f SIMPLE (64, 0)
:fcvt.d.lu frd,rs1L,FRM is RV64 & RVD & frd & FRM & op1214!=7 & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x3
{
#ATTN unsigned can be an issue here
local u64:$(XLEN2) = zext(rs1L);
local tmp:8 = int2float(u64);
frd = tmp;
}
# fcvt.l.d d,S c2207053 fff0707f SIMPLE (64, 0)
:fcvt.l.d rdL,frs1D is RV64 & RVD & frs1D & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x61 & op2024=0x2
{
rdL = trunc(frs1D);
}
# fcvt.l.d d,S,m c2200053 fff0007f SIMPLE (64, 0)
:fcvt.l.d rdL,frs1D,FRM is RV64 & RVD & frs1D & FRM & op1214!=7 & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x2
{
rdL = trunc(frs1D);
}
# fcvt.lu.d d,S c2307053 fff0707f SIMPLE (64, 0)
:fcvt.lu.d rdL,frs1D is RV64 & RVD & frs1D & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x61 & op2024=0x3
{
#TODO unsigned
rdL = trunc(frs1D);
}
# fcvt.lu.d d,S,m c2300053 fff0007f SIMPLE (64, 0)
:fcvt.lu.d rdL,frs1D,FRM is RV64 & RVD & frs1D & FRM & op1214!=7 & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x3
{
#TODO unsigned
rdL = trunc(frs1D);
}
# fmv.d.x D,s f2000053 fff0707f SIMPLE (64, 0)
:fmv.d.x frd,rs1L is RV64 & RVD & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x79 & op2024=0x0
{
frd = rs1L;
}
:fmv.x.d rdL,frs1D is RV64 & RVD & frs1D & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x71 & op2024=0x0
{
rdL = frs1D;
}
@endif

70
Ghidra/Processors/RISCV/data/languages/riscv.rv64f.sinc Normal file
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# RV64F Standard Extension (in addition to RV32F)
@if FPSIZE != ""
# fcvt.l.s d,S c0207053 fff0707f SIMPLE (64, 0)
:fcvt.l.s rdL,frs1S is RV64 & RVF & frs1S & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x60 & op2024=0x2
{
rdL = trunc(frs1S);
}
# fcvt.l.s d,S,m c0200053 fff0007f SIMPLE (64, 0)
:fcvt.l.s rdL,frs1S,FRM is RV64 & RVF & frs1S & FRM & op1214!=7 & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x2
{
rdL = trunc(frs1S);
}
# fcvt.lu.s d,S c0307053 fff0707f SIMPLE (64, 0)
:fcvt.lu.s rdL,frs1S is RV64 & RVF & frs1S & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x60 & op2024=0x3
{
#TODO unsigned
rdL = trunc(frs1S);
}
# fcvt.lu.s d,S,m c0300053 fff0007f SIMPLE (64, 0)
:fcvt.lu.s rdL,frs1S,FRM is RV64 & RVF & frs1S & FRM & op1214!=7 & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x3
{
#TODO unsigned
rdL = trunc(frs1S);
}
# fcvt.s.l D,s d0207053 fff0707f SIMPLE (64, 0)
:fcvt.s.l frd,rs1L is RV64 & RVF & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x68 & op2024=0x2
{
local tmp:4 = int2float(rs1L);
fassignS(frd, tmp);
}
# fcvt.s.l D,s,m d0200053 fff0007f SIMPLE (64, 0)
:fcvt.s.l frd,rs1L,FRM is RV64 & RVF & frd & FRM & op1214!=7 & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x2
{
local tmp:4 = int2float(rs1L);
fassignS(frd, tmp);
}
# fcvt.s.lu D,s d0307053 fff0707f SIMPLE (64, 0)
:fcvt.s.lu frd,rs1L is RV64 & RVF & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x68 & op2024=0x3
{
#ATTN unsigned can be an issue here
local u64:$(XLEN2) = zext(rs1L);
local tmp:4 = int2float(u64);
fassignS(frd, tmp);
}
# fcvt.s.lu D,s,m d0300053 fff0007f SIMPLE (64, 0)
:fcvt.s.lu frd,rs1L,FRM is RV64 & RVF & frd & FRM & op1214!=7 & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x3
{
#ATTN unsigned can be an issue here
local u64:$(XLEN2) = zext(rs1L);
local tmp:4 = int2float(u64);
fassignS(frd, tmp);
}
@endif

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# RV64I Base Instruction Set (in addition to RV32I)
# addiw d,s,j 0000001b 0000707f SIMPLE (64, 0)
:addiw rd,rs1,immI is RV64 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 & op2031>0
{
local result = rs1 + immI;
rd = sext(result:4);
}
:sext.w rd,rs1 is RV64 & RVI & rs1 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 & op2031=0
{
local result = rs1;
rd = sext(result:4);
}
# addw d,s,t 0000003b fe00707f SIMPLE (64, 0)
:addw rd,rs1,rs2 is RV64 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x0
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
local result:4 = tmpr1 + tmpr2;
rd = sext(result);
}
# ld d,o(s) 00003003 0000707f QWORD|DREF (64, 8)
:ld rd,immI(rs1) is RV64 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x3
{
local ea:$(XLEN) = rs1 + immI;
rd = *[ram]:8 ea;
}
# lwu d,o(s) 00006003 0000707f DWORD|DREF (64, 4)
:lwu rd,immI(rs1) is RV64 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x6
{
local ea:$(XLEN) = rs1 + immI;
rd = zext(*[ram]:4 ea);
}
# sd t,q(s) 00003023 0000707f QWORD|DREF (64, 8)
:sd rs2,immS(rs1) is RV64 & RVI & immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x3
{
local ea:$(XLEN) = rs1 + immS;
*[ram]:8 ea = rs2;
}
# slliw d,s,< 0000101b fe00707f SIMPLE (64, 0)
:slliw rd,rs1,shamt5 is RV64 & RVI & rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x1 & op2531=0x0
{
local tmp:4 = rs1:4;
tmp = tmp << shamt5;
rd = sext(tmp);
}
# sllw d,s,t 0000103b fe00707f SIMPLE (64, 0)
:sllw rd,rs1,rs2 is RV64 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x1 & funct7=0x0
{
local shift:$(XLEN) = rs2 & 0x1f;
local tmp:4 = rs1:4;
tmp = tmp << shift;
rd = sext(tmp);
}
# sraiw d,s,< 4000501b fe00707f SIMPLE (64, 0)
:sraiw rd,rs1,shamt5 is RV64 & RVI & rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x20
{
local tmp:4 = rs1:4;
tmp = tmp s>> shamt5;
rd = sext(tmp);
}
# sraw d,s,t 4000503b fe00707f SIMPLE (64, 0)
:sraw rd,rs1,rs2 is RV64 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x20
{
local shift:$(XLEN) = rs2 & 0x1f;
local tmp:4 = rs1:4;
tmp = tmp s>> shift;
rd = sext(tmp);
}
# srliw d,s,< 0000501b fe00707f SIMPLE (64, 0)
:srliw rd,rs1,shamt5 is RV64 & RVI & rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x0
{
local tmp:4 = rs1:4;
tmp = tmp >> shamt5;
rd = sext(tmp);
}
# srlw d,s,t 0000503b fe00707f SIMPLE (64, 0)
:srlw rd,rs1,rs2 is RV64 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x0
{
local shift:$(XLEN) = rs2 & 0x1f;
local tmp:4 = rs1:4;
tmp = tmp >> shift;
rd = sext(tmp);
}
# subw d,s,t 4000003b fe00707f SIMPLE (64, 0)
:subw rd,rs1W,rs2W is RV64 & RVI & rs1W & rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519!=0
{
local result = rs1W - rs2W;
rd = sext(result);
}
# negw d,t 4000003b fe0ff07f ALIAS (64, 0)
:negw rd,rs2W is RV64 & RVI & rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0
{
local tmp = -rs2W;
rd = sext(tmp);
}

45
Ghidra/Processors/RISCV/data/languages/riscv.rv64m.sinc Normal file
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# RV64M Standard Exention (in addition to RV32M)
# divuw d,s,t 0200503b fe00707f SIMPLE (64, 0)
:divuw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x1
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
rd = sext(tmpr1 / tmpr2);
}
# divw d,s,t 0200403b fe00707f SIMPLE (64, 0)
:divw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x4 & funct7=0x1
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
rd = sext(tmpr1 s/ tmpr2);
}
# mulw d,s,t 0200003b fe00707f SIMPLE (64, 0)
:mulw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x1
{
local tmp:4 = rs1:4 * rs2:4;
rd = sext(tmp);
}
# remuw d,s,t 0200703b fe00707f SIMPLE (64, 0)
:remuw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x7 & funct7=0x1
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
rd = sext(tmpr1 % tmpr2);
}
# remw d,s,t 0200603b fe00707f SIMPLE (64, 0)
:remw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x6 & funct7=0x1
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
rd = sext(tmpr1 s% tmpr2);
}

62
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# RV64Q Standard Extension (in addition to RV32Q)
#TODO fix q
#FIXME fix q
@if FPSIZE == "128"
# fcvt.l.q d,S c6207053 fff0707f SIMPLE (64, 0)
:fcvt.l.q rd,frs1 is RV64 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x63 & op2024=0x2
{
rd = trunc(frs1);
}
# fcvt.l.q d,S,m c6200053 fff0007f SIMPLE (64, 0)
:fcvt.l.q rd,frs1,FRM is RV64 & RVQ & frs1 & FRM & op1214!=7 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x2
{
rd = trunc(frs1);
}
# fcvt.lu.q d,S c6307053 fff0707f SIMPLE (64, 0)
:fcvt.lu.q rd,frs1 is RV64 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x63 & op2024=0x3
{
rd = trunc(frs1);
}
# fcvt.lu.q d,S,m c6300053 fff0007f SIMPLE (64, 0)
:fcvt.lu.q rd,frs1,FRM is RV64 & RVQ & frs1 & FRM & op1214!=7 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x3
{
rd = trunc(frs1);
}
# fcvt.q.l D,s d6207053 fff0707f SIMPLE (64, 0)
:fcvt.q.l frd,rs1 is RV64 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x6b & op2024=0x2
{
frd = int2float(rs1);
}
# fcvt.q.l D,s,m d6200053 fff0007f SIMPLE (64, 0)
:fcvt.q.l frd,rs1,FRM is RV64 & RVQ & frd & FRM & op1214!=7 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x2
{
frd = int2float(rs1);
}
# fcvt.q.lu D,s d6307053 fff0707f SIMPLE (64, 0)
:fcvt.q.lu frd,rs1 is RV64 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x6b & op2024=0x3
{
frd = int2float(rs1);
}
# fcvt.q.lu D,s,m d6300053 fff0007f SIMPLE (64, 0)
:fcvt.q.lu frd,rs1,FRM is RV64 & RVQ & frd & FRM & op1214!=7 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x3
{
frd = int2float(rs1);
}
@endif

371
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# RVC Standard Extension for Compressed Instructions
# c.add d,CV 00009002 0000f003 SIMPLE (0, 0)
:c.add crd,crs2 is RVC & crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1 & cop0711!=0 & cop0206!=0
{
crd = crd + crs2;
}
# c.addi d,Co 00000001 0000e003 SIMPLE (0, 0)
:c.addi crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x0 & cop0711!=0 & (cop1212!=0 | cop0206!=0)
{
crd = crd + cimmI;
}
:c.nop is RVC & cop0001=0x1 & cop1315=0x0 & cop0711=0 & cop1212=0 & cop0206=0
{
local NOP:1 = 0;
NOP = NOP;
}
# c.addi16sp Cc,CL 00006101 0000ef83 SIMPLE (0, 0)
:c.addi16sp sp,caddi16spimm is RVC & cop0711=0x2 & caddi16spimm & sp & cop0001=0x1 & cop1315=0x3 & cop0512!=0
{
sp = sp + caddi16spimm;
}
# c.addi4spn Ct,Cc,CK 00000000 0000e003 SIMPLE (0, 0)
:c.addi4spn cr0204s,sp,caddi4spnimm is RVC & caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0 & cop0512!=0
{
cr0204s = sp + caddi4spnimm;
}
@if ADDRSIZE == "64" || ADDRSIZE == "128"
# c.addiw d,Co 00002001 0000e003 SIMPLE (64, 0)
:c.addiw crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x1 & cop0711!=0
{
local tmp:8 = crd + cimmI;
crd = sext(tmp:4);
}
@endif
@if ADDRSIZE == "64" || ADDRSIZE == "128"
# c.addw Cs,Ct 00009c21 0000fc63 SIMPLE (64, 0)
:c.addw cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x7
{
local tmp:4 = cr0709s:4 + cr0204s:4;
cr0709s = sext(tmp);
}
@endif
# c.and Cs,Ct 00008c61 0000fc63 SIMPLE (0, 0)
:c.and cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x3 & cop1012=0x3
{
cr0709s = cr0709s & cr0204s;
}
# c.andi Cs,Co 00008801 0000ec03 SIMPLE (0, 0)
:c.andi cr0709s,cimmI is RVC & cimmI & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x2
{
cr0709s = cr0709s & cimmI;
}
# c.beqz Cs,Cp 0000c001 0000e003 CONDBRANCH (0, 0)
:c.beqz cr0709s,cbimm is RVC & cbimm & cr0709s & cop0001=0x1 & cop1315=0x6
{
if (cr0709s == 0) goto cbimm;
}
# c.bnez Cs,Cp 0000e001 0000e003 CONDBRANCH (0, 0)
:c.bnez cr0709s,cbimm is RVC & cbimm & cr0709s & cop0001=0x1 & cop1315=0x7
{
if (cr0709s != 0) goto cbimm;
}
# c.ebreak 00009002 0000ffff SIMPLE (0, 0)
:c.ebreak is RVC & cop0001=0x2 & cop1315=0x4 & cop0212=0x400
{
}
@if (ADDRSIZE == "32" || ADDRSIZE == "64") && FPSIZE == "64"
# c.fld CD,Cl(Cs) 00002000 0000e003 QWORD|DREF (0, 8)
:c.fld cfr0204s,cldimm(cr0709s) is RVC & RVD & cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x1 & cldimm
{
local ea:$(XLEN) = cldimm + cr0709s;
cfr0204s = *[ram]:8 ea;
}
@endif
@if (ADDRSIZE == "32" || ADDRSIZE == "64") && FPSIZE == "64"
# c.fldsp D,Cn(Cc) 00002002 0000e003 QWORD|DREF (0, 8)
:c.fldsp cfrd,cldspimm(sp) is RVC & RVD & cfrd & sp & cop0001=0x2 & cop1315=0x1 & cldspimm
{
local ea:$(XLEN) = cldspimm + sp;
cfrd = *[ram]:8 ea;
}
@endif
@if ADDRSIZE == "32" && FPSIZE != ""
# c.flw CD,Ck(Cs) 00006000 0000e003 DWORD|DREF (32, 4)
:c.flw cfr0204s,clwimm(cr0709s) is RVC & RVF & cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x3 & clwimm
{
local ea:$(XLEN) = clwimm + cr0709s;
cfr0204s = *[ram]:4 ea;
}
@endif
@if ADDRSIZE == "32" && FPSIZE != ""
# c.flwsp D,Cm(Cc) 00006002 0000e003 DWORD|DREF (32, 4)
:c.flwsp cfrd,clwspimm(sp) is RVC & RVF & cfrd & sp & cop0001=0x2 & cop1315=0x3 & clwspimm
{
local ea:$(XLEN) = clwspimm + sp;
cfrd = *[ram]:4 ea;
}
@endif
@if ADDRSIZE == "32" || ADDRSIZE == "64"
# c.fsd CD,Cl(Cs) 0000a000 0000e003 QWORD|DREF (0, 8)
:c.fsd cfr0204s,cldimm(cr0709s) is RVC & RVD & cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x5 & cldimm
{
local ea:$(XLEN) = cldimm + cr0709s;
*[ram]:8 ea = cfr0204s;
}
@endif
@if ADDRSIZE == "32" || ADDRSIZE == "64"
# c.fsdsp CT,CN(Cc) 0000a002 0000e003 QWORD|DREF (0, 8)
:c.fsdsp cfr0206,csdspimm(sp) is RVC & RVD & cfr0206 & sp & cop0001=0x2 & cop1315=0x5 & csdspimm
{
local ea:$(XLEN) = csdspimm + sp;
*[ram]:8 ea = cfr0206;
}
@endif
@if ADDRSIZE == "32"
# c.fsw CD,Ck(Cs) 0000e000 0000e003 DWORD|DREF (32, 4)
:c.fsw cfr0204s,clwimm(cr0709s) is RVC & RVF & cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x7 & clwimm
{
local ea:$(XLEN) = clwimm + cr0709s;
*[ram]:4 ea = cfr0204s;
}
@endif
@if ADDRSIZE == "32"
# c.fswsp CT,CM(Cc) 0000e002 0000e003 DWORD|DREF (32, 4)
:c.fswsp cfr0206,cswspimm(sp) is RVC & RVF & cfr0206 & sp & cop0001=0x2 & cop1315=0x7 & cswspimm
{
local ea:$(XLEN) = cswspimm + sp;
*[ram]:4 ea = cfr0206:4;
}
@endif
# c.j Ca 0000a001 0000e003 BRANCH (0, 0)
:c.j cjimm is RVC & cjimm & cop0001=0x1 & cop1315=0x5
{
goto cjimm;
}
@if ADDRSIZE == "32"
# c.jal Ca 00002001 0000e003 JSR (32, 0)
:c.jal cjimm is RVC & cjimm & cop0001=0x1 & cop1315=0x1
{
ra = inst_next;
call cjimm;
}
@endif
# c.jalr d 00009002 0000f07f JSR (0, 0)
:c.jalr crd is RVC & crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x1 & cop0711!=0
{
ra = inst_next;
call [crd];
}
# c.jr d 00008002 0000f07f BRANCH (0, 0)
:c.jr crd is RVC & crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0 & cop0711>1
{
goto [crd];
}
# ret 00008082 0000ffff BRANCH|ALIAS (0, 0)
:ret is RVC & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0 & cop0711=1
{
return [ra];
}
@if ADDRSIZE == "64" || ADDRSIZE == "128"
# c.ld Ct,Cl(Cs) 00006000 0000e003 QWORD|DREF (64, 8)
:c.ld cr0204s,cldimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x3 & cldimm
{
local ea:$(XLEN) = cldimm + cr0709s;
zassignD(cr0204s, *[ram]:8 ea);
}
@endif
@if ADDRSIZE == "128"
:c.lq cr0204s,clqimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x1 & clqimm
{
local ea:$(XLEN) = clqimm + cr0709s;
cr0204s = *[ram]:16 ea;
}
@endif
@if ADDRSIZE == "64" || ADDRSIZE == "128"
# c.ldsp d,Cn(Cc) 00006002 0000e003 QWORD|DREF (64, 8)
:c.ldsp crd,cldspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x3 & cldspimm & cop0711!=0
{
local ea:$(XLEN) = cldspimm + sp;
zassignD(crd, *[ram]:8 ea);
}
@endif
@if ADDRSIZE == "128"
:c.lqsp crd,clqspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x3 & clqspimm & cop0711!=0
{
local ea:$(XLEN) = clqspimm + sp;
crd = *[ram]:16 ea;
}
@endif
# c.li d,Co 00004001 0000e003 SIMPLE (0, 0)
:c.li crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x2 & cop0711!=0
{
crd = cimmI;
}
# c.lui d,Cu 00006001 0000e003 SIMPLE (0, 0)
:c.lui crd,cbigimm is RVC & cop0711!=0 & cop0711!=2 & crd & cbigimm & cop0001=0x1 & cop1315=0x3 & cop0711!=0 & cop0711!=2 & (cop1212!=0 | cop0206!=0)
{
crd = cbigimm << 12;
}
# c.lw Ct,Ck(Cs) 00004000 0000e003 DWORD|DREF (0, 4)
:c.lw cr0204s,clwimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x2 & clwimm
{
local ea:$(XLEN) = clwimm + cr0709s;
zassignW(cr0204s, *[ram]:4 ea);
}
# c.lwsp d,Cm(Cc) 00004002 0000e003 SIMPLE (0, 0)
:c.lwsp crd,clwspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x2 & clwspimm & cop0711!=0
{
local ea:$(XLEN) = clwspimm + sp;
zassignW(crd, *[ram]:4 ea);
}
# c.mv d,CV 00008002 0000f003 SIMPLE (0, 0)
:c.mv crd,crs2 is RVC & crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0 & cop0711!=0 & cop0206!=0
{
crd = crs2;
}
# c.or Cs,Ct 00008c41 0000fc63 SIMPLE (0, 0)
:c.or cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x2 & cop1012=0x3
{
cr0709s = cr0709s | cr0204s;
}
@if ADDRSIZE == "64" || ADDRSIZE == "128"
# c.sd Ct,Cl(Cs) 0000e000 0000e003 QWORD|DREF (64, 8)
:c.sd cr0204s,cldimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x7 & cldimm
{
local ea:$(XLEN) = cldimm + cr0709s;
*[ram]:8 ea = cr0204s:8;
}
@endif
@if ADDRSIZE == "64" || ADDRSIZE == "128"
# c.sdsp CV,CN(Cc) 0000e002 0000e003 QWORD|DREF (64, 8)
:c.sdsp crs2,csdspimm(sp) is RVC & crs2 & sp & cop0001=0x2 & cop1315=0x7 & csdspimm
{
local ea:$(XLEN) = csdspimm + sp;
*[ram]:8 ea = crs2:8;
}
@endif
# c.slli d,C> 00000002 0000e003 SIMPLE (0, 0)
:c.slli crd,c6imm is RVC & crd & c6imm & cop0001=0x2 & cop1315=0x0 & cop0711!=0
{
crd = crd << c6imm;
}
#TODO hint?
# c.slli64 d 00000002 0000f07f SIMPLE (0, 0)
:c.slli64 crd is RVC & crd & cop0001=0x2 & cop1315=0x0 & cop0206=0x0 & cop1212=0x0 & cop0711!=0
{
crd = crd << 0;
}
# c.srai Cs,C> 00008401 0000ec03 SIMPLE (0, 0)
:c.srai cr0709s,c6imm is RVC & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x1
{
cr0709s = cr0709s s>> c6imm;
}
#TODO hint?
# c.srai64 Cs 00008401 0000fc7f SIMPLE (0, 0)
:c.srai64 cr0709s is RVC & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0206=0x0 & cop1012=0x1
{
cr0709s = cr0709s s>> 0;
}
# c.srli Cs,C> 00008001 0000ec03 SIMPLE (0, 0)
:c.srli cr0709s,c6imm is RVC & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x0
{
cr0709s = cr0709s >> c6imm;
}
#TODO hint?
# c.srli64 Cs 00008001 0000fc7f SIMPLE (0, 0)
:c.srli64 cr0709s is RVC & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0206=0x0 & cop1012=0x0
{
cr0709s = cr0709s >> 0;
}
# c.sub Cs,Ct 00008c01 0000fc63 SIMPLE (0, 0)
:c.sub cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x3
{
cr0709s = cr0709s - cr0204s;
}
@if ADDRSIZE == "64" || ADDRSIZE == "128"
# c.subw Cs,Ct 00009c01 0000fc63 SIMPLE (64, 0)
:c.subw cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x7
{
local tmp:4 = cr0709s:4 - cr0204s:4;
cr0709s = sext(tmp);
}
@endif
# c.sw Ct,Ck(Cs) 0000c000 0000e003 DWORD|DREF (0, 4)
:c.sw cr0204s,clwimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x6 & clwimm
{
local ea:$(XLEN) = clwimm + cr0709s;
*[ram]:4 ea = cr0204s:4;
}
@if ADDRSIZE == "128"
:c.sq cr0204s,clqimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x5 & clqimm
{
local ea:$(XLEN) = clqimm + cr0709s;
*[ram]:16 ea = cr0204s;
}
@endif
@if ADDRSIZE == "128"
:c.sqsp crs2,csqspimm(sp) is RVC & crs2 & sp & cop0001=0x2 & cop1315=0x5 & csqspimm
{
local ea:$(XLEN) = csqspimm + sp;
*[ram]:16 ea = crs2;
}
@endif
# c.swsp CV,CM(Cc) 0000c002 0000e003 DWORD|DREF (0, 4)
:c.swsp crs2,cswspimm(sp) is RVC & crs2 & sp & cop0001=0x2 & cop1315=0x6 & cswspimm
{
local ea:$(XLEN) = cswspimm + sp;
*[ram]:4 ea = crs2:4;
}
# c.unimp 00000000 0000ffff SIMPLE (0, 0)
:c.unimp is RVC & cop0001=0x0 & cop1315=0x0 & cop0212=0x0
{
trap();
}
# c.xor Cs,Ct 00008c21 0000fc63 SIMPLE (0, 0)
:c.xor cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x3
{
cr0709s = cr0709s ^ cr0204s;
}

359
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#TODO these names are madeup. do real ones exist?
#TODO go through and use these instead of numbers
@define HFLEN 2
@define SFLEN 4
@define DFLEN 8
@define QFLEN 16
@define HXLEN 2
@define WXLEN 4
@define DXLEN 8
@define QXLEN 16
define pcodeop trap;
# possible tokens: r0711 r1519 r2024 r2731 cr0206 cr0711 cd0711
rs1: r1519 is r1519 & op1519!=0 { export r1519; }
rs1: zero is r1519 & zero & op1519=0 { export 0:$(XLEN); }
rs2: r2024 is r2024 & op2024!=0 { export r2024; }
rs2: zero is r2024 & zero & op2024=0 { export 0:$(XLEN); }
rd: r0711 is r0711 & op0711!=0 { export r0711; }
rd: zero is r0711 & zero & op0711=0 { export 0:$(XLEN); }
@if ADDRSIZE == "32"
rs1W: r1519 is RV32 & r1519 & op1519!=0 { export r1519; }
rs1W: zero is RV32 & r1519 & zero & op1519=0 { export 0:$(XLEN); }
rs2W: r2024 is RV32 & r2024 & op2024!=0 { export r2024; }
rs2W: zero is RV32 & r2024 & zero & op2024=0 { export 0:$(XLEN); }
#TODO dest may be bad, might need an assign macro
rdW: r0711 is RV32 & r0711 & op0711!=0 { export r0711; }
rdW: zero is RV32 & r0711 & zero & op0711=0 { export 0:$(XLEN); }
@else
rs1W: r1519 is r1519 & op1519!=0 { local tmp:4 = r1519:4; export tmp; }
rs1W: zero is r1519 & zero & op1519=0 { export 0:4; }
rs2W: r2024 is r2024 & op2024!=0 { local tmp:4 = r2024:4; export tmp; }
rs2W: zero is r2024 & zero & op2024=0 { export 0:4; }
#TODO dest may be bad, might need an assign macro
rdW: r0711 is r0711 & op0711!=0 { export r0711; }
rdW: zero is r0711 & zero & op0711=0 { export 0:8; }
@endif
#TODO does this need to be in an if/endif
@if ADDRSIZE == "64"
rs1L: r1519 is r1519 & op1519!=0 { local tmp:8 = r1519:8; export tmp; }
rs1L: zero is r1519 & zero & op1519=0 { export 0:8; }
rs2L: r2024 is r2024 & op2024!=0 { local tmp:8 = r2024:8; export tmp; }
rs2L: zero is r2024 & zero & op2024=0 { export 0:8; }
#TODO dest may be bad, might need an assign macro
rdL: r0711 is r0711 & op0711!=0 { export r0711; }
rdL: zero is r0711 & zero & op0711=0 { export 0:8; }
@endif
#TODO eh not sure if this is usable
# would only make sense to use this if the float operation
# tables for frd,frs1,frs2 could be different sizes or
# if the cast could use this export, but they have to export
# the same size and you cant 'local tmp:fmt'
# # 32-bit single-precision $(SFLEN)
# fmt: ".s" is op2526=0 { export $(SFLEN):1; }
# # 64-bit double-precision $(DFLEN)
# fmt: ".d" is op2526=1 { export $(DFLEN):1; }
# # 16-bit half-precision $(HFLEN)
# fmt: ".h" is op2526=2 { export $(HFLEN):1; }
# # 128-bit quad-precision $(QFLEN)
# fmt: ".q" is op2526=3 { export $(QFLEN):1; }
@if FPSIZE != ""
frd: fr0711 is fr0711 { export fr0711; }
frs1: fr1519 is fr1519 { export fr1519; }
frs2: fr2024 is fr2024 { export fr2024; }
frs3: fr2731 is fr2731 { export fr2731; }
#TODO dest may be bad, might need an assign macro
#frdS: fr0711 is fr0711 { local tmp = fr0711:$(SFLEN); export tmp; }
frs1S: fr1519 is fr1519 { local tmp = fr1519:$(SFLEN); export tmp; }
frs2S: fr2024 is fr2024 { local tmp = fr2024:$(SFLEN); export tmp; }
frs3S: fr2731 is fr2731 { local tmp = fr2731:$(SFLEN); export tmp; }
#TODO dest may be bad, might need an assign macro
#frdD: fr0711 is fr0711 { local tmp = fr0711:$(DFLEN); export tmp; }
frs1D: fr1519 is fr1519 { local tmp = fr1519:$(DFLEN); export tmp; }
frs2D: fr2024 is fr2024 { local tmp = fr2024:$(DFLEN); export tmp; }
frs3D: fr2731 is fr2731 { local tmp = fr2731:$(DFLEN); export tmp; }
macro fassignS(dest, src) {
@if FPSIZE == "32"
dest = src;
@else
dest = zext(src);
@endif
}
@endif
macro assignW(dest, src) {
@if ADDRSIZE == "32"
dest = src;
@else
dest = sext(src);
@endif
}
macro zassignW(dest, src) {
@if ADDRSIZE == "32"
dest = src;
@else
dest = zext(src);
@endif
}
macro zassignD(dest, src) {
@if ADDRSIZE == "64"
dest = src;
@else
dest = zext(src);
@endif
}
immI: sop2031 is sop2031 { local tmp:$(XLEN) = sop2031; export tmp; }
immS: imm is op0711 & sop2531 [ imm = (sop2531 << 5) | op0711; ] { local tmp:$(XLEN) = imm; export tmp; }
# used for goto
immSB: reloc is op0707 & op0811 & op2530 & sop3131 [ reloc = inst_start + ((sop3131 << 12) | (op2530 << 5) | (op0811 << 1) | (op0707 << 11)); ] { export *[ram]:$(XLEN) reloc; }
#immSB: reloc is op0707 & op0811 & op2530 & sop3131 [ reloc = inst_start + ((sop3131 << 12) | (op2530 << 5) | (op0811 << 1) | (op0707 << 11)); ] { export reloc; }
#NOTES this reads as '<< 12' but objdump does not
# immU: imm is sop1231 [ imm = (sop1231 << 12); ] { local tmp:$(XLEN) = imm; export tmp; }
immU: sop1231 is sop1231 { local tmp:$(XLEN) = sop1231; export tmp; }
# used for goto
immUJ: reloc is op1219 & op2020 & op2130 & sop3131 [ reloc = inst_start + ((sop3131 << 20) | (op2130 << 1) | (op2020 << 11) | (op1219 << 12)); ] { export *[ram]:$(XLEN) reloc; }
@if ADDRSIZE == "64"
shamt5: op2024 is op2024 { local tmp:$(XLEN) = op2024; export tmp; }
@endif
shamt6: imm is op2024 & op2525 [ imm = (op2525 << 5) | op2024; ] { local tmp:$(XLEN) = imm; export tmp; }
FRM: "rne" is op1214=0 { local tmp:1 = 0; export tmp; }
FRM: "rtz" is op1214=1 { local tmp:1 = 1; export tmp; }
FRM: "rdn" is op1214=2 { local tmp:1 = 2; export tmp; }
FRM: "rup" is op1214=3 { local tmp:1 = 3; export tmp; }
FRM: "rmm" is op1214=4 { local tmp:1 = 4; export tmp; }
# 5 Invalid. Reserved for future use
# 6 Invalid. Reserved for future use
FRM: "dyn" is op1214=7 { local tmp:1 = 7; export tmp; }
aqrl: "" is op2526=0 {}
aqrl: ".rl" is op2526=1 {}
aqrl: ".aq" is op2526=2 {}
aqrl: ".aqrl" is op2526=3 {}
crs1: cr0711 is cr0711 & cop0711!=0 { export cr0711; }
crs1: zero is cr0711 & zero & cop0711=0 { export 0:$(XLEN); }
crd: cd0711 is cd0711 & cop0711!=0 { export cd0711; }
crd: zero is cd0711 & zero & cop0711=0 { export 0:$(XLEN); }
crs2: cr0206 is cr0206 & cop0206!=0 { export cr0206; }
crs2: zero is cr0206 & zero & cop0206=0 { export 0:$(XLEN); }
@if FPSIZE != ""
cfrs1: cfr0711 is cfr0711 { export cfr0711; }
cfrd: cfr0711 is cfr0711 { export cfr0711; }
cfrs2: cfr0206 is cfr0206 { export cfr0206; }
@endif
#ATTN Not doing tables for the RVC registers since there is no
# zero register to worry about
cimmI: imm is scop1212 & cop0206 [ imm = (scop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = imm; export tmp; }
# used for goto
cbimm: reloc is scop1212 & cop1011 & cop0506 & cop0304 & cop0202 [ reloc = inst_start + ((scop1212 << 8) | (cop0506 << 6) | (cop0202 << 5) | (cop1011 << 3) | (cop0304 << 1)); ] { export *[ram]:$(XLEN) reloc; }
#cbimm: reloc is scop1212 & cop1011 & cop0506 & cop0304 & cop0202 [ reloc = inst_start + ((scop1212 << 8) | (cop0506 << 6) | (cop0202 << 5) | (cop1011 << 3) | (cop0304 << 1)); ] { export reloc; }
# used for goto
cjimm: reloc is scop1212 & cop1111 & cop0910 & cop0808 & cop0707 & cop0606 & cop0305 & cop0202 [ reloc = inst_start + ((scop1212 << 11) | (cop1111 << 4) | (cop0910 << 8) | (cop0808 << 10) | (cop0707 << 6) | (cop0606 << 7) | (cop0305 << 1) | (cop0202 << 5)); ] { export *[ram]:$(XLEN) reloc; }
@if ADDRSIZE == "32"
#TODO nonzero, would like to have cop0205>0
c6imm: uimm is cop1212=0 & cop0206 [ uimm = (cop0206 + 0); ] { local tmp:$(XLEN) = uimm; export tmp; }
@elif ADDRSIZE == "64"
#TODO nonzero, would like to have cop0205>0 | cop0206>0
c6imm: uimm is cop1212 & cop0206 [ uimm = (cop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = uimm; export tmp; }
@elif ADDRSIZE == "128"
c6imm: uimm is cop1212 & cop0206 [ uimm = (cop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = uimm + (64 * (uimm == 0)); export tmp; }
@endif
#NOTES not shifted
# cbigimm: imm is scop1212 & cop0206 [ imm = (scop1212 << 17) | (cop0206 << 12); ] { local tmp:$(XLEN) = imm; export tmp; }
cbigimm: imm is scop1212 & cop0206 [ imm = (scop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = imm; export tmp; }
caddi4spnimm: uimm is cop1112 & cop0710 & cop0606 & cop0505 [ uimm = (cop0710 << 6) | (cop1112 << 4) | (cop0505 << 3) | (cop0606 << 2); ] { local tmp:$(XLEN) = uimm; export tmp; }
caddi16spimm: imm is scop1212 & cop0606 & cop0505 & cop0304 & cop0202 [ imm = (scop1212 << 9) | (cop0304 << 7) | (cop0505 << 6) | (cop0202 << 5) | (cop0606 << 4); ] { local tmp:$(XLEN) = imm; export tmp; }
cldimm: uimm is cop1012 & cop0506 [ uimm = (cop1012 << 3) | (cop0506 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
clwimm: uimm is cop1012 & cop0606 & cop0505 [ uimm = (cop1012 << 3) | (cop0606 << 2) | (cop0505 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
clqimm: uimm is cop1112 & cop1010 & cop0506 [ uimm = (cop1112 << 4) | (cop1010 << 8) | (cop0506 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
cldspimm: uimm is cop1212 & cop0506 & cop0204 [ uimm = (cop1212 << 5) | (cop0506 << 3) | (cop0204 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
@if ADDRSIZE == "64"
clqspimm: uimm is cop1212 & cop0606 & cop0205 [ uimm = (cop1212 << 5) | (cop0606 << 4) | (cop0205 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
@endif
clwspimm: uimm is cop1212 & cop0406 & cop0203 [ uimm = (cop1212 << 5) | (cop0406 << 2) | (cop0203 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
csdspimm: uimm is cop0709 & cop1012 [ uimm = (cop0709 << 6) | (cop1012 << 3); ] { local tmp:$(XLEN) = uimm; export tmp; }
@if ADDRSIZE == "128"
csqspimm: uimm is cop0710 & cop1112 [ uimm = (cop0710 << 6) | (cop1112 << 4); ] { local tmp:$(XLEN) = uimm; export tmp; }
@endif
cswspimm: uimm is cop0708 & cop0912 [ uimm = (cop0708 << 6) | (cop0912 << 2); ] { local tmp:$(XLEN) = uimm; export tmp; }
#TODO this is broken
#TODO maybe 2 tables are needed for address and size
# instead of register name
# CSR have different access level, use, and accessibility
# just formatting this way for readability. Breaking up
# csr into multiples to avoid having an 'attach variables'
# with 0x1000 fields
# SEE riscv-privileged.pdf Section 'CSR Listing' for description
# 0x000-0x0ff
with csr: op3031=0 & op2829=0 {
: csr_0 is csr_0 {}
}
# 0x100-0x1ff
with csr: op3031=0 & op2829=1 {
: csr_1 is csr_1 {}
}
# 0x200-0x2ff
with csr: op3031=0 & op2829=2 {
: csr_2 is csr_2 {}
}
# 0x300-0x3ff
with csr: op3031=0 & op2829=3 {
: csr_3 is csr_3 {}
}
# 0x400-0x4ff
with csr: op3031=1 & op2829=0 {
: csr_4 is csr_4 {}
}
# 0x500-0x5ff
with csr: op3031=1 & op2829=1 {
: csr_50 is csr_50 & op2727=0 {}
: csr_58 is csr_58 & op2627=2 {}
: csr_5C is csr_5C & op2627=3 {}
}
# 0x600-0x6ff
with csr: op3031=1 & op2829=2 {
: csr_60 is csr_60 & op2727=0 {}
: csr_68 is csr_68 & op2627=2 {}
: csr_6C is csr_6C & op2627=3 {}
}
# 0x700-0x7ff
with csr: op3031=1 & op2829=3 {
: csr_70 is csr_70 & op2727=0 {}
: csr_78 is csr_78 & op2527=4 {}
: csr_7A is csr_7A & op2427=0xa {}
: csr_7B is csr_7B & op2427=0xb {}
: csr_7C is csr_7C & op2627=3 {}
}
# 0x800-0x8ff
with csr: op3031=2 & op2829=0 {
: csr_8 is csr_8 {}
}
# 0x900-0x9ff
with csr: op3031=2 & op2829=1 {
: csr_90 is csr_90 & op2727=0 {}
: csr_98 is csr_98 & op2627=2 {}
: csr_9C is csr_9C & op2627=3 {}
}
# 0xa00-0xaff
with csr: op3031=2 & op2829=2 {
: csr_A0 is csr_A0 & op2727=0 {}
: csr_A8 is csr_A8 & op2627=2 {}
: csr_AC is csr_AC & op2627=3 {}
}
# 0xb00-0xbff
with csr: op3031=2 & op2829=3 {
: csr_B0 is csr_B0 & op2727=0 {}
: csr_B8 is csr_B8 & op2627=2 {}
: csr_BC is csr_BC & op2627=3 {}
}
# 0xc00-0xcff
with csr: op3031=3 & op2829=0 {
: csr_C0 is csr_C0 & op2727=0 {}
: csr_C8 is csr_C8 & op2627=2 {}
: csr_CC is csr_CC & op2627=3 {}
}
# 0xd00-0xdff
with csr: op3031=3 & op2829=1 {
: csr_D0 is csr_D0 & op2727=0 {}
: csr_D8 is csr_D8 & op2627=2 {}
: csr_DC is csr_DC & op2627=3 {}
}
# 0xe00-0xeff
with csr: op3031=3 & op2829=2 {
: csr_E0 is csr_E0 & op2727=0 {}
: csr_E8 is csr_E8 & op2627=2 {}
: csr_EC is csr_EC & op2627=3 {}
}
# 0xf00-0xfff
with csr: op3031=3 & op2829=3 {
: csr_F0 is csr_F0 & op2727=0 {}
: csr_F8 is csr_F8 & op2627=2 {}
: csr_FC is csr_FC & op2627=3 {}
}

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# RV32/RV64 Zifencei Standard Extension
# fence.i 0000100f ffffffff SIMPLE (0, 0)
:fence.i is op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x1 & fm=0x0 & op0711=0x0 & op1527=0x0
{
}

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Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="4" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="ram"/>
<register name="gp"/>
<register name="tp"/>
</global>
<returnaddress>
<register name="ra"/>
</returnaddress>
<stackpointer register="sp" space="ram"/>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0" strategy="register">
<input>
<pentry minsize="1" maxsize="4">
<register name="a0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a1"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a2"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a3"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a4"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a5"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a6"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a7"/>
</pentry>
<pentry minsize="4" maxsize="4">
<register name="fa0"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa1"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa2"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa3"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa4"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa5"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa6"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa7"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="16" space="ram"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="a0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a1"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa0"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa1"/>
</pentry>
</output>
<unaffected>
<register name="sp"/>
<register name="gp"/>
<register name="tp"/>
<register name="s0"/>
<register name="s1"/>
<register name="s2"/>
<register name="s3"/>
<register name="s4"/>
<register name="s5"/>
<register name="s6"/>
<register name="s7"/>
<register name="s8"/>
<register name="s9"/>
<register name="s10"/>
<register name="s11"/>
<register name="fs0"/>
<register name="fs1"/>
<register name="fs2"/>
<register name="fs3"/>
<register name="fs4"/>
<register name="fs5"/>
<register name="fs6"/>
<register name="fs7"/>
<register name="fs8"/>
<register name="fs9"/>
<register name="fs10"/>
<register name="fs11"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>

22
Ghidra/Processors/RISCV/data/languages/riscv32-fp.dwarf Normal file
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<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="zero"/>
<register_mapping dwarf="1" ghidra="ra"/>
<register_mapping dwarf="2" ghidra="sp" stackpointer="true"/>
<register_mapping dwarf="3" ghidra="gp"/>
<register_mapping dwarf="4" ghidra="tp"/>
<register_mapping dwarf="5" ghidra="t0" auto_count="3"/>
<register_mapping dwarf="8" ghidra="s0"/>
<register_mapping dwarf="9" ghidra="s1"/>
<register_mapping dwarf="10" ghidra="a0" auto_count="8"/>
<register_mapping dwarf="18" ghidra="s2" auto_count="10"/>
<register_mapping dwarf="28" ghidra="t3" auto_count="4"/>
<register_mapping dwarf="32" ghidra="ft0" auto_count="8"/>
<register_mapping dwarf="40" ghidra="fs0"/>
<register_mapping dwarf="41" ghidra="fs1"/>
<register_mapping dwarf="42" ghidra="fa0" auto_count="8"/>
<register_mapping dwarf="50" ghidra="fs2" auto_count="10"/>
<register_mapping dwarf="60" ghidra="ft8" auto_count="4"/>
</register_mappings>
<call_frame_cfa value="4"/>
</dwarf>

89
Ghidra/Processors/RISCV/data/languages/riscv32.cspec Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="4" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="ram"/>
<register name="gp"/>
<register name="tp"/>
</global>
<returnaddress>
<register name="ra"/>
</returnaddress>
<stackpointer register="sp" space="ram"/>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0" strategy="register">
<input>
<pentry minsize="1" maxsize="4">
<register name="a0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a1"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a2"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a3"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a4"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a5"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a6"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a7"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="16" space="ram"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="a0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a1"/>
</pentry>
</output>
<unaffected>
<register name="sp"/>
<register name="gp"/>
<register name="tp"/>
<register name="s0"/>
<register name="s1"/>
<register name="s2"/>
<register name="s3"/>
<register name="s4"/>
<register name="s5"/>
<register name="s6"/>
<register name="s7"/>
<register name="s8"/>
<register name="s9"/>
<register name="s10"/>
<register name="s11"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>

16
Ghidra/Processors/RISCV/data/languages/riscv32.dwarf Normal file
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<dwarf>
<register_mappings>
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<register_mapping dwarf="4" ghidra="tp"/>
<register_mapping dwarf="5" ghidra="t0" auto_count="3"/>
<register_mapping dwarf="8" ghidra="s0"/>
<register_mapping dwarf="9" ghidra="s1"/>
<register_mapping dwarf="10" ghidra="a0" auto_count="8"/>
<register_mapping dwarf="18" ghidra="s2" auto_count="10"/>
<register_mapping dwarf="28" ghidra="t3" auto_count="4"/>
</register_mappings>
<call_frame_cfa value="4"/>
</dwarf>

133
Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="8" />
<default_alignment value="1" />
<default_pointer_alignment value="8" />
<pointer_size value="8" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="ram"/>
<register name="gp"/>
<register name="tp"/>
</global>
<returnaddress>
<register name="ra"/>
</returnaddress>
<stackpointer register="sp" space="ram"/>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0" strategy="register">
<input>
<pentry minsize="1" maxsize="8">
<register name="a0"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a1"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a2"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a3"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a4"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a5"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a6"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a7"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa0"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa1"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa2"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa3"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa4"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa5"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa6"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa7"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="16" space="ram"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8">
<register name="a0"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a1"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa0"/>
</pentry>
<pentry minsize="4" maxsize="8">
<register name="fa1"/>
</pentry>
</output>
<unaffected>
<register name="sp"/>
<register name="gp"/>
<register name="tp"/>
<register name="s0"/>
<register name="s1"/>
<register name="s2"/>
<register name="s3"/>
<register name="s4"/>
<register name="s5"/>
<register name="s6"/>
<register name="s7"/>
<register name="s8"/>
<register name="s9"/>
<register name="s10"/>
<register name="s11"/>
<register name="fs0"/>
<register name="fs1"/>
<register name="fs2"/>
<register name="fs3"/>
<register name="fs4"/>
<register name="fs5"/>
<register name="fs6"/>
<register name="fs7"/>
<register name="fs8"/>
<register name="fs9"/>
<register name="fs10"/>
<register name="fs11"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>

22
Ghidra/Processors/RISCV/data/languages/riscv64-fp.dwarf Normal file
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<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="zero"/>
<register_mapping dwarf="1" ghidra="ra"/>
<register_mapping dwarf="2" ghidra="sp" stackpointer="true"/>
<register_mapping dwarf="3" ghidra="gp"/>
<register_mapping dwarf="4" ghidra="tp"/>
<register_mapping dwarf="5" ghidra="t0" auto_count="3"/>
<register_mapping dwarf="8" ghidra="s0"/>
<register_mapping dwarf="9" ghidra="s1"/>
<register_mapping dwarf="10" ghidra="a0" auto_count="8"/>
<register_mapping dwarf="18" ghidra="s2" auto_count="10"/>
<register_mapping dwarf="28" ghidra="t3" auto_count="4"/>
<register_mapping dwarf="32" ghidra="ft0" auto_count="8"/>
<register_mapping dwarf="40" ghidra="fs0"/>
<register_mapping dwarf="41" ghidra="fs1"/>
<register_mapping dwarf="42" ghidra="fa0" auto_count="8"/>
<register_mapping dwarf="50" ghidra="fs2" auto_count="10"/>
<register_mapping dwarf="60" ghidra="ft8" auto_count="4"/>
</register_mappings>
<call_frame_cfa value="8"/>
</dwarf>

89
Ghidra/Processors/RISCV/data/languages/riscv64.cspec Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="8" />
<default_alignment value="1" />
<default_pointer_alignment value="8" />
<pointer_size value="8" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="ram"/>
<register name="gp"/>
<register name="tp"/>
</global>
<returnaddress>
<register name="ra"/>
</returnaddress>
<stackpointer register="sp" space="ram"/>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0" strategy="register">
<input>
<pentry minsize="1" maxsize="8">
<register name="a0"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a1"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a2"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a3"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a4"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a5"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a6"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a7"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="16" space="ram"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8">
<register name="a0"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="a1"/>
</pentry>
</output>
<unaffected>
<register name="sp"/>
<register name="gp"/>
<register name="tp"/>
<register name="s0"/>
<register name="s1"/>
<register name="s2"/>
<register name="s3"/>
<register name="s4"/>
<register name="s5"/>
<register name="s6"/>
<register name="s7"/>
<register name="s8"/>
<register name="s9"/>
<register name="s10"/>
<register name="s11"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>

16
Ghidra/Processors/RISCV/data/languages/riscv64.dwarf Normal file
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<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="zero"/>
<register_mapping dwarf="1" ghidra="ra"/>
<register_mapping dwarf="2" ghidra="sp" stackpointer="true"/>
<register_mapping dwarf="3" ghidra="gp"/>
<register_mapping dwarf="4" ghidra="tp"/>
<register_mapping dwarf="5" ghidra="t0" auto_count="3"/>
<register_mapping dwarf="8" ghidra="s0"/>
<register_mapping dwarf="9" ghidra="s1"/>
<register_mapping dwarf="10" ghidra="a0" auto_count="8"/>
<register_mapping dwarf="18" ghidra="s2" auto_count="10"/>
<register_mapping dwarf="28" ghidra="t3" auto_count="4"/>
</register_mappings>
<call_frame_cfa value="8"/>
</dwarf>

2871
Ghidra/Processors/RISCV/scripts/binutil.py Normal file
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146
Ghidra/Processors/RISCV/src/main/java/ghidra/app/plugin/core/analysis/RISCVAddressAnalyzer.java Normal file
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/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.app.plugin.core.analysis;
import ghidra.program.model.listing.ContextChangeException;
import ghidra.program.model.listing.Function;
import ghidra.program.model.listing.Instruction;
import ghidra.program.model.listing.Program;
import ghidra.program.model.listing.ProgramContext;
import java.math.BigInteger;
import ghidra.app.util.importer.MessageLog;
import ghidra.program.model.address.Address;
import ghidra.program.model.address.AddressSet;
import ghidra.program.model.address.AddressSetView;
import ghidra.program.model.lang.Processor;
import ghidra.program.model.lang.Register;
import ghidra.program.model.lang.RegisterValue;
import ghidra.program.model.symbol.Symbol;
import ghidra.program.model.symbol.SymbolUtilities;
import ghidra.program.util.SymbolicPropogator;
import ghidra.program.util.VarnodeContext;
import ghidra.util.task.TaskMonitor;
import ghidra.util.Msg;
import ghidra.util.exception.AssertException;
import ghidra.util.exception.CancelledException;
public class RISCVAddressAnalyzer extends ConstantPropagationAnalyzer {
public static final String RISCV___GLOBAL_POINTER = "__global_pointer$";
private Address gp_assumption_value;
private static final String REGISTER_GP = "gp";
private Register gp;
private static final String PROCESSOR_NAME = "RISCV";
public RISCVAddressAnalyzer() {
super(PROCESSOR_NAME);
}
@Override
public boolean canAnalyze(Program program) {
boolean canAnalyze = program.getLanguage().getProcessor().equals(
Processor.findOrPossiblyCreateProcessor(PROCESSOR_NAME));
if (!canAnalyze) {
return false;
}
gp = program.getRegister(REGISTER_GP);
return true;
}
@Override
public boolean added(Program program, AddressSetView set, TaskMonitor monitor, MessageLog log)
throws CancelledException {
gp_assumption_value = null;
// check for the __global_pointer$ symbol to see what the global gp
// value should be
checkForGlobalGP(program, set, monitor);
return super.added(program, set, monitor, log);
}
@Override
public AddressSetView flowConstants(final Program program, Address flowStart,
AddressSetView flowSet, final SymbolicPropogator symEval, final TaskMonitor monitor)
throws CancelledException {
// get the function body
final Function func = program.getFunctionManager().getFunctionContaining(flowStart);
final AddressSet coveredSet = new AddressSet();
if (func != null && gp_assumption_value != null) {
ProgramContext programContext = program.getProgramContext();
RegisterValue gpVal = programContext.getRegisterValue(gp, flowStart);
if (gpVal == null || !gpVal.hasValue()) {
gpVal = new RegisterValue(gp, BigInteger.valueOf(gp_assumption_value.getOffset()));
try {
program.getProgramContext().setRegisterValue(func.getEntryPoint(),
func.getEntryPoint(), gpVal);
}
catch (ContextChangeException e) {
// only happens for context register
throw new AssertException("unexpected", e);
}
}
}
// follow all flows building up context
ConstantPropagationContextEvaluator eval =
new ConstantPropagationContextEvaluator(trustWriteMemOption) {
private boolean mustStopNow = false;
@Override
public boolean evaluateContextBefore(VarnodeContext context, Instruction instr) {
return mustStopNow;
}
@Override
public boolean evaluateContext(VarnodeContext context, Instruction instr) {
return mustStopNow;
}
};
AddressSet resultSet = symEval.flowConstants(flowStart, null, eval, true, monitor);
resultSet.add(coveredSet);
return resultSet;
}
/**
* Check for a global GP register symbol or discovered symbol
* @param program
* @param set
* @param monitor
*/
private void checkForGlobalGP(Program program, AddressSetView set, TaskMonitor monitor) {
Symbol symbol = SymbolUtilities.getLabelOrFunctionSymbol(program,
RISCV___GLOBAL_POINTER,
err -> Msg.error(this, err));
if (symbol != null) {
gp_assumption_value = symbol.getAddress();
return;
}
}
}

49
Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/extend/RISCV_ElfExtension.java Normal file
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/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.app.util.bin.format.elf.extend;
import ghidra.app.util.bin.format.elf.*;
import ghidra.program.model.address.Address;
import ghidra.program.model.lang.*;
import ghidra.program.model.listing.Program;
import ghidra.program.model.listing.ContextChangeException;
public class RISCV_ElfExtension extends ElfExtension {
//TODO not sure about these
public static final String RISCV_PROC="RISCV";
public static final String RISCV_SUFFIX="_RISCV";
@Override
public boolean canHandle(ElfHeader elf) {
return elf.e_machine() == ElfConstants.EM_RISCV;
}
@Override
public boolean canHandle(ElfLoadHelper elfLoadHelper) {
if (!canHandle(elfLoadHelper.getElfHeader()))
return false;
Language language = elfLoadHelper.getProgram().getLanguage();
int size =language.getLanguageDescription().getSize();
return ((32 == size || 64 == size) && language.getProcessor().toString().equals(RISCV_PROC));
}
@Override
public String getDataTypeSuffix() {
return RISCV_SUFFIX;
}
}

84
Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/relocation/RISCV_ElfRelocationConstants.java Normal file
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/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.app.util.bin.format.elf.relocation;
public class RISCV_ElfRelocationConstants {
/*
* A Addend field in the relocation entry associated with the symbol
* B Base address of a shared object loaded into memory
* G Offset of the symbol into the GOT (Global Offset Table)
* S Value of the symbol in the symbol table
* GP Global Pointer register (x3)
*/
public static final int R_RISCV_NONE = 0; // None
public static final int R_RISCV_32 = 1; // Runtime relocation word32 = S + A
public static final int R_RISCV_64 = 2; // Runtime relocation word64 = S + A
public static final int R_RISCV_RELATIVE = 3; // Runtime relocation word32,64 = B + A
public static final int R_RISCV_COPY = 4; // Runtime relocation must be in executable. not allowed in shared library
public static final int R_RISCV_JUMP_SLOT = 5; // Runtime relocation word32,64 = S ;handled by PLT unless LD_BIND_NOW
public static final int R_RISCV_TLS_DTPMOD32 = 6; // TLS relocation word32 = S->TLSINDEX
public static final int R_RISCV_TLS_DTPMOD64 = 7; // TLS relocation word64 = S->TLSINDEX
public static final int R_RISCV_TLS_DTPREL32 = 8; // TLS relocation word32 = TLS + S + A - TLS_TP_OFFSET
public static final int R_RISCV_TLS_DTPREL64 = 9; // TLS relocation word64 = TLS + S + A - TLS_TP_OFFSET
public static final int R_RISCV_TLS_TPREL32 = 10; // TLS relocation word32 = TLS + S + A + S_TLS_OFFSET - TLS_DTV_OFFSET
public static final int R_RISCV_TLS_TPREL64 = 11; // TLS relocation word64 = TLS + S + A + S_TLS_OFFSET - TLS_DTV_OFFSET
public static final int R_RISCV_BRANCH = 16; // PC-relative branch (SB-Type)
public static final int R_RISCV_JAL = 17; // PC-relative jump (UJ-Type)
public static final int R_RISCV_CALL = 18; // PC-relative call MACRO call,tail (auipc+jalr pair)
public static final int R_RISCV_CALL_PLT = 19; // PC-relative call (PLT) MACRO call,tail (auipc+jalr pair) PIC
public static final int R_RISCV_GOT_HI20 = 20; // PC-relative GOT reference MACRO la
public static final int R_RISCV_TLS_GOT_HI20 = 21; // PC-relative TLS IE GOT offset MACRO la.tls.ie
public static final int R_RISCV_TLS_GD_HI20 = 22; // PC-relative TLS GD reference MACRO la.tls.gd
public static final int R_RISCV_PCREL_HI20 = 23; // PC-relative reference %pcrel_hi(symbol) (U-Type)
public static final int R_RISCV_PCREL_LO12_I = 24; // PC-relative reference %pcrel_lo(symbol) (I-Type)
public static final int R_RISCV_PCREL_LO12_S = 25; // PC-relative reference %pcrel_lo(symbol) (S-Type)
public static final int R_RISCV_HI20 = 26; // Absolute address %hi(symbol) (U-Type)
public static final int R_RISCV_LO12_I = 27; // Absolute address %lo(symbol) (I-Type)
public static final int R_RISCV_LO12_S = 28; // Absolute address %lo(symbol) (S-Type)
public static final int R_RISCV_TPREL_HI20 = 29; // TLS LE thread offset %tprel_hi(symbol) (U-Type)
public static final int R_RISCV_TPREL_LO12_I = 30; // TLS LE thread offset %tprel_lo(symbol) (I-Type)
public static final int R_RISCV_TPREL_LO12_S = 31; // TLS LE thread offset %tprel_lo(symbol) (S-Type)
public static final int R_RISCV_TPREL_ADD = 32; // TLS LE thread usage %tprel_add(symbol)
public static final int R_RISCV_ADD8 = 33; // 8-bit label addition word8 = old + S + A
public static final int R_RISCV_ADD16 = 34; // 16-bit label addition word16 = old + S + A
public static final int R_RISCV_ADD32 = 35; // 32-bit label addition word32 = old + S + A
public static final int R_RISCV_ADD64 = 36; // 64-bit label addition word64 = old + S + A
public static final int R_RISCV_SUB8 = 37; // 8-bit label subtraction word8 = old - S - A
public static final int R_RISCV_SUB16 = 38; // 16-bit label subtraction word16 = old - S - A
public static final int R_RISCV_SUB32 = 39; // 32-bit label subtraction word32 = old - S - A
public static final int R_RISCV_SUB64 = 40; // 64-bit label subtraction word64 = old - S - A
public static final int R_RISCV_GNU_VTINHERIT = 41; // GNU C++ vtable hierarchy
public static final int R_RISCV_GNU_VTENTRY = 42; // GNU C++ vtable member usage
public static final int R_RISCV_ALIGN = 43; // Alignment statement
public static final int R_RISCV_RVC_BRANCH = 44; // PC-relative branch offset (CB-Type)
public static final int R_RISCV_RVC_JUMP = 45; // PC-relative jump offset (CJ-Type)
public static final int R_RISCV_RVC_LUI = 46; // Absolute address (CI-Type)
public static final int R_RISCV_GPREL_I = 47; // GP-relative reference (I-Type)
public static final int R_RISCV_GPREL_S = 48; // GP-relative reference (S-Type)
public static final int R_RISCV_TPREL_I = 49; // TP-relative TLS LE load (I-Type)
public static final int R_RISCV_TPREL_S = 50; // TP-relative TLS LE store (S-Type)
public static final int R_RISCV_RELAX = 51; // Instruction pair can be relaxed
public static final int R_RISCV_SUB6 = 52; // Local label subtraction
public static final int R_RISCV_SET6 = 53; // Local label subtraction
public static final int R_RISCV_SET8 = 54; // Local label subtraction
public static final int R_RISCV_SET16 = 55; // Local label subtraction
public static final int R_RISCV_SET32 = 56; // Local label subtraction
public static final int R_RISCV_32_PCREL = 57; // 32-bit PC relative
// 58-191 Reserved Reserved for future standard use
// 192-255 Reserved Reserved for nonstandard ABI extensions
}

459
Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/relocation/RISCV_ElfRelocationHandler.java Normal file
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/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.app.util.bin.format.elf.relocation;
import ghidra.app.util.bin.format.elf.*;
import ghidra.program.model.address.Address;
import ghidra.program.model.listing.Program;
import ghidra.program.model.mem.Memory;
import ghidra.program.model.mem.MemoryAccessException;
import ghidra.util.exception.NotFoundException;
public class RISCV_ElfRelocationHandler extends ElfRelocationHandler {
@Override
public boolean canRelocate(ElfHeader elf) {
return elf.e_machine() == ElfConstants.EM_RISCV;
}
@Override
public void relocate(ElfRelocationContext elfRelocationContext, ElfRelocation relocation,
Address relocationAddress) throws MemoryAccessException, NotFoundException {
ElfHeader elf = elfRelocationContext.getElfHeader();
if (!canRelocate(elf)) {
return;
}
Program program = elfRelocationContext.getProgram();
Memory memory = program.getMemory();
boolean is32 = elf.is32Bit();
int type = relocation.getType();
if (RISCV_ElfRelocationConstants.R_RISCV_NONE == type) {
return;
}
long addend = relocation.hasAddend() ? relocation.getAddend() : is32 ? memory.getInt(relocationAddress) : memory.getLong(relocationAddress);
long offset = relocationAddress.getOffset();
long base = elfRelocationContext.getImageBaseWordAdjustmentOffset();
ElfSymbol sym = null;
long symbolValue = 0;
String symbolName = null;
int symbolIndex = relocation.getSymbolIndex();
if (symbolIndex != 0) {
sym = elfRelocationContext.getSymbol(symbolIndex);
}
if (null != sym) {
symbolValue = elfRelocationContext.getSymbolValue(sym);
symbolName = sym.getNameAsString();
}
//TODO remove debug
switch(type) {
case 2:
case 3:
case 5:
break;
default:
System.out.println("DEBUG RISCV: " +
type + " " + relocationAddress + " " +
String.format("%x", symbolValue) + " " +
String.format("%x", addend) + " " +
String.format("%x", offset) + " " +
String.format("%x", base));// + " " +
//String.format("%x", memory.getInt(relocationAddress)));
break;
}
long value64 = 0;
int value32 = 0;
short value16 = 0;
byte value8 = 0;
switch (type) {
case RISCV_ElfRelocationConstants.R_RISCV_32:
// Runtime relocation word32 = S + A
value32 = (int)(symbolValue + addend);
memory.setInt(relocationAddress, value32);
break;
case RISCV_ElfRelocationConstants.R_RISCV_64:
// Runtime relocation word64 = S + A
value64 = symbolValue + addend;
memory.setLong(relocationAddress, value64);
break;
case RISCV_ElfRelocationConstants.R_RISCV_RELATIVE:
// Runtime relocation word32,64 = B + A
if (is32) {
value32 = (int)(base + addend);
memory.setInt(relocationAddress, value32);
}
else {
value64 = base + addend;
memory.setLong(relocationAddress, value64);
}
break;
case RISCV_ElfRelocationConstants.R_RISCV_COPY:
// Runtime relocation must be in executable. not allowed in shared library
markAsWarning(program, relocationAddress, "R_RISCV_COPY", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_JUMP_SLOT:
// Runtime relocation word32,64 = S ;handled by PLT unless LD_BIND_NOW
if (is32) {
value32 = (int)(symbolValue);
memory.setInt(relocationAddress, value32);
}
else {
value64 = symbolValue;
memory.setLong(relocationAddress, value64);
}
break;
case RISCV_ElfRelocationConstants.R_RISCV_TLS_DTPMOD32:
// TLS relocation word32 = S->TLSINDEX
markAsWarning(program, relocationAddress, "R_RISCV_TLS_DTPMOD32", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_TLS_DTPMOD64:
// TLS relocation word64 = S->TLSINDEX
markAsWarning(program, relocationAddress, "R_RISCV_TLS_DTPMOD32", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_TLS_DTPREL32:
// TLS relocation word32 = TLS + S + A - TLS_TP_OFFSET
markAsWarning(program, relocationAddress, "R_RISCV_TLS_DTPREL32", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_TLS_DTPREL64:
// TLS relocation word64 = TLS + S + A - TLS_TP_OFFSET
markAsWarning(program, relocationAddress, "R_RISCV_TLS_DTPREL64", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_TLS_TPREL32:
// TLS relocation word32 = TLS + S + A + S_TLS_OFFSET - TLS_DTV_OFFSET
markAsWarning(program, relocationAddress, "R_RISCV_TLS_DTREL32", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_TLS_TPREL64:
// TLS relocation word64 = TLS + S + A + S_TLS_OFFSET - TLS_DTV_OFFSET
markAsWarning(program, relocationAddress, "R_RISCV_TLS_TPREL64", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_BRANCH:
// PC-relative branch (SB-Type)
markAsWarning(program, relocationAddress, "R_RISCV_BRANCH", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_JAL:
// PC-relative jump (UJ-Type)
markAsWarning(program, relocationAddress, "R_RISCV_JAL", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_CALL:
// PC-relative call MACRO call,tail (auipc+jalr pair)
markAsWarning(program, relocationAddress, "R_RISCV_CALL", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_CALL_PLT:
// PC-relative call (PLT) MACRO call,tail (auipc+jalr pair) PIC
markAsWarning(program, relocationAddress, "R_RISCV_CALL_PLT", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_GOT_HI20:
// PC-relative GOT reference MACRO la
markAsWarning(program, relocationAddress, "R_RISCV_GOT_HI20", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_TLS_GOT_HI20:
// PC-relative TLS IE GOT offset MACRO la.tls.ie
markAsWarning(program, relocationAddress, "R_RISCV_TLS_GOT_HI20", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_TLS_GD_HI20:
// PC-relative TLS GD reference MACRO la.tls.gd
markAsWarning(program, relocationAddress, "R_RISCV_TLS_GD_HI20", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_PCREL_HI20:
// PC-relative reference %pcrel_hi(symbol) (U-Type)
markAsWarning(program, relocationAddress, "R_RISCV_PCREL_HI20", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_PCREL_LO12_I:
// PC-relative reference %pcrel_lo(symbol) (I-Type)
markAsWarning(program, relocationAddress, "R_RISCV_PCREL_LO12_I", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_PCREL_LO12_S:
// PC-relative reference %pcrel_lo(symbol) (S-Type)
markAsWarning(program, relocationAddress, "R_RISCV_PCREL_LO12_S", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_HI20:
// Absolute address %hi(symbol) (U-Type)
markAsWarning(program, relocationAddress, "R_RISCV_HI20", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_LO12_I:
// Absolute address %lo(symbol) (I-Type)
markAsWarning(program, relocationAddress, "R_RISCV_LO12_I", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_LO12_S:
// Absolute address %lo(symbol) (S-Type)
markAsWarning(program, relocationAddress, "R_RISCV_LO12_S", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_TPREL_HI20:
// TLS LE thread offset %tprel_hi(symbol) (U-Type)
markAsWarning(program, relocationAddress, "R_RISCV_TPREL_HI20", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_TPREL_LO12_I:
// TLS LE thread offset %tprel_lo(symbol) (I-Type)
markAsWarning(program, relocationAddress, "R_RISCV_TPREL_LO12_I", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_TPREL_LO12_S:
// TLS LE thread offset %tprel_lo(symbol) (S-Type)
markAsWarning(program, relocationAddress, "R_RISCV_TPREL_LO12_S", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_TPREL_ADD:
// TLS LE thread usage %tprel_add(symbol)
markAsWarning(program, relocationAddress, "R_RISCV_TPREL_ADD", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_ADD8:
// 8-bit label addition word8 = old + S + A
markAsWarning(program, relocationAddress, "R_RISCV_ADD8", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
value8 = memory.getByte(relocationAddress);
value8 += (byte)symbolValue;
value8 += (byte)addend;
memory.setByte(relocationAddress, value8);
break;
case RISCV_ElfRelocationConstants.R_RISCV_ADD16:
// 16-bit label addition word16 = old + S + A
markAsWarning(program, relocationAddress, "R_RISCV_ADD16", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
value16 = memory.getShort(relocationAddress);
value16 += (short)symbolValue;
value16 += (short)addend;
memory.setShort(relocationAddress, value16);
break;
case RISCV_ElfRelocationConstants.R_RISCV_ADD32:
// 32-bit label addition word32 = old + S + A
markAsWarning(program, relocationAddress, "R_RISCV_ADD32", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
value32 = memory.getInt(relocationAddress);
value32 += (int)symbolValue;
value32 += (int)addend;
memory.setInt(relocationAddress, value32);
break;
case RISCV_ElfRelocationConstants.R_RISCV_ADD64:
// 64-bit label addition word64 = old + S + A
markAsWarning(program, relocationAddress, "R_RISCV_ADD64", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
value64 = memory.getLong(relocationAddress);
value64 += symbolValue;
value64 += addend;
memory.setLong(relocationAddress, value64);
break;
case RISCV_ElfRelocationConstants.R_RISCV_SUB8:
// 8-bit label subtraction word8 = old - S - A
markAsWarning(program, relocationAddress, "R_RISCV_SUB8", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
value8 = memory.getByte(relocationAddress);
value8 -= (byte)symbolValue;
value8 -= (byte)addend;
memory.setByte(relocationAddress, value8);
break;
case RISCV_ElfRelocationConstants.R_RISCV_SUB16:
// 16-bit label subtraction word16 = old - S - A
markAsWarning(program, relocationAddress, "R_RISCV_SUB16", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
value16 = memory.getShort(relocationAddress);
value16 -= (short)symbolValue;
value16 -= (short)addend;
memory.setShort(relocationAddress, value16);
break;
case RISCV_ElfRelocationConstants.R_RISCV_SUB32:
// 32-bit label subtraction word32 = old - S - A
markAsWarning(program, relocationAddress, "R_RISCV_SUB32", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
value32 = memory.getInt(relocationAddress);
value32 -= (int)symbolValue;
value32 -= (int)addend;
memory.setInt(relocationAddress, value32);
break;
case RISCV_ElfRelocationConstants.R_RISCV_SUB64:
// 64-bit label subtraction word64 = old - S - A
markAsWarning(program, relocationAddress, "R_RISCV_SUB64", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
value64 = memory.getLong(relocationAddress);
value64 -= symbolValue;
value64 -= addend;
memory.setLong(relocationAddress, value64);
break;
case RISCV_ElfRelocationConstants.R_RISCV_GNU_VTINHERIT:
// GNU C++ vtable hierarchy
markAsWarning(program, relocationAddress, "R_RISCV_GNU_VTINHERIT", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_GNU_VTENTRY:
// GNU C++ vtable member usage
markAsWarning(program, relocationAddress, "R_RISCV_GNU_VTENTRY", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_ALIGN:
// Alignment statement
markAsWarning(program, relocationAddress, "R_RISCV_ALIGN", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_RVC_BRANCH:
// PC-relative branch offset (CB-Type)
markAsWarning(program, relocationAddress, "R_RISCV_RVC_BRANCH", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_RVC_JUMP:
// PC-relative jump offset (CJ-Type)
markAsWarning(program, relocationAddress, "R_RISCV_RVC_BRANCH", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_RVC_LUI:
// Absolute address (CI-Type)
markAsWarning(program, relocationAddress, "R_RISCV_RVC_LUI", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_GPREL_I:
// GP-relative reference (I-Type)
markAsWarning(program, relocationAddress, "R_RISCV_GPREL_I", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_GPREL_S:
// GP-relative reference (S-Type)
markAsWarning(program, relocationAddress, "R_RISCV_GPREL_S", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_TPREL_I:
// TP-relative TLS LE load (I-Type)
markAsWarning(program, relocationAddress, "R_RISCV_TPREL_I", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_TPREL_S:
// TP-relative TLS LE store (S-Type)
markAsWarning(program, relocationAddress, "R_RISCV_TPREL_S", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_RELAX:
// Instruction pair can be relaxed
markAsWarning(program, relocationAddress, "R_RISCV_RELAX", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_SUB6:
// Local label subtraction
markAsWarning(program, relocationAddress, "R_RISCV_SUB6", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_SET6:
// Local label subtraction
markAsWarning(program, relocationAddress, "R_RISCV_SET6", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_SET8:
// Local label subtraction
markAsWarning(program, relocationAddress, "R_RISCV_SET8", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_SET16:
// Local label subtraction
markAsWarning(program, relocationAddress, "R_RISCV_SET16", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_SET32:
// Local label subtraction
markAsWarning(program, relocationAddress, "R_RISCV_SET32", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
case RISCV_ElfRelocationConstants.R_RISCV_32_PCREL:
// 32-bit PC relative
markAsWarning(program, relocationAddress, "R_RISCV_32_PCREL", symbolName, symbolIndex,
"TODO, needs support ", elfRelocationContext.getLog());
break;
default:
// 58-191 Reserved Reserved for future standard use
// 192-255 Reserved Reserved for nonstandard ABI extensions
markAsUnhandled(program, relocationAddress, type, symbolIndex, symbolName, elfRelocationContext.getLog());
break;
}
}
}

61
Ghidra/Processors/RISCV/src/main/java/ghidra/program/emulation/RISCVEmulateInstructionStateModifier.java Normal file
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/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.program.emulation;
import ghidra.pcode.emulate.EmulateInstructionStateModifier;
import ghidra.pcode.error.LowlevelError;
import ghidra.program.model.address.Address;
import ghidra.program.model.lang.RegisterValue;
import ghidra.program.model.pcode.PcodeOp;
import ghidra.pcode.emulate.Emulate;
public class RISCVEmulateInstructionStateModifier extends EmulateInstructionStateModifier {
public RISCVEmulateInstructionStateModifier(Emulate emu) {
super(emu);
}
/**
* Emulation callback immediately before the first instruction is executed.
* This callback permits any language specific initializations to be performed.
* @param emulate
* @param current_address intial execute address
* @param contextRegisterValue initial context value or null if not applicable or unknown
* @throws LowlevelError
*/
@Override
public void initialExecuteCallback(Emulate emulate, Address current_address, RegisterValue contextRegisterValue) throws LowlevelError {
// no default implementation
}
/**
* Emulation callback immediately following execution of the lastExecuteAddress.
* One use of this callback is to modify the flowing/future context state.
* @param emulate
* @param lastExecuteAddress
* @param lastExecutePcode
* @param lastPcodeIndex pcode index of last op or -1 if no pcode or fall-through occurred.
* @param currentAddress
* @throws LowlevelError
*/
@Override
public void postExecuteCallback(Emulate emulate, Address lastExecuteAddress,
PcodeOp[] lastExecutePcode, int lastPcodeIndex, Address currentAddress)
throws LowlevelError {
// no default implementation
}
}

40
Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32GC_O0_EmulatorTest.java Normal file
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/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.test.processors;
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
import junit.framework.Test;
public class RV32GC_O0_EmulatorTest extends ProcessorEmulatorTestAdapter {
private static final String LANGUAGE_ID = "RISCV:LE:32:RV32GC";
private static final String COMPILER_SPEC_ID = "gcc";
private static final String[] REG_DUMP_SET = new String[] {};
public RV32GC_O0_EmulatorTest(String name) throws Exception {
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
}
@Override
protected String getProcessorDesignator() {
return "RV32GC_GCC_O0";
}
public static Test suite() {
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV32GC_O0_EmulatorTest.class);
}
}

40
Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32GC_O3_EmulatorTest.java Normal file
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/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.test.processors;
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
import junit.framework.Test;
public class RV32GC_O3_EmulatorTest extends ProcessorEmulatorTestAdapter {
private static final String LANGUAGE_ID = "RISCV:LE:32:RV32GC";
private static final String COMPILER_SPEC_ID = "gcc";
private static final String[] REG_DUMP_SET = new String[] {};
public RV32GC_O3_EmulatorTest(String name) throws Exception {
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
}
@Override
protected String getProcessorDesignator() {
return "RV32GC_GCC_O3";
}
public static Test suite() {
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV32GC_O3_EmulatorTest.class);
}
}

39
Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32IMC_O0_EmulatorTest.java Normal file
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/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.test.processors;
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
import junit.framework.Test;
public class RV32IMC_O0_EmulatorTest extends ProcessorEmulatorTestAdapter {
private static final String LANGUAGE_ID = "RISCV:LE:32:RV32IMC";
private static final String COMPILER_SPEC_ID = "gcc";
private static final String[] REG_DUMP_SET = new String[] {};
public RV32IMC_O0_EmulatorTest(String name) throws Exception {
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
}
@Override
protected String getProcessorDesignator() {
return "RV32IMC_GCC_O0";
}
public static Test suite() {
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV32IMC_O0_EmulatorTest.class);
}
}

40
Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64GC_O0_EmulatorTest.java Normal file
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@ -0,0 +1,40 @@
/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.test.processors;
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
import junit.framework.Test;
public class RV64GC_O0_EmulatorTest extends ProcessorEmulatorTestAdapter {
private static final String LANGUAGE_ID = "RISCV:LE:64:RV64GC";
private static final String COMPILER_SPEC_ID = "gcc";
private static final String[] REG_DUMP_SET = new String[] {};
public RV64GC_O0_EmulatorTest(String name) throws Exception {
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
}
@Override
protected String getProcessorDesignator() {
return "RV64GC_GCC_O0";
}
public static Test suite() {
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV64GC_O0_EmulatorTest.class);
}
}

40
Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64GC_O3_EmulatorTest.java Normal file
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@ -0,0 +1,40 @@
/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.test.processors;
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
import junit.framework.Test;
public class RV64GC_O3_EmulatorTest extends ProcessorEmulatorTestAdapter {
private static final String LANGUAGE_ID = "RISCV:LE:64:RV64GC";
private static final String COMPILER_SPEC_ID = "gcc";
private static final String[] REG_DUMP_SET = new String[] {};
public RV64GC_O3_EmulatorTest(String name) throws Exception {
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
}
@Override
protected String getProcessorDesignator() {
return "RV64GC_GCC_O3";
}
public static Test suite() {
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV64GC_O3_EmulatorTest.class);
}
}

40
Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64G_O0_EmulatorTest.java Normal file
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@ -0,0 +1,40 @@
/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.test.processors;
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
import junit.framework.Test;
public class RV64G_O0_EmulatorTest extends ProcessorEmulatorTestAdapter {
private static final String LANGUAGE_ID = "RISCV:LE:64:RV64G";
private static final String COMPILER_SPEC_ID = "gcc";
private static final String[] REG_DUMP_SET = new String[] {};
public RV64G_O0_EmulatorTest(String name) throws Exception {
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
}
@Override
protected String getProcessorDesignator() {
return "RV64G_GCC_O0";
}
public static Test suite() {
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV64G_O0_EmulatorTest.class);
}
}

40
Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64G_O3_EmulatorTest.java Normal file
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/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.test.processors;
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
import junit.framework.Test;
public class RV64G_O3_EmulatorTest extends ProcessorEmulatorTestAdapter {
private static final String LANGUAGE_ID = "RISCV:LE:64:RV64G";
private static final String COMPILER_SPEC_ID = "gcc";
private static final String[] REG_DUMP_SET = new String[] {};
public RV64G_O3_EmulatorTest(String name) throws Exception {
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
}
@Override
protected String getProcessorDesignator() {
return "RV64G_GCC_O3";
}
public static Test suite() {
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV64G_O3_EmulatorTest.class);
}
}