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Merge remote-tracking branch
'origin/GP-3524_ghidorahrex_arm_thumb_vdup_fix' into patch (Closes #5420)
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commit
d5559a477c
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@ -475,7 +475,7 @@ define token instrArm (32)
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thv_Rt=(12,15)
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thv_Rn=(16,19)
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thv_Rm=(0,3)
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thv_Rt2=(8,11)
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thv_Rt2=(8,11)
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thv_immed=(0,7)
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# Arbitrary bit fields for 32-bit Big Endian Thumb
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@ -2507,24 +2507,24 @@ vdupSize2: 8 is c2222=1 & c0505=0 { }
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vdupSize2: 16 is c2222=0 & c0505=1 { }
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vdupSize2: 32 is c2222=0 & c0505=0 { }
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vdupRd8: Rd is Rd & c2222=1 & c0505=0
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vdupRd8: VRd is VRd & c2222=1 & c0505=0
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{
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val:8 = 0;
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local tmpRd = Rd;
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local tmpRd = VRd;
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replicate1to8(tmpRd:1, val);
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export val;
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}
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vdupRd8: Rd is Rd & c2222=0 & c0505=1
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vdupRd8: VRd is VRd & c2222=0 & c0505=1
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{
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val:8 = 0;
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local tmpRd = Rd;
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local tmpRd = VRd;
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replicate2to8(tmpRd:2, val);
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export val;
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}
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vdupRd8: Rd is Rd & c2222=0 & c0505=0
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vdupRd8: VRd is VRd & c2222=0 & c0505=0
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{
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val:8 = 0;
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local tmpRd = Rd;
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local tmpRd = VRd;
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replicate4to8(tmpRd:4, val);
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export val;
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}
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@ -2536,8 +2536,8 @@ vdupRd16: vdupRd8 is vdupRd8
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export val;
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}
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:vdup^COND^"."^vdupSize2 Dn,vdupRd8 is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=11 & c0606=0 & c0004=0x10) |
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($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & COND & Dn & vdupSize2 & vdupRd8
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:vdup^COND^"."^vdupSize2 Dn,VRd is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=11 & c0606=0 & c0004=0x10) |
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($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & VRd & COND & Dn & vdupSize2 & vdupRd8
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{
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build COND;
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build vdupRd8;
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@ -2545,8 +2545,8 @@ vdupRd16: vdupRd8 is vdupRd8
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Dn = vdupRd8;
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}
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:vdup^COND^"."^vdupSize2 Qn,vdupRd16 is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=2 & c0811=11 & c0606=0 & c0004=0x10) |
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($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & COND & Qn & vdupSize2 & vdupRd16
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:vdup^COND^"."^vdupSize2 Qn,VRd is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=2 & c0811=11 & c0606=0 & c0004=0x10) |
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($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & VRd & COND & Qn & vdupSize2 & vdupRd16
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{
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build COND;
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build vdupRd16;
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