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Merge remote-tracking branch 'origin/patch'

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This commit is contained in:
Ryan Kurtz 2023-05-18 11:06:01 -04:00
commit a87044c521
7 changed files with 30 additions and 43 deletions
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15
Ghidra/Features/Base/src/main/java/ghidra/app/util/exporter/OriginalFileExporter.java
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@ -178,6 +178,10 @@ public class OriginalFileExporter extends Exporter {
Iterable<Relocation> relocs = () -> program.getRelocationTable().getRelocations();
Memory memory = program.getMemory();
for (Relocation reloc : relocs) {
if (reloc.getStatus() != Relocation.Status.APPLIED &&
reloc.getStatus() != Relocation.Status.APPLIED_OTHER) {
continue;
}
Address addr = reloc.getAddress();
AddressSourceInfo addrSourceInfo = memory.getAddressSourceInfo(addr);
if (addrSourceInfo == null) {
@ -187,10 +191,12 @@ public class OriginalFileExporter extends Exporter {
if (offset >= 0) {
MemoryBlockSourceInfo memSourceInfo = addrSourceInfo.getMemoryBlockSourceInfo();
byte[] bytes = reloc.getBytes();
int len = Math.min(bytes.length,
(int) memSourceInfo.getMaxAddress().subtract(addr) + 1);
fout.seek(offset);
fout.write(bytes, 0, len);
if (bytes != null) {
int len = Math.min(bytes.length,
(int) memSourceInfo.getMaxAddress().subtract(addr) + 1);
fout.seek(offset);
fout.write(bytes, 0, len);
}
}
}
}
@ -198,6 +204,7 @@ public class OriginalFileExporter extends Exporter {
if (!tempFile.delete()) {
log.appendMsg("Failed to delete malformed file: " + tempFile);
}
log.appendException(e);
return false;
}

8
Ghidra/Processors/PowerPC/data/languages/ppc_a2.sinc
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@ -85,14 +85,6 @@ define pcodeop wclrallOp;
define pcodeop wclrOp;
# :wclr L,A,B is $(NOTVLE) & OP=31 & XOP_1_10=934 & L & A & B { wclrOp(); }
@ifdef IS_ISA
# binutils: 476.d 474: 7c 00 06 ac mbar
# binutils: 476.d 47c: 7c 20 06 ac mbar 1
# "mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {MO}
define pcodeop mbarOp;
:mbar MO is OP=31 & XOP_1_10=854 & MO { mbarOp(); }
@endif
# binutils: a2.d: 514: 7d 4a 3a 87 mfdcr\. r10,234
:mfdcr. D, DCRN is $(NOTVLE) & OP=31 & D & DCRN & XOP_1_10=323 & BIT_0=1
{

10
Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc
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@ -49,14 +49,12 @@
dataCacheBlockClearToZero(ea);
}
@ifndef IS_ISA
# this is equilent to "mbar 0"
#eieio 0x7c 00 06 ac
:eieio is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=854 & BIT_0=0
define pcodeop memoryBarrier;
#mbar 0 7c 00 06 ac
:mbar MO is OP=31 & MO & XOP_1_10=854
{
enforceInOrderExecutionIO();
memoryBarrier(MO:1);
}
@endif
#icbi r0,r0 0x7c 00 07 ac
:icbi RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=982 & BIT_0=0 & RA_OR_ZERO

7
Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc
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@ -1087,6 +1087,13 @@
externalControlOut(ea, S);
}
#===========================================================
# EIEIO
#===========================================================
# binutils-descr: "eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}
# binutils: mytest.d: 20: 7c 00 06 ac eieio
:eieio is OP=31 & XOP_1_10=854 & BITS_11_25=0 & BIT_0=0 { enforceInOrderExecutionIO(); }
#===========================================================
# EQVx
#===========================================================

8
Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
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@ -1625,14 +1625,6 @@ define pcodeop lbzcixOp;
RT = *:1 A;
}
# binutils-descr: "eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}
define pcodeop eieioOp;
# ISA-cmt: eieio - Enforce In-order Execution of I/O
# ISA-info: eieio - Form "X" Page 698 Category "S"
# binutils: mytest.d: 20: 7c 00 06 ac eieio
:eieio is $(NOTVLE) & OP=31 & XOP_1_10=854 & BITS_11_25=0 & BIT_0=0 { eieioOp(); }
# binutils-descr: "ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}
# ISA-cmt: ldcix - Load Doubleword Caching Inhibited Indexed
# ISA-info: ldcix - Form "X" Page 749 Category "S"

16
Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
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@ -400,14 +400,14 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
#TODO SEE TODO in e_ldmvsprw
# storeReg(CR);
local tmpCR:4 = 0;
tmpCR = tmpCR | zext((cr0 & 0xf) << 0);
tmpCR = tmpCR | zext((cr1 & 0xf) << 4);
tmpCR = tmpCR | zext((cr2 & 0xf) << 8);
tmpCR = tmpCR | zext((cr3 & 0xf) << 12);
tmpCR = tmpCR | zext((cr4 & 0xf) << 16);
tmpCR = tmpCR | zext((cr5 & 0xf) << 20);
tmpCR = tmpCR | zext((cr6 & 0xf) << 24);
tmpCR = tmpCR | zext((cr7 & 0xf) << 28);
tmpCR = tmpCR | (zext(cr0 & 0xf) << 0);
tmpCR = tmpCR | (zext(cr1 & 0xf) << 4);
tmpCR = tmpCR | (zext(cr2 & 0xf) << 8);
tmpCR = tmpCR | (zext(cr3 & 0xf) << 12);
tmpCR = tmpCR | (zext(cr4 & 0xf) << 16);
tmpCR = tmpCR | (zext(cr5 & 0xf) << 20);
tmpCR = tmpCR | (zext(cr6 & 0xf) << 24);
tmpCR = tmpCR | (zext(cr7 & 0xf) << 28);
*:4 tea = tmpCR;
tea = tea + 4;
storeReg(LR);

9
Ghidra/Processors/PowerPC/data/languages/quicciii.sinc
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@ -8,7 +8,6 @@ define pcodeop debuggerNotifyHalt;
define pcodeop instructionCacheBlockClearLock;
define pcodeop queryInstructionCacheBlockLock;
define pcodeop prefetchInstructionCacheBlockLockSetX;
define pcodeop memoryBarrier;
define pcodeop moveFromAPIDIndirect;
define pcodeop moveFromPerformanceMonitorRegister;
define pcodeop moveToPerformanceMonitorRegister;
@ -70,14 +69,6 @@ define pcodeop invalidateTLB;
# D = (zext(CC_X_OP) * RA_OR_ZERO) + (zext(!CC_X_OP) * B);
}
@ifndef IS_ISA
#mbar 0 #FIXME
:mbar MO is OP=31 & MO & XOP_1_10=854
{
memoryBarrier(MO:1);
}
@endif
#mfapidi r0,r1 #FIXME
:mfapidi D,A is $(NOTVLE) & OP=31 & D & A & XOP_1_10=275
{