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move around mbar/eieio

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This commit is contained in:
William Tan 2023-05-05 11:12:29 -04:00
parent eebdca2668
commit 9c694ebfd1
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4 changed files with 13 additions and 24 deletions
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13
Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc
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@ -49,13 +49,12 @@
dataCacheBlockClearToZero(ea);
}
@ifdef IS_ISA
# binutils: 476.d 474: 7c 00 06 ac mbar
# binutils: 476.d 47c: 7c 20 06 ac mbar 1
# "mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {MO}
define pcodeop mbarOp;
:mbar MO is OP=31 & XOP_1_10=854 & MO { mbarOp(); }
@endif
define pcodeop memoryBarrier;
#mbar 0 7c 00 06 ac
:mbar MO is OP=31 & MO & XOP_1_10=854
{
memoryBarrier(MO:1);
}
#icbi r0,r0 0x7c 00 07 ac
:icbi RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=982 & BIT_0=0 & RA_OR_ZERO

7
Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc
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@ -1087,6 +1087,13 @@
externalControlOut(ea, S);
}
#===========================================================
# EIEIO
#===========================================================
# binutils-descr: "eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}
# binutils: mytest.d: 20: 7c 00 06 ac eieio
:eieio is OP=31 & XOP_1_10=854 & BITS_11_25=0 & BIT_0=0 { enforceInOrderExecutionIO(); }
#===========================================================
# EQVx
#===========================================================

8
Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
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@ -1625,14 +1625,6 @@ define pcodeop lbzcixOp;
RT = *:1 A;
}
# binutils-descr: "eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}
define pcodeop eieioOp;
# ISA-cmt: eieio - Enforce In-order Execution of I/O
# ISA-info: eieio - Form "X" Page 698 Category "S"
# binutils: mytest.d: 20: 7c 00 06 ac eieio
:eieio is $(NOTVLE) & OP=31 & XOP_1_10=854 & BITS_11_25=0 & BIT_0=0 { eieioOp(); }
# binutils-descr: "ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}
# ISA-cmt: ldcix - Load Doubleword Caching Inhibited Indexed
# ISA-info: ldcix - Form "X" Page 749 Category "S"

9
Ghidra/Processors/PowerPC/data/languages/quicciii.sinc
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@ -8,7 +8,6 @@ define pcodeop debuggerNotifyHalt;
define pcodeop instructionCacheBlockClearLock;
define pcodeop queryInstructionCacheBlockLock;
define pcodeop prefetchInstructionCacheBlockLockSetX;
define pcodeop memoryBarrier;
define pcodeop moveFromAPIDIndirect;
define pcodeop moveFromPerformanceMonitorRegister;
define pcodeop moveToPerformanceMonitorRegister;
@ -70,14 +69,6 @@ define pcodeop invalidateTLB;
# D = (zext(CC_X_OP) * RA_OR_ZERO) + (zext(!CC_X_OP) * B);
}
@ifndef IS_ISA
#mbar 0 #FIXME
:mbar MO is OP=31 & MO & XOP_1_10=854
{
memoryBarrier(MO:1);
}
@endif
#mfapidi r0,r1 #FIXME
:mfapidi D,A is $(NOTVLE) & OP=31 & D & A & XOP_1_10=275
{