From 8cf5b0f2c63bb329ce899e6e60962de90efccebd Mon Sep 17 00:00:00 2001 From: emteere <47253321+emteere@users.noreply.github.com> Date: Tue, 2 Apr 2019 10:45:18 -0400 Subject: [PATCH] GT-2722 updates for CMP.W and LSL instruction decodes --- .../Processors/ARM/data/languages/ARM.ldefs | 34 +++++++++---------- .../data/languages/ARMTHUMBinstructions.sinc | 9 ++--- 2 files changed, 22 insertions(+), 21 deletions(-) diff --git a/Ghidra/Processors/ARM/data/languages/ARM.ldefs b/Ghidra/Processors/ARM/data/languages/ARM.ldefs index f98077ed69..08971e3ddf 100644 --- a/Ghidra/Processors/ARM/data/languages/ARM.ldefs +++ b/Ghidra/Processors/ARM/data/languages/ARM.ldefs @@ -5,7 +5,7 @@ endian="little" size="32" variant="v8" - version="1.101" + version="1.102" slafile="ARM8_le.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -22,7 +22,7 @@ instructionEndian="little" size="32" variant="v8LEInstruction" - version="1.101" + version="1.102" slafile="ARM8_le.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -37,7 +37,7 @@ endian="big" size="32" variant="v8" - version="1.101" + version="1.102" slafile="ARM8_be.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -53,7 +53,7 @@ endian="little" size="32" variant="v7" - version="1.101" + version="1.102" slafile="ARM7_le.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -71,7 +71,7 @@ instructionEndian="little" size="32" variant="v7LEInstruction" - version="1.101" + version="1.102" slafile="ARM7_le.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -86,7 +86,7 @@ endian="big" size="32" variant="v7" - version="1.101" + version="1.102" slafile="ARM7_be.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -102,7 +102,7 @@ endian="little" size="32" variant="Cortex" - version="1.101" + version="1.102" slafile="ARM7_le.sla" processorspec="ARMCortex.pspec" manualindexfile="../manuals/ARM.idx" @@ -117,7 +117,7 @@ endian="big" size="32" variant="Cortex" - version="1.101" + version="1.102" slafile="ARM7_be.sla" processorspec="ARMCortex.pspec" manualindexfile="../manuals/ARM.idx" @@ -132,7 +132,7 @@ endian="little" size="32" variant="v6" - version="1.101" + version="1.102" slafile="ARM6_le.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -150,7 +150,7 @@ endian="big" size="32" variant="v6" - version="1.101" + version="1.102" slafile="ARM6_be.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -168,7 +168,7 @@ endian="little" size="32" variant="v5t" - version="1.101" + version="1.102" slafile="ARM5t_le.sla" processorspec="ARMt_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -184,7 +184,7 @@ endian="big" size="32" variant="v5t" - version="1.101" + version="1.102" slafile="ARM5t_be.sla" processorspec="ARMt_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -200,7 +200,7 @@ endian="little" size="32" variant="v5" - version="1.101" + version="1.102" slafile="ARM5_le.sla" processorspec="ARM_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -232,7 +232,7 @@ endian="little" size="32" variant="v4t" - version="1.101" + version="1.102" slafile="ARM4t_le.sla" processorspec="ARMt_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -248,7 +248,7 @@ endian="big" size="32" variant="v4t" - version="1.101" + version="1.102" slafile="ARM4t_be.sla" processorspec="ARMt_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -264,7 +264,7 @@ endian="little" size="32" variant="v4" - version="1.101" + version="1.102" slafile="ARM4_le.sla" processorspec="ARM_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -280,7 +280,7 @@ endian="big" size="32" variant="v4" - version="1.101" + version="1.102" slafile="ARM4_be.sla" processorspec="ARM_v45.pspec" manualindexfile="../manuals/ARM.idx" diff --git a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc index a9c655d332..48a2d6a29f 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc @@ -185,6 +185,7 @@ define token instrThumb (16) thc0815=(8,15) thc0915=(9,15) thc1015=(10,15) + thc1112=(11,12) thc1115=(11,15) thc1215=(12,15) thc1315=(13,15) @@ -1614,7 +1615,7 @@ define pcodeop IndexCheck; @if defined(VERSION_6T2) || defined(VERSION_7) -:cmp^ItCond^".w" Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=13 & Rn0003; thc1515=0 & thc0811=15) & ThumbExpandImm12 +:cmp^ItCond^".w" Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & thc0404=1 & sop0508=13 & Rn0003; thc1515=0 & thc0811=15) & ThumbExpandImm12 { build ItCond; th_subflags(Rn0003,ThumbExpandImm12); @@ -2447,9 +2448,9 @@ define pcodeop ExclusiveAccess; build CheckInIT_ZN; } -:mov^ItCond Rd0002,Rn0305 is TMode=1 & ItCond & op6=0x070 & Rn0305 & Rd0002 & CheckInIT_ZN +:mov^ItCond Rd0002,Rn0305 is TMode=1 & ItCond & op6=0x000 & Rn0305 & Rd0002 & CheckInIT_ZN { - build ItCond; + build ItCond; Rd0002 = Rn0305; resflags(Rd0002); build CheckInIT_ZN; @@ -4482,7 +4483,7 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :sub^ItCond sp,Immed7_4 is TMode=1 & ItCond & op7=0x161 & sp & Immed7_4 { build ItCond; - sp = sp - Immed7_4; + sp = sp - Immed7_4; } @if defined(VERSION_6T2) || defined(VERSION_7)