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AArch32: (Thumb32) fixed ldrsh.w & ldrsb.w (pc-relative)
* double memory load bug
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@ -2396,7 +2396,7 @@ define pcodeop ExclusiveAccess;
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:ldrsb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12
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:ldrsb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12
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{
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{
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build ItCond;
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build ItCond;
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tmp:1 = *PcrelOffset12;
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tmp:1 = PcrelOffset12:1;
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Rt1215 = sext(tmp);
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Rt1215 = sext(tmp);
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}
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}
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@ -2437,7 +2437,7 @@ define pcodeop ExclusiveAccess;
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{
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{
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build ItCond;
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build ItCond;
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build PcrelOffset12;
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build PcrelOffset12;
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tmp:2 = *PcrelOffset12;
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tmp:2 = PcrelOffset12:2;
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Rt1215 = sext(tmp);
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Rt1215 = sext(tmp);
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}
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}
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