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AArch32: (Thumb32) fixed ldrsh.w & ldrsb.w (pc-relative)

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* double memory load bug
This commit is contained in:
Sleigh-InSPECtor 2024-05-23 13:46:50 +09:30
parent cae9190c13
commit 8a43da3fa1
1 changed files with 2 additions and 2 deletions
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4
Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
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@ -2396,7 +2396,7 @@ define pcodeop ExclusiveAccess;
:ldrsb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
tmp:1 = *PcrelOffset12;
tmp:1 = PcrelOffset12:1;
Rt1215 = sext(tmp);
}
@ -2437,7 +2437,7 @@ define pcodeop ExclusiveAccess;
{
build ItCond;
build PcrelOffset12;
tmp:2 = *PcrelOffset12;
tmp:2 = PcrelOffset12:2;
Rt1215 = sext(tmp);
}