mirror of
https://github.com/NationalSecurityAgency/ghidra.git
synced 2025-02-16 07:30:16 +00:00
Moved SuperH4 processor for release.
This commit is contained in:
ghidorahrex
parent
70b5c0478c
commit
864235ee7d
0
Ghidra/Processors/SuperH4/Module.manifest
Normal file
0
Ghidra/Processors/SuperH4/Module.manifest
Normal file
11
Ghidra/Processors/SuperH4/build.gradle
Normal file
11
Ghidra/Processors/SuperH4/build.gradle
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@ -0,0 +1,11 @@
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apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle"
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apply from: "$rootProject.projectDir/gradle/javaProject.gradle"
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apply from: "$rootProject.projectDir/gradle/jacocoProject.gradle"
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apply from: "$rootProject.projectDir/gradle/javaTestProject.gradle"
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apply from: "$rootProject.projectDir/gradle/processorProject.gradle"
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apply plugin: 'eclipse'
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eclipse.project.name = 'Processors SuperH4'
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dependencies {
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compile project(':Base')
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}
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19
Ghidra/Processors/SuperH4/certification.manifest
Normal file
19
Ghidra/Processors/SuperH4/certification.manifest
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@ -0,0 +1,19 @@
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##VERSION: 2.0
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.project||GHIDRA||||END|
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Module.manifest||GHIDRA||||END|
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build.gradle||GHIDRA||||END|
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data/build.xml||GHIDRA||||END|
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data/languages/SuperH4.cspec||GHIDRA||||END|
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data/languages/SuperH4.ldefs||GHIDRA||||END|
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data/languages/SuperH4.opinion||GHIDRA||||END|
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data/languages/SuperH4.pspec||GHIDRA||||END|
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data/languages/SuperH4.sinc||GHIDRA||||END|
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data/languages/SuperH4_be.slaspec||GHIDRA||||END|
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data/languages/SuperH4_le.slaspec||GHIDRA||||END|
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data/languages/old/SuperH4-BE-16.lang||GHIDRA||||END|
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data/languages/old/SuperH4-BE-16.trans||GHIDRA||||END|
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data/languages/old/SuperH4-LE-16.lang||GHIDRA||||END|
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data/languages/old/SuperH4-LE-16.trans||GHIDRA||||END|
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data/manuals/superh4.idx||GHIDRA||||END|
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data/patterns/SuperH4_patterns.xml||GHIDRA||||END|
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data/patterns/patternconstraints.xml||GHIDRA||||END|
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212
Ghidra/Processors/SuperH4/data/languages/SuperH4.cspec
Normal file
212
Ghidra/Processors/SuperH4/data/languages/SuperH4.cspec
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@ -0,0 +1,212 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<compiler_spec>
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<data_organization>
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<absolute_max_alignment value="0" />
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<machine_alignment value="2" />
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<default_alignment value="1" />
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<default_pointer_alignment value="4" />
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<pointer_size value="4" />
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<wchar_size value="4" />
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<short_size value="2" />
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<integer_size value="4" />
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<long_size value="4" />
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<float_size value="4" />
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<double_size value="8" />
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<size_alignment_map>
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<entry size="1" alignment="1" />
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<entry size="2" alignment="2" />
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<entry size="4" alignment="4" />
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<entry size="8" alignment="4" />
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</size_alignment_map>
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</data_organization>
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<global>
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<range space="ram"/>
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</global>
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<stackpointer register="r15" space="ram" growth="negative"/>
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<default_proto>
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<prototype name="__stdcall" extrapop="0" stackshift="0" strategy="register">
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<input>
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<pentry minsize="1" maxsize="4">
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<register name="r4"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="r5"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="r6"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="r7"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="fr4"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="fr5"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="fr6"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="fr7"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="dr4"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="dr6"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="dr8"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="dr10"/>
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</pentry>
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<pentry minsize="1" maxsize="500" align="4">
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<addr offset="0" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="4">
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<register name="r0"/>
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</pentry>
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</output>
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<unaffected>
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<register name="r15"/>
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<register name="r14"/>
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<register name="r13"/>
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<register name="r12"/>
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<register name="r11"/>
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<register name="r10"/>
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<register name="r9"/>
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<register name="r8"/>
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</unaffected>
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<killedbycall>
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<register name="r0"/>
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</killedbycall>
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</prototype>
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</default_proto>
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<prototype name="__floatret" extrapop="0" stackshift="0" strategy="register">
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<input>
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<pentry minsize="1" maxsize="4">
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<register name="r4"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="r5"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="r6"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="r7"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="fr4"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="fr5"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="fr6"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="fr7"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="dr4"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="dr6"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="dr8"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="dr10"/>
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</pentry>
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<pentry minsize="1" maxsize="500" align="4">
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<addr offset="0" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="4">
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<register name="fr0"/>
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</pentry>
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</output>
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<unaffected>
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<register name="r15"/>
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<register name="r14"/>
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<register name="r13"/>
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<register name="r12"/>
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<register name="r11"/>
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<register name="r10"/>
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<register name="r9"/>
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<register name="r8"/>
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</unaffected>
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<killedbycall>
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<register name="fr0"/>
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</killedbycall>
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</prototype>
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<prototype name="__doubleret" extrapop="0" stackshift="0" strategy="register">
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<input>
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<pentry minsize="1" maxsize="4">
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<register name="r4"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="r5"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="r6"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="r7"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="fr4"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="fr5"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="fr6"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="fr7"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="dr4"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="dr6"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="dr8"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="dr10"/>
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</pentry>
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<pentry minsize="1" maxsize="500" align="4">
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<addr offset="0" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="4">
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<register name="dr0"/>
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</pentry>
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</output>
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<unaffected>
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<register name="r15"/>
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<register name="r14"/>
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<register name="r13"/>
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<register name="r12"/>
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<register name="r11"/>
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<register name="r10"/>
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<register name="r9"/>
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<register name="r8"/>
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</unaffected>
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<killedbycall>
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<register name="dr0"/>
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</killedbycall>
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</prototype>
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</compiler_spec>
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31
Ghidra/Processors/SuperH4/data/languages/SuperH4.ldefs
Normal file
31
Ghidra/Processors/SuperH4/data/languages/SuperH4.ldefs
Normal file
@ -0,0 +1,31 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<language_definitions>
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<language processor="SuperH4"
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endian="big"
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size="32"
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variant="default"
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version="1.01"
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slafile="SuperH4_be.sla"
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processorspec="SuperH4.pspec"
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manualindexfile="../manuals/superh4.idx"
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id="SuperH4:BE:32:default">
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<description>SuperH-4(a) (SH4) big endian</description>
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<compiler name="default" spec="SuperH4.cspec" id="default"/>
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<external_name tool="IDA-PRO" name="sh4b"/>
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</language>
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<language processor="SuperH4"
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endian="little"
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size="32"
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variant="default"
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version="1.01"
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slafile="SuperH4_le.sla"
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processorspec="SuperH4.pspec"
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manualindexfile="../manuals/superh4.idx"
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id="SuperH4:LE:32:default">
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<description>SuperH-4(a) (SH4) little endian</description>
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<compiler name="default" spec="SuperH4.cspec" id="default"/>
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<compiler name="Visual Studio" spec="SuperH4.cspec" id="windows"/>
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<external_name tool="IDA-PRO" name="sh4"/>
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</language>
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</language_definitions>
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12
Ghidra/Processors/SuperH4/data/languages/SuperH4.opinion
Normal file
12
Ghidra/Processors/SuperH4/data/languages/SuperH4.opinion
Normal file
@ -0,0 +1,12 @@
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<opinions>
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<constraint loader="Portable Executable (PE)" compilerSpecID="windows">
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<constraint primary="422" processor="SuperH4" endian="little" size="32" />
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</constraint>
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<constraint loader="MS Common Object File Format (COFF)" compilerSpecID="windows">
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<constraint primary="422" processor="SuperH4" endian="little" size="32" />
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</constraint>
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<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
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<constraint primary="42" processor="SuperH4" endian="little" size="32" />
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<constraint primary="42" processor="SuperH4" endian="big" size="32" />
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</constraint>
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</opinions>
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9
Ghidra/Processors/SuperH4/data/languages/SuperH4.pspec
Normal file
9
Ghidra/Processors/SuperH4/data/languages/SuperH4.pspec
Normal file
@ -0,0 +1,9 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<processor_spec>
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<properties>
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<property key="assemblyRating:SuperH4:BE:32:default" value="PLATINUM"/>
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<property key="assemblyRating:SuperH4:LE:32:default" value="PLATINUM"/>
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</properties>
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<programcounter register="PC"/>
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</processor_spec>
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4001
Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc
Normal file
4001
Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,8 @@
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# This module defines SuperH version 4a, but should work against versions 1,2, and 3.
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# DSP Extensions are not yet added
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# Based on "Renesas SH-4 Software Manual: Rev 6.00 2006.09 (i.e. rej09b0318_sh_4sm.pdf)
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@define ENDIAN "big"
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@include "SuperH4.sinc"
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@ -0,0 +1,9 @@
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# This module defines SuperH version 4, but should work against versions 1,2, and 3.
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# There is a SuperH version 4A (which has 4 byte instruction length) which has instructions incompatable
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# with this.
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# Based on "Renesas SH-4 Software Manual: Rev 6.00 2006.09 (i.e. rej09b0318_sh_4sm.pdf)
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@define ENDIAN "little"
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@include "SuperH4.sinc"
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131
Ghidra/Processors/SuperH4/data/languages/old/SuperH4-BE-16.lang
Normal file
131
Ghidra/Processors/SuperH4/data/languages/old/SuperH4-BE-16.lang
Normal file
@ -0,0 +1,131 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<language version="1" endian="big">
|
||||
<description>
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||||
<id>SuperH4:BE:16:default</id>
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<processor>SuperH4</processor>
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<variant>default</variant>
|
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<size>16</size>
|
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</description>
|
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<compiler name="default" id="default" />
|
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<spaces>
|
||||
<space name="ram" type="ram" size="4" default="yes" />
|
||||
<space name="register" type="register" size="4" />
|
||||
</spaces>
|
||||
<registers>
|
||||
<context_register name="FPSCR" offset="0x810" bitsize="32">
|
||||
<field name="doubleWidthMoveMode" range="1,1" />
|
||||
<field name="doublePrecMode" range="0,0" />
|
||||
</context_register>
|
||||
<register name="r0" offset="0x0" bitsize="32" />
|
||||
<register name="r1" offset="0x4" bitsize="32" />
|
||||
<register name="r2" offset="0x8" bitsize="32" />
|
||||
<register name="r3" offset="0xc" bitsize="32" />
|
||||
<register name="r4" offset="0x10" bitsize="32" />
|
||||
<register name="r5" offset="0x14" bitsize="32" />
|
||||
<register name="r6" offset="0x18" bitsize="32" />
|
||||
<register name="r7" offset="0x1c" bitsize="32" />
|
||||
<register name="r8" offset="0x20" bitsize="32" />
|
||||
<register name="r9" offset="0x24" bitsize="32" />
|
||||
<register name="r10" offset="0x28" bitsize="32" />
|
||||
<register name="r11" offset="0x2c" bitsize="32" />
|
||||
<register name="r12" offset="0x30" bitsize="32" />
|
||||
<register name="r13" offset="0x34" bitsize="32" />
|
||||
<register name="r14" offset="0x38" bitsize="32" />
|
||||
<register name="r15" offset="0x3c" bitsize="32" />
|
||||
<register name="R0_BANK" offset="0x40" bitsize="32" />
|
||||
<register name="R1_BANK" offset="0x44" bitsize="32" />
|
||||
<register name="R2_BANK" offset="0x48" bitsize="32" />
|
||||
<register name="R3_BANK" offset="0x4c" bitsize="32" />
|
||||
<register name="R4_BANK" offset="0x50" bitsize="32" />
|
||||
<register name="R5_BANK" offset="0x54" bitsize="32" />
|
||||
<register name="R6_BANK" offset="0x58" bitsize="32" />
|
||||
<register name="R7_BANK" offset="0x5c" bitsize="32" />
|
||||
<register name="R_BANK0" offset="0x0" bitsize="256" />
|
||||
<register name="R_UNBANKED" offset="0x20" bitsize="256" />
|
||||
<register name="R_BANK1" offset="0x40" bitsize="256" />
|
||||
<register name="fr0" offset="0x200" bitsize="32" />
|
||||
<register name="fr1" offset="0x204" bitsize="32" />
|
||||
<register name="fr2" offset="0x208" bitsize="32" />
|
||||
<register name="fr3" offset="0x20c" bitsize="32" />
|
||||
<register name="fr4" offset="0x210" bitsize="32" />
|
||||
<register name="fr5" offset="0x214" bitsize="32" />
|
||||
<register name="fr6" offset="0x218" bitsize="32" />
|
||||
<register name="fr7" offset="0x21c" bitsize="32" />
|
||||
<register name="fr8" offset="0x220" bitsize="32" />
|
||||
<register name="fr9" offset="0x224" bitsize="32" />
|
||||
<register name="fr10" offset="0x228" bitsize="32" />
|
||||
<register name="fr11" offset="0x22c" bitsize="32" />
|
||||
<register name="fr12" offset="0x230" bitsize="32" />
|
||||
<register name="fr13" offset="0x234" bitsize="32" />
|
||||
<register name="fr14" offset="0x238" bitsize="32" />
|
||||
<register name="fr15" offset="0x23c" bitsize="32" />
|
||||
<register name="xf0" offset="0x240" bitsize="32" />
|
||||
<register name="xf1" offset="0x244" bitsize="32" />
|
||||
<register name="xf2" offset="0x248" bitsize="32" />
|
||||
<register name="xf3" offset="0x24c" bitsize="32" />
|
||||
<register name="xf4" offset="0x250" bitsize="32" />
|
||||
<register name="xf5" offset="0x254" bitsize="32" />
|
||||
<register name="xf6" offset="0x258" bitsize="32" />
|
||||
<register name="xf7" offset="0x25c" bitsize="32" />
|
||||
<register name="xf8" offset="0x260" bitsize="32" />
|
||||
<register name="xf9" offset="0x264" bitsize="32" />
|
||||
<register name="xf10" offset="0x268" bitsize="32" />
|
||||
<register name="xf11" offset="0x26c" bitsize="32" />
|
||||
<register name="xf12" offset="0x270" bitsize="32" />
|
||||
<register name="xf13" offset="0x274" bitsize="32" />
|
||||
<register name="xf14" offset="0x278" bitsize="32" />
|
||||
<register name="xf15" offset="0x27c" bitsize="32" />
|
||||
<register name="dr0" offset="0x200" bitsize="64" />
|
||||
<register name="dr2" offset="0x208" bitsize="64" />
|
||||
<register name="dr4" offset="0x210" bitsize="64" />
|
||||
<register name="dr6" offset="0x218" bitsize="64" />
|
||||
<register name="dr8" offset="0x220" bitsize="64" />
|
||||
<register name="dr10" offset="0x228" bitsize="64" />
|
||||
<register name="dr12" offset="0x230" bitsize="64" />
|
||||
<register name="dr14" offset="0x238" bitsize="64" />
|
||||
<register name="xd0" offset="0x240" bitsize="64" />
|
||||
<register name="xd2" offset="0x248" bitsize="64" />
|
||||
<register name="xd4" offset="0x250" bitsize="64" />
|
||||
<register name="xd6" offset="0x258" bitsize="64" />
|
||||
<register name="xd8" offset="0x260" bitsize="64" />
|
||||
<register name="xd10" offset="0x268" bitsize="64" />
|
||||
<register name="xd12" offset="0x270" bitsize="64" />
|
||||
<register name="xd14" offset="0x278" bitsize="64" />
|
||||
<register name="fv0" offset="0x200" bitsize="128" />
|
||||
<register name="fv4" offset="0x210" bitsize="128" />
|
||||
<register name="fv8" offset="0x220" bitsize="128" />
|
||||
<register name="fv12" offset="0x230" bitsize="128" />
|
||||
<register name="FPR_BANK0" offset="0x200" bitsize="512" />
|
||||
<register name="FPR_BANK1" offset="0x240" bitsize="512" />
|
||||
<register name="GBR" offset="0x400" bitsize="32" />
|
||||
<register name="SR" offset="0x404" bitsize="32" />
|
||||
<register name="SSR" offset="0x408" bitsize="32" />
|
||||
<register name="SPC" offset="0x40c" bitsize="32" />
|
||||
<register name="VBR" offset="0x410" bitsize="32" />
|
||||
<register name="SGR" offset="0x414" bitsize="32" />
|
||||
<register name="DBR" offset="0x418" bitsize="32" />
|
||||
<register name="MD" offset="0x600" bitsize="8" />
|
||||
<register name="RB" offset="0x601" bitsize="8" />
|
||||
<register name="BL" offset="0x602" bitsize="8" />
|
||||
<register name="FD" offset="0x603" bitsize="8" />
|
||||
<register name="M" offset="0x604" bitsize="8" />
|
||||
<register name="Q" offset="0x605" bitsize="8" />
|
||||
<register name="IMASK" offset="0x606" bitsize="8" />
|
||||
<register name="S" offset="0x607" bitsize="8" />
|
||||
<register name="T" offset="0x608" bitsize="8" />
|
||||
<register name="MACH" offset="0x800" bitsize="32" />
|
||||
<register name="MACL" offset="0x804" bitsize="32" />
|
||||
<register name="PR" offset="0x808" bitsize="32" />
|
||||
<register name="PC" offset="0x80c" bitsize="32" />
|
||||
<register name="FPUL" offset="0x814" bitsize="32" />
|
||||
<register name="FPSCR_RM" offset="0xa00" bitsize="8" />
|
||||
<register name="FPSCR_FLAG" offset="0xa01" bitsize="8" />
|
||||
<register name="FPSCR_ENABLE" offset="0xa02" bitsize="8" />
|
||||
<register name="FPSCR_CAUSE" offset="0xa03" bitsize="8" />
|
||||
<register name="FPSCR_DN" offset="0xa04" bitsize="8" />
|
||||
<register name="FPSCR_PR" offset="0xa05" bitsize="8" />
|
||||
<register name="FPSCR_SZ" offset="0xa06" bitsize="8" />
|
||||
<register name="FPSCR_FR" offset="0xa07" bitsize="8" />
|
||||
</registers>
|
||||
</language>
|
||||
|
||||
@ -0,0 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<language_translation>
|
||||
<from_language version="1">SuperH4:BE:16:default</from_language>
|
||||
<to_language version="1">SuperH4:BE:32:default</to_language>
|
||||
<map_compiler_spec from="default" to="default" />
|
||||
</language_translation>
|
||||
|
||||
131
Ghidra/Processors/SuperH4/data/languages/old/SuperH4-LE-16.lang
Normal file
131
Ghidra/Processors/SuperH4/data/languages/old/SuperH4-LE-16.lang
Normal file
@ -0,0 +1,131 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<language version="1" endian="little">
|
||||
<description>
|
||||
<id>SuperH4:LE:16:default</id>
|
||||
<processor>SuperH4</processor>
|
||||
<variant>default</variant>
|
||||
<size>16</size>
|
||||
</description>
|
||||
<compiler name="default" id="default" />
|
||||
<spaces>
|
||||
<space name="ram" type="ram" size="4" default="yes" />
|
||||
<space name="register" type="register" size="4" />
|
||||
</spaces>
|
||||
<registers>
|
||||
<context_register name="FPSCR" offset="0x810" bitsize="32">
|
||||
<field name="doubleWidthMoveMode" range="1,1" />
|
||||
<field name="doublePrecMode" range="0,0" />
|
||||
</context_register>
|
||||
<register name="r0" offset="0x0" bitsize="32" />
|
||||
<register name="r1" offset="0x4" bitsize="32" />
|
||||
<register name="r2" offset="0x8" bitsize="32" />
|
||||
<register name="r3" offset="0xc" bitsize="32" />
|
||||
<register name="r4" offset="0x10" bitsize="32" />
|
||||
<register name="r5" offset="0x14" bitsize="32" />
|
||||
<register name="r6" offset="0x18" bitsize="32" />
|
||||
<register name="r7" offset="0x1c" bitsize="32" />
|
||||
<register name="r8" offset="0x20" bitsize="32" />
|
||||
<register name="r9" offset="0x24" bitsize="32" />
|
||||
<register name="r10" offset="0x28" bitsize="32" />
|
||||
<register name="r11" offset="0x2c" bitsize="32" />
|
||||
<register name="r12" offset="0x30" bitsize="32" />
|
||||
<register name="r13" offset="0x34" bitsize="32" />
|
||||
<register name="r14" offset="0x38" bitsize="32" />
|
||||
<register name="r15" offset="0x3c" bitsize="32" />
|
||||
<register name="R0_BANK" offset="0x40" bitsize="32" />
|
||||
<register name="R1_BANK" offset="0x44" bitsize="32" />
|
||||
<register name="R2_BANK" offset="0x48" bitsize="32" />
|
||||
<register name="R3_BANK" offset="0x4c" bitsize="32" />
|
||||
<register name="R4_BANK" offset="0x50" bitsize="32" />
|
||||
<register name="R5_BANK" offset="0x54" bitsize="32" />
|
||||
<register name="R6_BANK" offset="0x58" bitsize="32" />
|
||||
<register name="R7_BANK" offset="0x5c" bitsize="32" />
|
||||
<register name="R_BANK0" offset="0x0" bitsize="256" />
|
||||
<register name="R_UNBANKED" offset="0x20" bitsize="256" />
|
||||
<register name="R_BANK1" offset="0x40" bitsize="256" />
|
||||
<register name="fr0" offset="0x200" bitsize="32" />
|
||||
<register name="fr1" offset="0x204" bitsize="32" />
|
||||
<register name="fr2" offset="0x208" bitsize="32" />
|
||||
<register name="fr3" offset="0x20c" bitsize="32" />
|
||||
<register name="fr4" offset="0x210" bitsize="32" />
|
||||
<register name="fr5" offset="0x214" bitsize="32" />
|
||||
<register name="fr6" offset="0x218" bitsize="32" />
|
||||
<register name="fr7" offset="0x21c" bitsize="32" />
|
||||
<register name="fr8" offset="0x220" bitsize="32" />
|
||||
<register name="fr9" offset="0x224" bitsize="32" />
|
||||
<register name="fr10" offset="0x228" bitsize="32" />
|
||||
<register name="fr11" offset="0x22c" bitsize="32" />
|
||||
<register name="fr12" offset="0x230" bitsize="32" />
|
||||
<register name="fr13" offset="0x234" bitsize="32" />
|
||||
<register name="fr14" offset="0x238" bitsize="32" />
|
||||
<register name="fr15" offset="0x23c" bitsize="32" />
|
||||
<register name="xf0" offset="0x240" bitsize="32" />
|
||||
<register name="xf1" offset="0x244" bitsize="32" />
|
||||
<register name="xf2" offset="0x248" bitsize="32" />
|
||||
<register name="xf3" offset="0x24c" bitsize="32" />
|
||||
<register name="xf4" offset="0x250" bitsize="32" />
|
||||
<register name="xf5" offset="0x254" bitsize="32" />
|
||||
<register name="xf6" offset="0x258" bitsize="32" />
|
||||
<register name="xf7" offset="0x25c" bitsize="32" />
|
||||
<register name="xf8" offset="0x260" bitsize="32" />
|
||||
<register name="xf9" offset="0x264" bitsize="32" />
|
||||
<register name="xf10" offset="0x268" bitsize="32" />
|
||||
<register name="xf11" offset="0x26c" bitsize="32" />
|
||||
<register name="xf12" offset="0x270" bitsize="32" />
|
||||
<register name="xf13" offset="0x274" bitsize="32" />
|
||||
<register name="xf14" offset="0x278" bitsize="32" />
|
||||
<register name="xf15" offset="0x27c" bitsize="32" />
|
||||
<register name="dr0" offset="0x200" bitsize="64" />
|
||||
<register name="dr2" offset="0x208" bitsize="64" />
|
||||
<register name="dr4" offset="0x210" bitsize="64" />
|
||||
<register name="dr6" offset="0x218" bitsize="64" />
|
||||
<register name="dr8" offset="0x220" bitsize="64" />
|
||||
<register name="dr10" offset="0x228" bitsize="64" />
|
||||
<register name="dr12" offset="0x230" bitsize="64" />
|
||||
<register name="dr14" offset="0x238" bitsize="64" />
|
||||
<register name="xd0" offset="0x240" bitsize="64" />
|
||||
<register name="xd2" offset="0x248" bitsize="64" />
|
||||
<register name="xd4" offset="0x250" bitsize="64" />
|
||||
<register name="xd6" offset="0x258" bitsize="64" />
|
||||
<register name="xd8" offset="0x260" bitsize="64" />
|
||||
<register name="xd10" offset="0x268" bitsize="64" />
|
||||
<register name="xd12" offset="0x270" bitsize="64" />
|
||||
<register name="xd14" offset="0x278" bitsize="64" />
|
||||
<register name="fv0" offset="0x200" bitsize="128" />
|
||||
<register name="fv4" offset="0x210" bitsize="128" />
|
||||
<register name="fv8" offset="0x220" bitsize="128" />
|
||||
<register name="fv12" offset="0x230" bitsize="128" />
|
||||
<register name="FPR_BANK0" offset="0x200" bitsize="512" />
|
||||
<register name="FPR_BANK1" offset="0x240" bitsize="512" />
|
||||
<register name="GBR" offset="0x400" bitsize="32" />
|
||||
<register name="SR" offset="0x404" bitsize="32" />
|
||||
<register name="SSR" offset="0x408" bitsize="32" />
|
||||
<register name="SPC" offset="0x40c" bitsize="32" />
|
||||
<register name="VBR" offset="0x410" bitsize="32" />
|
||||
<register name="SGR" offset="0x414" bitsize="32" />
|
||||
<register name="DBR" offset="0x418" bitsize="32" />
|
||||
<register name="MD" offset="0x600" bitsize="8" />
|
||||
<register name="RB" offset="0x601" bitsize="8" />
|
||||
<register name="BL" offset="0x602" bitsize="8" />
|
||||
<register name="FD" offset="0x603" bitsize="8" />
|
||||
<register name="M" offset="0x604" bitsize="8" />
|
||||
<register name="Q" offset="0x605" bitsize="8" />
|
||||
<register name="IMASK" offset="0x606" bitsize="8" />
|
||||
<register name="S" offset="0x607" bitsize="8" />
|
||||
<register name="T" offset="0x608" bitsize="8" />
|
||||
<register name="MACH" offset="0x800" bitsize="32" />
|
||||
<register name="MACL" offset="0x804" bitsize="32" />
|
||||
<register name="PR" offset="0x808" bitsize="32" />
|
||||
<register name="PC" offset="0x80c" bitsize="32" />
|
||||
<register name="FPUL" offset="0x814" bitsize="32" />
|
||||
<register name="FPSCR_RM" offset="0xa00" bitsize="8" />
|
||||
<register name="FPSCR_FLAG" offset="0xa01" bitsize="8" />
|
||||
<register name="FPSCR_ENABLE" offset="0xa02" bitsize="8" />
|
||||
<register name="FPSCR_CAUSE" offset="0xa03" bitsize="8" />
|
||||
<register name="FPSCR_DN" offset="0xa04" bitsize="8" />
|
||||
<register name="FPSCR_PR" offset="0xa05" bitsize="8" />
|
||||
<register name="FPSCR_SZ" offset="0xa06" bitsize="8" />
|
||||
<register name="FPSCR_FR" offset="0xa07" bitsize="8" />
|
||||
</registers>
|
||||
</language>
|
||||
|
||||
@ -0,0 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<language_translation>
|
||||
<from_language version="1">SuperH4:LE:16:default</from_language>
|
||||
<to_language version="1">SuperH4:LE:32:default</to_language>
|
||||
<map_compiler_spec from="default" to="default" />
|
||||
</language_translation>
|
||||
|
||||
132
Ghidra/Processors/SuperH4/data/manuals/superh4.idx
Normal file
132
Ghidra/Processors/SuperH4/data/manuals/superh4.idx
Normal file
@ -0,0 +1,132 @@
|
||||
@ rej09b0318_sh_4sm.pdf[SH-4 Software Manual Rev 6.00 2006.09]
|
||||
add, 229
|
||||
addc, 231
|
||||
addv, 232
|
||||
and, 234
|
||||
and.b, 234
|
||||
bf, 236
|
||||
bf/s, 238
|
||||
bra, 240
|
||||
braf, 242
|
||||
bsr, 244
|
||||
bsrf, 246
|
||||
bt, 248
|
||||
bt/s, 250
|
||||
clrmac, 252
|
||||
clrs, 253
|
||||
clrt, 254
|
||||
cmp/eq, 255
|
||||
cmp/ge, 255
|
||||
cmp/gt, 255
|
||||
cmp/hi, 255
|
||||
cmp/hs, 255
|
||||
cmp/pl, 255
|
||||
cmp/pz, 255
|
||||
cmp/str, 255
|
||||
cmp/eq, 255
|
||||
cmp/str, 255
|
||||
div0s, 259
|
||||
div0u, 260
|
||||
div1, 261
|
||||
dmuls.l, 266
|
||||
dmulu.l, 268
|
||||
dt, 270
|
||||
exts.b, 271
|
||||
exts.w, 271
|
||||
extu.b, 273
|
||||
extu.w, 273
|
||||
jmp, 331
|
||||
jsr, 332
|
||||
ldc, 334
|
||||
ldc.l, 334
|
||||
lds, 339
|
||||
lds.l, 339
|
||||
ldtlb, 343
|
||||
mac.l, 345
|
||||
mac, 349
|
||||
mac.w, 349
|
||||
mov, 352
|
||||
mov.b, 352
|
||||
mov.w, 352
|
||||
mov.l, 352
|
||||
mova, 367
|
||||
movca.l, 368
|
||||
movt, 369
|
||||
mul.l, 370
|
||||
muls.w, 371
|
||||
muls, 371
|
||||
mulu.w, 372
|
||||
mulu, 372
|
||||
neg, 373
|
||||
negc, 374
|
||||
nop, 375
|
||||
not, 376
|
||||
ocbi, 377
|
||||
ocbp, 378
|
||||
ocbwb, 379
|
||||
or, 380
|
||||
or.b, 380
|
||||
pref, 382
|
||||
rotcl, 383
|
||||
rotcr, 384
|
||||
rotl, 385
|
||||
rotr, 386
|
||||
rte, 387
|
||||
rts, 389
|
||||
sets, 391
|
||||
sett, 392
|
||||
shad, 393
|
||||
shal, 395
|
||||
shar, 396
|
||||
shld, 397
|
||||
shll, 399
|
||||
shll2, 400
|
||||
shll8, 400
|
||||
shll16, 400
|
||||
shlr, 402
|
||||
shlr2, 403
|
||||
shlr8, 403
|
||||
shlr16, 403
|
||||
sleep, 405
|
||||
stc, 406
|
||||
stc.l, 406
|
||||
sts, 411
|
||||
sts.l, 411
|
||||
sub, 416
|
||||
subc, 417
|
||||
subv, 418
|
||||
swap.b, 420
|
||||
swap.w, 420
|
||||
tas.b, 422
|
||||
trapa, 424
|
||||
tst, 426
|
||||
tst.b, 426
|
||||
xor, 428
|
||||
xor.b, 428
|
||||
xtrct, 430
|
||||
fabs, 275
|
||||
fadd, 276
|
||||
fcmp/eq, 279
|
||||
fcmp/gt, 279
|
||||
fcnvds, 283
|
||||
fcnvsd, 286
|
||||
fdiv, 288
|
||||
fipr, 292
|
||||
fldi0, 294
|
||||
fldi1, 295
|
||||
flds, 296
|
||||
float, 297
|
||||
fmac, 299
|
||||
fmov, 305
|
||||
fmov.s, 305
|
||||
fmul, 312
|
||||
fneg, 315
|
||||
frchg, 316
|
||||
fschg, 317
|
||||
fsqrt, 318
|
||||
fsts, 321
|
||||
fsub, 322
|
||||
ftrc, 325
|
||||
ftrv, 328
|
||||
|
||||
|
||||
17
Ghidra/Processors/SuperH4/data/patterns/SuperH4_patterns.xml
Normal file
17
Ghidra/Processors/SuperH4/data/patterns/SuperH4_patterns.xml
Normal file
@ -0,0 +1,17 @@
|
||||
<patternlist>
|
||||
<patternpairs totalbits="32" postbits="16">
|
||||
<prepatterns>
|
||||
<data>0x0b 0x00 0x09 0x00 </data> <!-- rts _nop -->
|
||||
<data>0x0b 0x00 0xf6 0x6. </data> <!-- rts _mov.l @r15+,<rx> -->
|
||||
<data>0x0b 0x00 0x09 0x00 0x00 0x00 </data> <!-- rts _nop filler -->
|
||||
<data>0x0b 0x00 0x.. 0x7f </data> <!-- rts add <#x>,r15 -->
|
||||
</prepatterns>
|
||||
<postpatterns>
|
||||
<data>10011101 11100011 10111... ........</data> <!-- save sp, xx, sp -->
|
||||
<data>0x22 0x4f </data> <!-- sts.l pr,@-r15 -->
|
||||
<data>0x22 0x4f 1....... 0x7f </data> <!-- sts.l pr,@-r15 add#-<x>,r15 -->
|
||||
<data> 1....... 0x7f </data> <!-- add #-<x>, r15 -->
|
||||
<funcstart/>
|
||||
</postpatterns>
|
||||
</patternpairs>
|
||||
</patternlist>
|
||||
@ -0,0 +1,5 @@
|
||||
<patternconstraints>
|
||||
<language id="SuperH4:LE:32:*">
|
||||
<patternfile>SuperH4_patterns.xml</patternfile>
|
||||
</language>
|
||||
</patternconstraints>
|
||||
@ -0,0 +1,41 @@
|
||||
/* ###
|
||||
* IP: GHIDRA
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
package ghidra.test.processors;
|
||||
|
||||
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
|
||||
import junit.framework.Test;
|
||||
|
||||
public class SuperH4_BE_O0_EmulatorTest extends ProcessorEmulatorTestAdapter {
|
||||
|
||||
private static final String LANGUAGE_ID = "SuperH4:BE:32:default";
|
||||
private static final String COMPILER_SPEC_ID = "default";
|
||||
|
||||
private static final String[] REG_DUMP_SET = new String[] {};
|
||||
|
||||
public SuperH4_BE_O0_EmulatorTest(String name) throws Exception {
|
||||
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
|
||||
}
|
||||
|
||||
@Override
|
||||
protected String getProcessorDesignator() {
|
||||
return "SH4_GCC_O0";
|
||||
}
|
||||
|
||||
public static Test suite() {
|
||||
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(
|
||||
SuperH4_BE_O0_EmulatorTest.class);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,41 @@
|
||||
/* ###
|
||||
* IP: GHIDRA
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
package ghidra.test.processors;
|
||||
|
||||
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
|
||||
import junit.framework.Test;
|
||||
|
||||
public class SuperH4_BE_O3_EmulatorTest extends ProcessorEmulatorTestAdapter {
|
||||
|
||||
private static final String LANGUAGE_ID = "SuperH4:BE:32:default";
|
||||
private static final String COMPILER_SPEC_ID = "default";
|
||||
|
||||
private static final String[] REG_DUMP_SET = new String[] {};
|
||||
|
||||
public SuperH4_BE_O3_EmulatorTest(String name) throws Exception {
|
||||
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
|
||||
}
|
||||
|
||||
@Override
|
||||
protected String getProcessorDesignator() {
|
||||
return "SH4_GCC_O3";
|
||||
}
|
||||
|
||||
public static Test suite() {
|
||||
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(
|
||||
SuperH4_BE_O3_EmulatorTest.class);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,40 @@
|
||||
/* ###
|
||||
* IP: GHIDRA
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
package ghidra.test.processors;
|
||||
|
||||
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
|
||||
import junit.framework.Test;
|
||||
|
||||
public class SuperH4_O0_EmulatorTest extends ProcessorEmulatorTestAdapter {
|
||||
|
||||
private static final String LANGUAGE_ID = "SuperH4:LE:32:default";
|
||||
private static final String COMPILER_SPEC_ID = "default";
|
||||
|
||||
private static final String[] REG_DUMP_SET = new String[] {};
|
||||
|
||||
public SuperH4_O0_EmulatorTest(String name) throws Exception {
|
||||
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
|
||||
}
|
||||
|
||||
@Override
|
||||
protected String getProcessorDesignator() {
|
||||
return "SH4_LE_GCC_O0";
|
||||
}
|
||||
|
||||
public static Test suite() {
|
||||
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(SuperH4_O0_EmulatorTest.class);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,40 @@
|
||||
/* ###
|
||||
* IP: GHIDRA
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
package ghidra.test.processors;
|
||||
|
||||
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
|
||||
import junit.framework.Test;
|
||||
|
||||
public class SuperH4_O3_EmulatorTest extends ProcessorEmulatorTestAdapter {
|
||||
|
||||
private static final String LANGUAGE_ID = "SuperH4:LE:32:default";
|
||||
private static final String COMPILER_SPEC_ID = "default";
|
||||
|
||||
private static final String[] REG_DUMP_SET = new String[] {};
|
||||
|
||||
public SuperH4_O3_EmulatorTest(String name) throws Exception {
|
||||
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
|
||||
}
|
||||
|
||||
@Override
|
||||
protected String getProcessorDesignator() {
|
||||
return "SH4_LE_GCC_O3";
|
||||
}
|
||||
|
||||
public static Test suite() {
|
||||
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(SuperH4_O3_EmulatorTest.class);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user