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Merge remote-tracking branch 'origin/patch'

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This commit is contained in:
Ryan Kurtz 2023-01-13 08:17:56 -05:00
commit 82ac8f7143
5 changed files with 43 additions and 33 deletions
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33
Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc
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@ -113,36 +113,33 @@
DCRN = D;
}
# mtmsr varies from processor to processor. This version is consistent with PowerISA v2.07B
#mtmsr r0,0 0x7c 00 01 24
:mtmsr S,0 is OP=31 & S & BITS_17_20=0 & MSR_L=0 & BITS_11_15=0 & XOP_1_10=146 & BIT_0=0
{
bit58:$(REGISTER_SIZE) = (S >> 5) & 1; #bit 58
bit49:$(REGISTER_SIZE) = (S >> 14)& 1; #bit 49
bit59:$(REGISTER_SIZE) = (S >> 4) & 1; #bit 59
@ifdef BIT_64
tmp:8 = S & 0x00000000ffff6fcf; #0b00000000000000000000000000000000 1111 1111 1111 1111 0110 1111 1100 1111
tmp = tmp & ((bit58 | bit49) << 5);
tmp = tmp & ((bit59 | bit49) << 4);
MSR = MSR & 0xffffffff00009030 | tmp;
@else
tmp:4 = S & 0xffff6fcf;
tmp = tmp & ((bit58 | bit49) << 5);
tmp = tmp & ((bit59 | bit49) << 4);
MSR = MSR & 0x00009000 | tmp;
@endif
bit58:$(REGISTER_SIZE) = (S >> 5) & 1; #bit 58
bit49:$(REGISTER_SIZE) = (S >> 14) & 1; #bit 49
bit48:$(REGISTER_SIZE) = (S >> 15) & 1; #bit 48
local mask:$(REGISTER_SIZE) = 0xffff6fcf; # preserves bits 32:47 49:50 52:57 60:62
local tmp:$(REGISTER_SIZE) = S & mask; # 1111 1111 1111 1111 0110 1111 1100 1111
tmp = tmp | ((bit48 | bit49) << 15); # MSR 48 <- (RS) 48 | (RS) 49
tmp = tmp | ((bit58 | bit49) << 5); # MSR 58 <- (RS) 58 | (RS) 49
tmp = tmp | ((bit59 | bit49) << 4); # MSR 59 <- (RS) 59 | (RS) 49
MSR = (MSR & ~mask) | tmp;
}
#mtmsr r0,1 0x7c 01 01 24
:mtmsr S,1 is OP=31 & S & BITS_17_20=0 & MSR_L=1 & BITS_11_15=0 & XOP_1_10=146 & BIT_0=0
{
@ifdef BIT_64
mask:8 = 0x000000000000fffe;
@else
mask:4 = 0x0000fffe;
@endif
mask:$(REGISTER_SIZE) = 0x8002; #preserves bits 48 and 62
MSR = (MSR & ~mask) | (S & mask);
}
#mtspr spr000,r0 0x7c 00 02 a6
:mtspr SPRVAL,S is OP=31 & SPRVAL & S & XOP_1_10=467 & BIT_0=0
{

34
Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc
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@ -3152,29 +3152,41 @@ define pcodeop lswxOp;
cr1flags();
}
# This instruction is not exclusive to 64 bit processors, per page 1259 of the PowerISA manual.
# However, it does seem to require 64 bit registers, so it is currently restricted to 64 bit machines.
# This instruction is not exclusive to 64 bit processors, per page 1405 of the PowerISA manual.
# Prior to the Power ISA introduction, PowerPC architecture had 32-bit versions of the MSR in 32-bit implementations.
# Since this instruction requires 64-bit processsors, it is currently restricted to 64 bit machines.
# mtmsrd varies from processor to processor. This version is consistent with PowerISA v2.07B
@ifdef BIT_64
#mtmsrd r0,0 0x7c 00 01 64
:mtmsrd S,0 is $(NOTVLE) & OP=31 & S & BITS_17_20=0 & MSR_L=0 & BITS_11_15=0 & XOP_1_10=178 & BIT_0=0
{
bit0:8 = S >> 63 & 1;
bit1:8 = S >> 62 & 1;
bit49:8 = (S >> 14)& 1;
bit59:8 = (S >> 4) & 1;
tmp:8 = S & 0x6fffffffffff6fcf;
tmp = tmp & ((bit0 | bit1) << 63);
tmp = tmp & ((bit59 | bit49) << 5);
MSR = MSR & 0xefffffff00009020 | tmp;
local bit59:$(REGISTER_SIZE) = (S >> 4) & 1; #bit 59
local bit58:$(REGISTER_SIZE) = (S >> 5) & 1; #bit 58
local bit49:$(REGISTER_SIZE) = (S >> 14) & 1; #bit 49
local bit48:$(REGISTER_SIZE) = (S >> 15) & 1; #bit 48
local bits2931:$(REGISTER_SIZE) = zext(S[32,3]); #bits 29-31
local mbits2931:$(REGISTER_SIZE) = zext(MSR[32,3]); #bits 29-31
local cond = (mbits2931 != 0x2)|(bits2931 != 0);
bits2931 = (zext(cond) * bits2931) + (zext(!cond) * mbits2931);
local mask:$(REGISTER_SIZE) =0xeffffff8ffff6fce;
tmp:8 = S & mask; #preserves (RS) 0:2 4:40 42:47 49:50 52:57 60:62
tmp = tmp | (bits2931) << 32;
tmp = tmp | ((bit48 | bit49) << 15); # MSR 48 <- (RS) 48 | (RS) 49
tmp = tmp | ((bit58 | bit49) << 5); # MSR 58 <- (RS) 58 | (RS) 49
tmp = tmp | ((bit59 | bit49) << 4); # MSR 59 <- (RS) 59 | (RS) 49
MSR = (MSR & ~mask) | tmp;
}
#mtmsrd r0,1 0x7c 01 01 64
:mtmsrd S,1 is $(NOTVLE) & OP=31 & S & BITS_17_20=0 & MSR_L=1 & BITS_11_15=0 & XOP_1_10=178 & BIT_0=0
{
mask:8 = 0x000000000000fffe & S;
mask:$(REGISTER_SIZE) = 0x8002;
MSR = (MSR & ~mask) | (S & mask);
}
@endif
CRM_val: crmval is CRM [crmval = CRM+0;] {export *[const]:1 crmval;}
#mtocrf 10,r0 0x7c 21 01 20
:mtocrf CRM_val,S is OP=31 & S & BIT_20=1 & CRM_val & CRM0 & CRM1 & CRM2 & CRM3 & CRM4 & CRM5 & CRM6 & CRM7 & BIT_11=0 & XOP_1_10=144 & BIT_0=0

2
Ghidra/RuntimeScripts/Linux/support/launch.sh
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@ -145,7 +145,7 @@ fi
JAVA_CMD="${JAVA_HOME}/bin/java"
# Get the configurable VM arguments from the launch properties
while IFS= read -r line; do
while IFS=$'\r\n' read -r line; do
VMARGS_FROM_LAUNCH_PROPS+=("$line")
done < <(java -cp "${LS_CPATH}" LaunchSupport "${INSTALL_DIR}" -vmargs)

2
Ghidra/RuntimeScripts/Windows/support/launch.bat
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@ -129,7 +129,7 @@ if "%JAVA_HOME%" == "" (
set "JAVA_CMD=%JAVA_HOME%\bin\java"
:: Get the configurable VM arguments from the launch properties
for /f "delims=*" %%i in ('java -cp "%LS_CPATH%" LaunchSupport "%INSTALL_DIR%" -vmargs') do set VMARG_LIST=%VMARG_LIST% %%i
for /f "delims=*" %%i in ('java -cp "%LS_CPATH%" LaunchSupport "%INSTALL_DIR%" -vmargs') do set VMARG_LIST=!VMARG_LIST! %%i
:: Set Max Heap Size if specified
if not "%MAXMEM%"=="" (

3
GhidraBuild/LaunchSupport/src/main/java/LaunchSupport.java
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@ -291,7 +291,8 @@ public class LaunchSupport {
return EXIT_FAILURE;
}
javaConfig.getLaunchProperties().getVmArgList().forEach(arg -> System.out.println(arg));
// Force newline style to make cross-platform parsing consistent
javaConfig.getLaunchProperties().getVmArgList().forEach(e -> System.out.print(e + "\r\n"));
return EXIT_SUCCESS;
}
}