mirror of
https://github.com/NationalSecurityAgency/ghidra.git
synced 2024-11-21 19:42:14 +00:00
[tricore] TRICORE processor module
This commit is contained in:
mumbel
parent
ac474530f4
commit
7fc76dbca4
0
Ghidra/Processors/tricore/Module.manifest
Normal file
0
Ghidra/Processors/tricore/Module.manifest
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8
Ghidra/Processors/tricore/build.gradle
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8
Ghidra/Processors/tricore/build.gradle
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apply plugin: 'eclipse'
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eclipse.project.name = 'Processors tricore'
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/*********************************************************************************
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* Imports
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*********************************************************************************/
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apply from: "$rootProject.projectDir/gradleScripts/processorUtils.gradle"
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19
Ghidra/Processors/tricore/certification.manifest
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19
Ghidra/Processors/tricore/certification.manifest
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##VERSION: 2.0
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.classpath||GHIDRA||||END|
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.project||GHIDRA||||END|
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Module.manifest||GHIDRA||||END|
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build.gradle||GHIDRA||||END|
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data/build.xml||GHIDRA||||END|
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data/languages/tricore.cspec||GHIDRA||||END|
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data/languages/tricore.ldefs||GHIDRA||||END|
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data/languages/tricore.pspec||GHIDRA||||END|
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data/languages/tc29x.pspec||GHIDRA||||END|
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data/languages/tc172x.pspec||GHIDRA||||END|
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data/languages/tc176x.pspec||GHIDRA||||END|
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data/languages/tricore.slaspec||GHIDRA||||END|
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data/languages/tricore.sinc||GHIDRA||||END|
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data/languages/tricore.pcp.sinc||GHIDRA||||END|
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data/languages/tricore.dwarf||GHIDRA||||END|
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data/manuals/tricore.idx||GHIDRA||||END|
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data/manuals/tricore2.idx||GHIDRA||||END|
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2342
Ghidra/Processors/tricore/data/languages/tc172x.pspec
Normal file
2342
Ghidra/Processors/tricore/data/languages/tc172x.pspec
Normal file
File diff suppressed because it is too large
Load Diff
1523
Ghidra/Processors/tricore/data/languages/tc176x.pspec
Normal file
1523
Ghidra/Processors/tricore/data/languages/tc176x.pspec
Normal file
File diff suppressed because it is too large
Load Diff
3726
Ghidra/Processors/tricore/data/languages/tc29x.pspec
Normal file
3726
Ghidra/Processors/tricore/data/languages/tc29x.pspec
Normal file
File diff suppressed because it is too large
Load Diff
116
Ghidra/Processors/tricore/data/languages/tricore.cspec
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116
Ghidra/Processors/tricore/data/languages/tricore.cspec
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@ -0,0 +1,116 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<compiler_spec>
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<data_organization>
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<absolute_max_alignment value="0" />
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<machine_alignment value="8" />
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<default_alignment value="1" />
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<default_pointer_alignment value="4" />
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<pointer_size value="4" />
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<short_size value="2" />
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<integer_size value="4" />
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<long_size value="4" />
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<long_long_size value="8" />
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<float_size value="4" />
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<double_size value="8" />
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<size_alignment_map>
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<entry size="1" alignment="1" />
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<entry size="2" alignment="2" />
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<entry size="4" alignment="4" />
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<entry size="8" alignment="4" />
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</size_alignment_map>
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</data_organization>
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<global>
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<register name="a8"/>
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<register name="a9"/>
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<register name="p8"/>
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<register name="a0"/>
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<register name="a1"/>
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<register name="p0"/>
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<range space="ram"/>
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</global>
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<returnaddress>
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<register name="a11"/>
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</returnaddress>
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<stackpointer register="a10" space="ram"/>
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<default_proto>
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<prototype name="__stdcall" extrapop="0" stackshift="0" strategy="register">
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<input>
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<pentry minsize="1" maxsize="4">
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<!-- This is the first non pointer -->
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<register name="a4"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<!-- This is the first non pointer -->
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<register name="d4"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="a5"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="d5"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="a6"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="d6"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="a7"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="d7"/>
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</pentry>
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<pentry minsize="1" maxsize="500" align="4">
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<addr offset="16" space="ram"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="4">
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<register name="a2"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="d2"/>
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</pentry>
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</output>
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<unaffected>
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<register name="d8"/>
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<register name="d9"/>
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<register name="d10"/>
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<register name="d11"/>
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<register name="d12"/>
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<register name="d13"/>
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<register name="d14"/>
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<register name="d15"/>
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<register name="a10"/>
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<register name="a11"/>
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<register name="a12"/>
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<register name="a13"/>
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<register name="a14"/>
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<register name="a15"/>
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</unaffected>
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</prototype>
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</default_proto>
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<callotherfixup targetop="saveCallerState">
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<pcode>
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<input name="fcx"/>
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<input name="lcx"/>
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<input name="pcxi"/>
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<body><![CDATA[
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tmpptr:4 = 0;
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]]></body>
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</pcode>
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</callotherfixup>
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<callotherfixup targetop="restoreCallerState">
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<pcode>
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<input name="fcx"/>
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<input name="lcx"/>
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<input name="pcxi"/>
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<body><![CDATA[
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tmpptr:4 = 0;
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]]></body>
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</pcode>
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</callotherfixup>
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</compiler_spec>
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27
Ghidra/Processors/tricore/data/languages/tricore.dwarf
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27
Ghidra/Processors/tricore/data/languages/tricore.dwarf
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<dwarf>
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<register_mappings>
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<register_mapping dwarf="0" ghidra="d0" auto_count="16"/> <!-- d0..d15 -->
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<register_mapping dwarf="16" ghidra="a0" auto_count="10"/> <!-- d0.d9 -->
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<register_mapping dwarf="26" ghidra="a10" stackpointer="true"/>
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<register_mapping dwarf="27" ghidra="a11" auto_count="5"/> <!-- d11..d15 -->
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<register_mapping dwarf="32" ghidra="e0"/>
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<register_mapping dwarf="33" ghidra="e2"/>
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<register_mapping dwarf="34" ghidra="e4"/>
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<register_mapping dwarf="35" ghidra="e6"/>
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<register_mapping dwarf="36" ghidra="e8"/>
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<register_mapping dwarf="37" ghidra="e10"/>
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<register_mapping dwarf="38" ghidra="e12"/>
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<register_mapping dwarf="39" ghidra="e14"/>
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<register_mapping dwarf="40" ghidra="PSW"/>
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<register_mapping dwarf="41" ghidra="PCXI"/>
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<register_mapping dwarf="42" ghidra="PC"/>
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<register_mapping dwarf="43" ghidra="FCX"/>
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<register_mapping dwarf="44" ghidra="LCX"/>
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<register_mapping dwarf="45" ghidra="ISP"/>
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<register_mapping dwarf="46" ghidra="ICR"/>
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<register_mapping dwarf="47" ghidra="PIPN"/>
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<register_mapping dwarf="48" ghidra="BIV"/>
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<register_mapping dwarf="49" ghidra="BTV"/>
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</register_mappings>
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<call_frame_cfa value="4"/>
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</dwarf>
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57
Ghidra/Processors/tricore/data/languages/tricore.ldefs
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57
Ghidra/Processors/tricore/data/languages/tricore.ldefs
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<?xml version="1.0" encoding="UTF-8"?>
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<language_definitions>
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<language processor="tricore"
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endian="little"
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size="32"
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variant="default"
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version="1.6"
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slafile="tricore.sla"
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processorspec="tricore.pspec"
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manualindexfile="../manuals/tricore2.idx"
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id="tricore:LE:32:default">
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<description>Siemens Tricore Embedded Processor</description>
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<compiler name="default" spec="tricore.cspec" id="default"/>
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<external_name tool="DWARF.register.mapping.file" name="tricore.dwarf"/>
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</language>
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<language processor="tricore"
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endian="little"
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size="32"
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variant="TC29x"
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version="1.6"
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slafile="tricore.sla"
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processorspec="tc29x.pspec"
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manualindexfile="../manuals/tricore2.idx"
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id="tricore:LE:32:tc29x">
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<description>Siemens Tricore Embedded Processor TC29x</description>
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<compiler name="default" spec="tricore.cspec" id="default"/>
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<external_name tool="DWARF.register.mapping.file" name="tricore.dwarf"/>
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</language>
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<language processor="tricore"
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endian="little"
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size="32"
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variant="TC172x"
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version="1.3"
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slafile="tricore.sla"
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processorspec="tc172x.pspec"
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manualindexfile="../manuals/tricore.idx"
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id="tricore:LE:32:tc172x">
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<description>Siemens Tricore Embedded Processor TC1724/TC1728</description>
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<compiler name="default" spec="tricore.cspec" id="default"/>
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<external_name tool="DWARF.register.mapping.file" name="tricore.dwarf"/>
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</language>
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<language processor="tricore"
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endian="little"
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size="32"
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variant="TC176x"
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version="1.3"
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slafile="tricore.sla"
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processorspec="tc176x.pspec"
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manualindexfile="../manuals/tricore.idx"
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id="tricore:LE:32:tc176x">
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<description>Siemens Tricore Embedded Processor TC1762/TC1766</description>
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<compiler name="default" spec="tricore.cspec" id="default"/>
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<external_name tool="DWARF.register.mapping.file" name="tricore.dwarf"/>
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</language>
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</language_definitions>
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861
Ghidra/Processors/tricore/data/languages/tricore.pcp.sinc
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861
Ghidra/Processors/tricore/data/languages/tricore.pcp.sinc
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@ -0,0 +1,861 @@
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# R0 - Accumulator
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# R1 -
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# R2 - Return Address
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# R3 -
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# R4 - SRC
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# R5 - DST
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# R6 - CPPN/SRPN/TOS/CNT1
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# R7 - DPTR/Flags
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define register offset=0xf0043F00 size=4 [ R0 R1 R2 R3 R4 R5 R6 R7 ];
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@define CPPN "R6[24,8]"
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@define SRPN "R6[16,8]"
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@define TOS "R6[14,2]"
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@define CNT1 "R6[0,12]"
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@define DPTR "R7[8,8]"
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@define CEN "R7[6,1]"
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@define IEN "R7[5,1]"
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@define CNZ "R7[4,1]"
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@define V "R7[3,1]"
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@define C "R7[2,1]"
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@define N "R7[1,1]"
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@define Z "R7[0,1]"
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define token pcpinstr (16)
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pcp_op0000=(0,0)
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pcp_op0001=(0,1)
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pcp_op0002=(0,2)
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ccAB=(0,3)
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ccA=(0,2)
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pcp_op0004=(0,4)
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pcp_op0005=(0,5)
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pcp_op0009=(0,9)
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pcp_op0010=(0,10)
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pcp_op0101=(1,1)
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pcp_op0202=(2,2)
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pcp_op0203=(2,3)
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pcp_op0204=(2,4)
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pcp_op0303=(3,3)
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R0305=(3,5)
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pcp_op0404=(4,4)
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pcp_op0405=(4,5)
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pcp_op0406=(4,6)
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pcp_op0505=(5,5)
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pcp_op0506=(5,6)
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R0608=(6,8)
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ccB=(6,9)
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pcp_op0707=(7,7)
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pcp_op0708=(7,8)
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pcp_op0808=(8,8)
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pcp_op0909=(9,9)
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pcp_op0910=(9,10)
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pcp_op0912=(9,12)
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pcp_op1010=(10,10)
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pcp_op1012=(10,12)
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pcp_op1111=(11,11)
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pcp_op1212=(12,12)
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addrmode=(13,15)
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;
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define token pcpinstr2 (16)
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pcp_op1631=(0,15)
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;
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attach variables [ R0305 R0608 ] [ R0 R1 R2 R3 R4 R5 R6 R7 ];
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CONDCA: "cc_UC" is PCPMode=1 & ccA=0x0 { local tmp:1 = 1; export tmp; }
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CONDCA: "cc_Z" is PCPMode=1 & ccA=0x1 { local tmp:1 = ($(Z)==1); export tmp; }
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CONDCA: "cc_NZ" is PCPMode=1 & ccA=0x2 { local tmp:1 = ($(Z)==0); export tmp; }
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CONDCA: "cc_V" is PCPMode=1 & ccA=0x3 { local tmp:1 = ($(V)==1); export tmp; }
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CONDCA: "cc_ULT" is PCPMode=1 & ccA=0x4 { local tmp:1 = ($(C)==1); export tmp; }
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CONDCA: "cc_UGT" is PCPMode=1 & ccA=0x5 { local tmp:1 = (($(C)|$(Z))==0); export tmp; }
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CONDCA: "cc_SLT" is PCPMode=1 & ccA=0x6 { local tmp:1 = (($(N)^$(V))==1); export tmp; }
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CONDCA: "cc_SGT" is PCPMode=1 & ccA=0x7 { local tmp:1 = ((($(N)^$(V))|$(Z))==0); export tmp; }
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CONDCB: "cc_UC" is PCPMode=1 & ccB=0x0 { local tmp:1 = 1; export tmp; }
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CONDCB: "cc_Z" is PCPMode=1 & ccB=0x1 { local tmp:1 = ($(Z)==1); export tmp; }
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CONDCB: "cc_NZ" is PCPMode=1 & ccB=0x2 { local tmp:1 = ($(Z)==0); export tmp; }
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CONDCB: "cc_V" is PCPMode=1 & ccB=0x3 { local tmp:1 = ($(V)==1); export tmp; }
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CONDCB: "cc_ULT" is PCPMode=1 & ccB=0x4 { local tmp:1 = ($(C)==1); export tmp; }
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CONDCB: "cc_UGT" is PCPMode=1 & ccB=0x5 { local tmp:1 = (($(C)|$(Z))==0); export tmp; }
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CONDCB: "cc_SLT" is PCPMode=1 & ccB=0x6 { local tmp:1 = (($(N)^$(V))==1); export tmp; }
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CONDCB: "cc_SGT" is PCPMode=1 & ccB=0x7 { local tmp:1 = ((($(N)^$(V))|$(Z))==0); export tmp; }
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CONDCB: "cc_N" is PCPMode=1 & ccB=0x8 { local tmp:1 = ($(N)==1); export tmp; }
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CONDCB: "cc_NN" is PCPMode=1 & ccB=0x9 { local tmp:1 = ($(N)==0); export tmp; }
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CONDCB: "cc_NV" is PCPMode=1 & ccB=0xA { local tmp:1 = ($(V)==0); export tmp; }
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CONDCB: "cc_UGE" is PCPMode=1 & ccB=0xB { local tmp:1 = ($(C)==0); export tmp; }
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CONDCB: "cc_SGE" is PCPMode=1 & ccB=0xC { local tmp:1 = (($(N)^$(V))==0); export tmp; }
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CONDCB: "cc_SLE" is PCPMode=1 & ccB=0xD { local tmp:1 = ((($(N)^$(V))|$(Z))==1); export tmp; }
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CONDCB: "cc_CNZ" is PCPMode=1 & ccB=0xE { local tmp:1 = ($(CNZ)==1); export tmp; }
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CONDCB: "cc_CNN" is PCPMode=1 & ccB=0xF { local tmp:1 = ($(CNZ)==0); export tmp; }
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#TODO
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CONDCAB: "cc_UC" is PCPMode=1 & ccAB=0x0 { local tmp:1 = 1; export tmp; }
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CONDCAB: "cc_Z" is PCPMode=1 & ccAB=0x1 { local tmp:1 = ($(Z)==1); export tmp; }
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CONDCAB: "cc_NZ" is PCPMode=1 & ccAB=0x2 { local tmp:1 = ($(Z)==0); export tmp; }
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CONDCAB: "cc_V" is PCPMode=1 & ccAB=0x3 { local tmp:1 = ($(V)==1); export tmp; }
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CONDCAB: "cc_ULT" is PCPMode=1 & ccAB=0x4 { local tmp:1 = ($(C)==1); export tmp; }
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CONDCAB: "cc_UGT" is PCPMode=1 & ccAB=0x5 { local tmp:1 = (($(C)|$(Z))==0); export tmp; }
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CONDCAB: "cc_SLT" is PCPMode=1 & ccAB=0x6 { local tmp:1 = (($(N)^$(V))==1); export tmp; }
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CONDCAB: "cc_SGT" is PCPMode=1 & ccAB=0x7 { local tmp:1 = ((($(N)^$(V))|$(Z))==0); export tmp; }
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CONDCAB: "cc_N" is PCPMode=1 & ccAB=0x8 { local tmp:1 = ($(N)==1); export tmp; }
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CONDCAB: "cc_NN" is PCPMode=1 & ccAB=0x9 { local tmp:1 = ($(N)==0); export tmp; }
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CONDCAB: "cc_NV" is PCPMode=1 & ccAB=0xA { local tmp:1 = ($(V)==0); export tmp; }
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CONDCAB: "cc_UGE" is PCPMode=1 & ccAB=0xB { local tmp:1 = ($(C)==0); export tmp; }
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CONDCAB: "cc_SGE" is PCPMode=1 & ccAB=0xC { local tmp:1 = (($(N)^$(V))==0); export tmp; }
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CONDCAB: "cc_SLE" is PCPMode=1 & ccAB=0xD { local tmp:1 = ((($(N)^$(V))|$(Z))==1); export tmp; }
|
||||
CONDCAB: "cc_CNZ" is PCPMode=1 & ccAB=0xE { local tmp:1 = ($(CNZ)==1); export tmp; }
|
||||
CONDCAB: "cc_CNN" is PCPMode=1 & ccAB=0xF { local tmp:1 = ($(CNZ)==0); export tmp; }
|
||||
|
||||
imm5: "#"^pcp_op0004 is pcp_op0004 { local tmp:4 = pcp_op0004; export tmp; }
|
||||
imm6: "#"^pcp_op0005 is pcp_op0005 { local tmp:4 = pcp_op0005; export tmp; }
|
||||
#imm10: "#"^pcp_op0009 is pcp_op0009 { local tmp:4 = pcp_op0009; export tmp; }
|
||||
imm16: "#"^pcp_op1631 is pcp_op1631 { local tmp:4 = pcp_op1631; export tmp; }
|
||||
offset6: "[#"^pcp_op0005^"]" is pcp_op0005 { local tmp:4 = (zext($(DPTR)) << 6) + pcp_op0005; export *[ram]:4 tmp; }
|
||||
|
||||
offset6W: R0608, "[#"^pcp_op0005^"]" is pcp_op0005 & R0608 { local tmp:4 = (zext($(DPTR)) << 6) + pcp_op0005; *[ram]:4 tmp = R0608; }
|
||||
offset6RW: R0608, "[#"^pcp_op0005^"]" is pcp_op0005 & R0608 { local tmp:4 = R0608; local ea:4 = (zext($(DPTR)) << 6) + pcp_op0005; R0608 = *[ram]:4 ea; *[ram]:4 ea = tmp; }
|
||||
|
||||
SRC: R4 is PCPMode=1 & pcp_op0708=0 & R4 { local tmp:4 = 0; export tmp; }
|
||||
SRC: R4+ is PCPMode=1 & pcp_op0708=1 & R4 { local tmp:4 = 1; export tmp; }
|
||||
SRC: R4- is PCPMode=1 & pcp_op0708=2 & R4 { local tmp:4 = -1; export tmp; }
|
||||
|
||||
DST: R5 is PCPMode=1 & pcp_op0910=0 & R5 { local tmp:4 = 0; export tmp; }
|
||||
DST: R5+ is PCPMode=1 & pcp_op0910=1 & R5 { local tmp:4 = 1; export tmp; }
|
||||
DST: R5- is PCPMode=1 & pcp_op0910=2 & R5 { local tmp:4 = -1; export tmp; }
|
||||
|
||||
SIZE0: "8" is PCPMode=1 & pcp_op0001=0 { local tmp:4 = zext(*[ram]:1 R4); export tmp;}
|
||||
SIZE0: "16" is PCPMode=1 & pcp_op0001=1 { local tmp:4 = zext(*[ram]:2 R4); export tmp;}
|
||||
SIZE0: "32" is PCPMode=1 & pcp_op0001=2 { local tmp:4 = *[ram]:4 R4; export tmp;}
|
||||
|
||||
SIZE1: [R0305], "8" is PCPMode=1 & pcp_op0001=0 & R0305 { local tmp:4 = zext(*[ram]:1 R0305); export tmp;}
|
||||
SIZE1: [R0305], "16" is PCPMode=1 & pcp_op0001=1 & R0305 { local tmp:4 = zext(*[ram]:2 R0305); export tmp;}
|
||||
SIZE1: [R0305], "32" is PCPMode=1 & pcp_op0001=2 & R0305 { local tmp:4 = *[ram]:4 R0305; export tmp;}
|
||||
|
||||
SIZE1W: R0608, [R0305], "8" is PCPMode=1 & pcp_op0001=0 & R0305 & R0608 { *[ram]:1 R0305 = R0608[0,8]; }
|
||||
SIZE1W: R0608, [R0305], "16" is PCPMode=1 & pcp_op0001=1 & R0305 & R0608 { *[ram]:2 R0305 = R0608[0,16]; }
|
||||
SIZE1W: R0608, [R0305], "32" is PCPMode=1 & pcp_op0001=2 & R0305 & R0608 { *[ram]:4 R0305 = R0608; }
|
||||
|
||||
SIZE1RW: R0608, [R0305], "8" is PCPMode=1 & pcp_op0001=0 & R0305 & R0608 { local tmp:1 = R0608[0,8]; R0608 = zext(*[ram]:1 R0305); *[ram]:1 R0305 = tmp; }
|
||||
SIZE1RW: R0608, [R0305], "16" is PCPMode=1 & pcp_op0001=1 & R0305 & R0608 { local tmp:2 = R0608[0,16]; R0608 = zext(*[ram]:2 R0305); *[ram]:2 R0305 = tmp; }
|
||||
SIZE1RW: R0608, [R0305], "32" is PCPMode=1 & pcp_op0001=2 & R0305 & R0608 { local tmp:4 = R0608; R0608 = *[ram]:4 R0305; *[ram]:4 R0305 = tmp; }
|
||||
|
||||
SIZE5: "8" is PCPMode=1 & pcp_op0505=0 & pcp_op0909=0 & R0608 { local tmp:4 = zext(*[ram]:1 R0608); export tmp;}
|
||||
SIZE5: "16" is PCPMode=1 & pcp_op0505=1 & pcp_op0909=0 & R0608 { local tmp:4 = zext(*[ram]:2 R0608); export tmp;}
|
||||
SIZE5: "32" is PCPMode=1 & pcp_op0505=0 & pcp_op0909=1 & R0608 { local tmp:4 = *[ram]:4 R0608; export tmp;}
|
||||
|
||||
SIZE5W: [R0608], imm5, "8" is PCPMode=1 & pcp_op0505=0 & pcp_op0909=0 & imm5 & R0608 { *[ram]:1 (R0608 + imm5) = R0[0,8]; }
|
||||
SIZE5W: [R0608], imm5, "16" is PCPMode=1 & pcp_op0505=1 & pcp_op0909=0 & imm5 & R0608 { *[ram]:2 (R0608 + imm5) = R0[0,16]; }
|
||||
SIZE5W: [R0608], imm5, "32" is PCPMode=1 & pcp_op0505=0 & pcp_op0909=1 & imm5 & R0608 { *[ram]:4 (R0608 + imm5) = R0; }
|
||||
|
||||
# Counter Control
|
||||
# 00 = perform xfer by CNT0 ; goto next
|
||||
# 01 = perform xfer by CNT0 ; dec CNT1 ; goto next
|
||||
# 10 = perform xfer by CNT0 ; dec CNT1 ; repeat dec ; goto next
|
||||
CNC: pcp_op0506 is PCPMode=1 & pcp_op0506 { local tmp:4 = pcp_op0506; export tmp; }
|
||||
|
||||
# Counter Reload Value (COPY)
|
||||
# 001..111 = perform 1..7 xfer
|
||||
CNT03: pcp_op0204 is PCPMode=1 & pcp_op0204 { local tmp:4 = pcp_op0204; export tmp; }
|
||||
|
||||
# Counter Reload Value Block Size (BCOPY)
|
||||
# 00 = block size 8 words
|
||||
# 10 = block size 2 words
|
||||
# 11 = block size 4 words
|
||||
CNT02: pcp_op0203 is PCPMode=1 & pcp_op0203 { local tmp:4 = pcp_op0203; export tmp; }
|
||||
|
||||
EC: pcp_op0707 is PCPMode=1 & pcp_op0707 { local tmp:1 = pcp_op0707; export tmp; }
|
||||
EP: pcp_op0808 is PCPMode=1 & pcp_op0808 { local tmp:1 = pcp_op0808; export tmp; }
|
||||
INT: pcp_op0909 is PCPMode=1 & pcp_op0909 { local tmp:1 = pcp_op0909; export tmp; }
|
||||
ST: pcp_op1010 is PCPMode=1 & pcp_op1010 { local tmp:1 = pcp_op1010; export tmp; }
|
||||
|
||||
SETCLR: "SET" is PCPMode=1 & pcp_op0505=1 { local tmp:1 = 1; export tmp; }
|
||||
SETCLR: "CLR" is PCPMode=1 & pcp_op0505=0 { local tmp:1 = 0; export tmp; }
|
||||
|
||||
SDB: pcp_op0000 is PCPMode=1 & pcp_op0000 { local tmp:1 = pcp_op0000; export tmp; }
|
||||
EDA: pcp_op0101 is PCPMode=1 & pcp_op0101 { local tmp:1 = pcp_op0101; export tmp; }
|
||||
RTA: pcp_op0202 is PCPMode=1 & pcp_op0202 { local tmp:1 = pcp_op0202; export tmp; }
|
||||
DAC: pcp_op0303 is PCPMode=1 & pcp_op0303 { local tmp:1 = pcp_op0303; export tmp; }
|
||||
|
||||
# Addressing Modes:
|
||||
# 0 - control
|
||||
# 1 - FPI
|
||||
# 2 - PRAM
|
||||
# 3 - Arithmetic
|
||||
# 4 - Immediate
|
||||
# 5 - FPI Immediate
|
||||
# 6 - Complex Maths
|
||||
# 7 - Jump
|
||||
|
||||
|
||||
# 3: 16-bit 6000|0b110000000000000 9e00|0b1001111000000000
|
||||
# ADD Rb, Ra, cc_A
|
||||
:add R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x0 & R0608 & R0305 & CONDCA
|
||||
{
|
||||
#TODO flags N,Z,V,C
|
||||
if (CONDCA == 0) goto inst_next;
|
||||
R0608 = R0608 + R0305;
|
||||
}
|
||||
|
||||
|
||||
# 1: 16-bit 2000|0b10000000000000 de04|0b1101111000000100
|
||||
# ADD.F Rb, [Ra], Size
|
||||
:add.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x0 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1
|
||||
{
|
||||
#TODO flags N,Z,V,C
|
||||
build SIZE1;
|
||||
R0608 = R0608 + SIZE1;
|
||||
}
|
||||
|
||||
|
||||
# 4: 16-bit 8000|0b1000000000000000 7e00|0b111111000000000
|
||||
# ADD.I Ra, #imm6
|
||||
:add.i R0608, imm6 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x0 & imm6
|
||||
{
|
||||
#TODO flags N,Z,V,C
|
||||
R0608 = R0608 + imm6;
|
||||
}
|
||||
|
||||
|
||||
# 2: 16-bit 4000|0b100000000000000 be00|0b1011111000000000
|
||||
# ADD.PI Ra, [#offset6]
|
||||
:add.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x0 & R0608 & offset6
|
||||
{
|
||||
#TODO flags N,Z,V,C
|
||||
build offset6;
|
||||
R0608 = R0608 + offset6;
|
||||
}
|
||||
|
||||
|
||||
# 3: 16-bit 6a00|0b110101000000000 9400|0b1001010000000000
|
||||
# AND Rb, Ra, cc_A
|
||||
:and R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x5 & R0608 & R0305 & CONDCA
|
||||
{
|
||||
#TODO flags N,Z
|
||||
if (CONDCA == 0) goto inst_next;
|
||||
R0608 = R0608 & R0305;
|
||||
}
|
||||
|
||||
|
||||
# 1: 16-bit 2a00|0b10101000000000 d404|0b1101010000000100
|
||||
# AND.F Rb, [Ra], Size
|
||||
:and.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x5 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1
|
||||
{
|
||||
#TODO flags N,Z
|
||||
build SIZE1;
|
||||
R0608 = R0608 & SIZE1;
|
||||
}
|
||||
|
||||
|
||||
# 2: 16-bit 4a00|0b100101000000000 b400|0b1011010000000000
|
||||
# AND.PI Ra, [#offset6]
|
||||
:and.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x5 & R0608 & offset6
|
||||
{
|
||||
#TODO flags N,Z
|
||||
build offset6;
|
||||
R0608 = R0608 & offset6;
|
||||
}
|
||||
|
||||
|
||||
# 0: 16-bit 1800|0b1100000000000 e013|0b1110000000010011
|
||||
#
|
||||
:bcopy DST, SRC, CNC, CNT02 is PCPMode=1 & addrmode=0 & pcp_op1212=0x1 & pcp_op1111=0x1 & DST & SRC & CNC & CNT02 & pcp_op0404=0x0 & pcp_op0001=0x0
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
# 4: 16-bit 9c00|0b1001110000000000 6200|0b110001000000000
|
||||
# CHKB Ra, #imm5, S/C
|
||||
:chkb R0608, imm5, SETCLR is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xe & SETCLR & imm5
|
||||
{
|
||||
$(C) = (R0608 & (1 << imm5)) != 0;
|
||||
}
|
||||
|
||||
|
||||
# 4: 16-bit 9600|0b1001011000000000 6820|0b110100000100000
|
||||
# CLR Ra, #imm5
|
||||
:clr R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xb & pcp_op0505=0x0 & imm5
|
||||
{
|
||||
R0608 = R0608 & ~(1 << imm5);
|
||||
}
|
||||
|
||||
|
||||
# 5: 16-bit b000|0b1011000000000000 4c00|0b100110000000000
|
||||
# CLR.F [Ra], #imm5, Size
|
||||
:clr.f [R0608], imm5, SIZE5 is PCPMode=1 & addrmode=0x5 & pcp_op1012=0x4 & R0608 & imm5 & SIZE5
|
||||
{
|
||||
build SIZE5;
|
||||
*[ram]:4 R0608 = SIZE5 & ~(1 << imm5);
|
||||
}
|
||||
|
||||
|
||||
#TODO the manual does not specify
|
||||
# N negative
|
||||
# Z zero
|
||||
# V overflow
|
||||
# C carry
|
||||
macro Flags(r0, r1) {
|
||||
local val:4 = r0 - r1;
|
||||
$(N) = val s< 0;
|
||||
$(Z) = r0 == r1;
|
||||
$(V) = r0[31,1] | r1[31,1];
|
||||
$(C) = r0 < r1;
|
||||
}
|
||||
|
||||
# 3: 16-bit 6400|0b110010000000000 9a00|0b1001101000000000
|
||||
# COMP Rb, Ra, cc_A
|
||||
:comp R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x2 & R0608 & R0305 & CONDCA
|
||||
{
|
||||
if (CONDCA == 0) goto inst_next;
|
||||
Flags(R0608, R0305);
|
||||
}
|
||||
|
||||
|
||||
# 1: 16-bit 2400|0b10010000000000 da04|0b1101101000000100
|
||||
# COMP.F Rb, [Ra], Size
|
||||
:comp.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x2 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1
|
||||
{
|
||||
build SIZE1;
|
||||
Flags(R0608, SIZE1);
|
||||
}
|
||||
|
||||
|
||||
# 4: 16-bit 8400|0b1000010000000000 7a00|0b111101000000000
|
||||
# COMP.I Ra, #imm6
|
||||
:comp.i R0608, imm6 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x2 & imm6
|
||||
{
|
||||
Flags(R0608, imm6);
|
||||
}
|
||||
|
||||
|
||||
# 2: 16-bit 4400|0b100010000000000 ba00|0b1011101000000000
|
||||
# COMP.PI Ra, [#offset6]
|
||||
:comp.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x2 & R0608 & offset6
|
||||
{
|
||||
build offset6;
|
||||
Flags(R0608, offset6);
|
||||
}
|
||||
|
||||
|
||||
# 0: 16-bit 0800|0b100000000000 f000|0b1111000000000000
|
||||
#
|
||||
:copy DST, SRC, CNC, CNT03, SIZE0 is PCPMode=1 & addrmode=0 & pcp_op1212=0x0 & pcp_op1111=0x1 & DST & SRC & CNC & CNT03 & SIZE0
|
||||
{
|
||||
}
|
||||
|
||||
#TODO DEBUG SLEIGH instead
|
||||
define pcodeop pcpdebug;
|
||||
|
||||
# 7: 16-bit fc00|0b1111110000000000 0030|0b110000
|
||||
# DEBUG EDA, DAC, RTA, SDB, cc_B
|
||||
:debug DAC, RTA, EDA, SDB, CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x7 & DAC & RTA & EDA & SDB & CONDCB & pcp_op0405=0x0
|
||||
{
|
||||
if (CONDCB == 0) goto inst_next;
|
||||
pcpdebug();
|
||||
}
|
||||
|
||||
|
||||
# 6: 16-bit c000|0b1100000000000000 3e07|0b11111000000111
|
||||
# DINIT <R0>, Rb, Ra
|
||||
:dinit "<"^R0^">", R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x0 & R0 & R0608 & R0305 & pcp_op0002=0x0
|
||||
{
|
||||
R0 = 0;
|
||||
$(V) = R0305 == 0;
|
||||
$(Z) = (R0608 == 0) && (R0305 != 0);
|
||||
}
|
||||
|
||||
|
||||
# 6: 16-bit c200|0b1100001000000000 3c07|0b11110000000111
|
||||
# DSTEP <R0>, Rb, Ra
|
||||
:dstep "<"^R0^">", R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x1 & R0 & R0608 & R0305 & pcp_op0002=0x0
|
||||
{
|
||||
#TODO flags Z not sure
|
||||
R0 = (R0 << 8) + (R0608 >> 24);
|
||||
R0608 = (R0608 << 8) + (R0 / R0305);
|
||||
R0 = R0 % R0305;
|
||||
$(Z) = R0 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 0: 16-bit 1000|0b1000000000000 e870|0b1110100001110000
|
||||
#
|
||||
:exit ST, EC, INT, EP, CONDCAB is PCPMode=1 & addrmode=0 & pcp_op1212=0x1 & pcp_op1111=0x0 & ST & EC & INT & EP & CONDCAB & pcp_op0406=0x0
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
# 3: 16-bit 7a00|0b111101000000000 8400|0b1000010000000000
|
||||
# INB Rb, Ra, cc_A
|
||||
:inb R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0xd & R0608 & R0305 & CONDCA
|
||||
{
|
||||
if (CONDCA == 0) goto inst_next;
|
||||
R0608 = (R0608 & ~(1 << R0305[0,5])) | zext($(C) << R0305[0,5]);
|
||||
}
|
||||
|
||||
|
||||
# 4: 16-bit 9a00|0b1001101000000000 6420|0b110010000100000
|
||||
# INB.I Ra, #imm5
|
||||
:inb.i R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xd & pcp_op0505=0x0 & imm5
|
||||
{
|
||||
R0608 = (R0608 & ~(1 << imm5)) | zext($(C) << imm5);
|
||||
}
|
||||
|
||||
imm6pc: reloc is PCPMode=1 & pcp_op0005 [ reloc = inst_start + pcp_op0005; ] { export *[ram]:4 reloc; }
|
||||
imm10pc: reloc is PCPMode=1 & pcp_op0009 [ reloc = inst_start + pcp_op0009; ] { export *[ram]:4 reloc; }
|
||||
imm16abs: pcp_op1631 is PCPMode=1 & pcp_op1631 { export *[ram]:4 pcp_op1631; }
|
||||
|
||||
# 7: 16-bit e400|0b1110010000000000 1800|0b1100000000000
|
||||
# JC offset6, cc_B
|
||||
:jc imm6pc, CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x1 & imm6pc & CONDCB
|
||||
{
|
||||
if (CONDCB == 0) goto inst_next;
|
||||
goto imm6pc;
|
||||
}
|
||||
|
||||
|
||||
# 7: 32-bit e800|0b1110100000000000 143f|0b1010000111111
|
||||
# JC.A #address16, cc_B
|
||||
:jc.a imm16abs, CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x2 & CONDCB & pcp_op0005=0 ; imm16abs
|
||||
{
|
||||
if (CONDCB == 0) goto inst_next;
|
||||
goto imm16abs;
|
||||
}
|
||||
|
||||
|
||||
# 7: 16-bit f000|0b1111000000000000 0c07|0b110000000111
|
||||
# JC.I Ra, cc_B
|
||||
:jc.i [R0305], CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x4 & R0305 & CONDCB & pcp_op0002=0x0
|
||||
{
|
||||
if (CONDCB == 0) goto inst_next;
|
||||
local tmp:4 = inst_start + zext(R0305[0,16]);
|
||||
goto [tmp];
|
||||
}
|
||||
|
||||
|
||||
# 7: 16-bit f400|0b1111010000000000 0807|0b100000000111
|
||||
# JC.IA Ra, cc_B
|
||||
:jc.ia [R0305], CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x5 & R0305 & CONDCB & pcp_op0002=0x0
|
||||
{
|
||||
if (CONDCB == 0) goto inst_next;
|
||||
local tmp:4 = zext(R0305[0,16]);
|
||||
goto [tmp];
|
||||
}
|
||||
|
||||
|
||||
# 7: 16-bit e000|0b1110000000000000 1c00|0b1110000000000
|
||||
# JL offset10
|
||||
:jl imm10pc is PCPMode=1 & addrmode=7 & pcp_op1012=0x0 & imm10pc
|
||||
{
|
||||
goto imm10pc;
|
||||
}
|
||||
|
||||
|
||||
# 1: 16-bit 3200|0b11001000000000 cc04|0b1100110000000100
|
||||
# LD.F Rb, [Ra], Size
|
||||
:ld.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x9 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1
|
||||
{
|
||||
R0608 = SIZE1;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 4: 16-bit 9800|0b1001100000000000 6600|0b110011000000000
|
||||
# LD.I Ra, #imm6
|
||||
:ld.i R0608, imm6 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xc & imm6
|
||||
{
|
||||
R0608 = imm6;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 5: 16-bit b400|0b1011010000000000 4800|0b100100000000000
|
||||
# LD.IF [Ra], #offset5, Size
|
||||
:ld.if [R0608], imm5, SIZE5 is PCPMode=1 & addrmode=0x5 & pcp_op1012=0x5 & R0608 & imm5 & SIZE5
|
||||
{
|
||||
R0608 = SIZE5 + imm5;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 3: 16-bit 7200|0b111001000000000 8c00|0b1000110000000000
|
||||
# LD.P Rb, [Ra], cc_A
|
||||
:ld.p R0608, [R0305], CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x9 & R0608 & R0305 & CONDCA
|
||||
{
|
||||
if (CONDCA == 0) goto inst_next;
|
||||
local tmp:4 = zext($(DPTR) << 6) + zext(R0305[0,6]);
|
||||
R0608 = *[ram]:4 tmp;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 2: 16-bit 5200|0b101001000000000 ac00|0b1010110000000000
|
||||
# LD.PI Ra, [#offset6]
|
||||
:ld.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x9 & R0608 & offset6
|
||||
{
|
||||
R0608 = offset6;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 4: 32-bit 9200|0b1001001000000000 6c3f|0b110110000111111
|
||||
# LDL.IL Ra, #imm16
|
||||
:ldl.il R0608, imm16 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x9 & pcp_op0005=0x0 ; imm16
|
||||
{
|
||||
#TODO are flags correct
|
||||
R0608[0,16] = imm16[0,16];
|
||||
$(N) = R0608[0,16] s< 0;
|
||||
$(Z) = R0608[0,16] == 0;
|
||||
}
|
||||
|
||||
|
||||
# 4: 32-bit 9000|0b1001000000000000 6e3f|0b110111000111111
|
||||
#
|
||||
:ldl.iu R0608, imm16 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x8 & pcp_op0005=0x0 ; imm16
|
||||
{
|
||||
#TODO are flags correct
|
||||
R0608[16,16] = imm16[0,16];
|
||||
$(N) = R0608[16,16] s< 0;
|
||||
$(Z) = R0608[16,16] == 0;
|
||||
}
|
||||
|
||||
|
||||
# 2: 16-bit 4800|0b100100000000000 b600|0b1011011000000000
|
||||
# MCLR.PI Ra, [#offset6]
|
||||
:mclr.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0005 & pcp_op0912=0x4 & R0608 & offset6
|
||||
{
|
||||
R0608 = R0608 & offset6;
|
||||
local tmp:4 = zext($(DPTR) << 6) + pcp_op0005;
|
||||
*[ram]:4 tmp = R0608;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 6: 16-bit c400|0b1100010000000000 3a07|0b11101000000111
|
||||
# MINIT <R0>, Rb, Ra
|
||||
:minit "<"^R0^">", R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x2 & R0 & R0608 & R0305 & pcp_op0002=0x0
|
||||
{
|
||||
R0 = 0;
|
||||
$(Z) = (R0608 == 0) || (R0305 == 0);
|
||||
}
|
||||
|
||||
|
||||
# 3: 16-bit 7800|0b111100000000000 8600|0b1000011000000000
|
||||
# MOV Rb, Ra, cc_A
|
||||
:mov R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0xc & R0608 & R0305 & CONDCA
|
||||
{
|
||||
if (CONDCA == 0) goto inst_next;
|
||||
R0608 = R0305;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 2: 16-bit 4c00|0b100110000000000 b200|0b1011001000000000
|
||||
# MSET.PI Ra, [#offset6]
|
||||
:mset.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0005 & pcp_op0912=0x6 & R0608 & offset6
|
||||
{
|
||||
R0608 = R0608 | offset6;
|
||||
local tmp:4 = zext($(DPTR) << 6) + pcp_op0005;
|
||||
*[ram]:4 tmp = R0608;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 6: 16-bit c600|0b1100011000000000 3807|0b11100000000111
|
||||
#
|
||||
:mstep.l R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x3 & R0608 & R0305 & pcp_op0002=0x0
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
# 6: 16-bit c800|0b1100100000000000 3607|0b11011000000111
|
||||
#
|
||||
:mstep.u R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x4 & R0608 & R0305 & pcp_op0002=0x0
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
# 3: 16-bit 6600|0b110011000000000 9800|0b1001100000000000
|
||||
# NEG Rb, Ra, cc_A
|
||||
:neg R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x3 & R0608 & R0305 & CONDCA
|
||||
{
|
||||
#TODO flags
|
||||
if (CONDCA == 0) goto inst_next;
|
||||
R0608 = -R0305;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
$(V) = R0608[31,1];
|
||||
$(C) = R0305[31,1];
|
||||
}
|
||||
|
||||
|
||||
# 0: 16-bit 0000|0b0 ffff|0b1111111111111111
|
||||
# NOP
|
||||
:nop is PCPMode=1 & addrmode=0 & pcp_op1212=0x0 & pcp_op1111=0x0 & pcp_op0010=0x0
|
||||
{
|
||||
local NOP:1 = 0;
|
||||
NOP = NOP;
|
||||
}
|
||||
|
||||
|
||||
# 3: 16-bit 6800|0b110100000000000 9600|0b1001011000000000
|
||||
# NOT Rb, Ra, cc_A
|
||||
:not R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x4 & R0608 & R0305 & CONDCA
|
||||
{
|
||||
if (CONDCA == 0) goto inst_next;
|
||||
R0608 = ~R0305;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 3: 16-bit 6e00|0b110111000000000 9000|0b1001000000000000
|
||||
# OR Rb, Ra, cc_A
|
||||
:or R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x7 & R0608 & R0305 & CONDCA
|
||||
{
|
||||
if (CONDCA == 0) goto inst_next;
|
||||
R0608 = R0608 | R0305;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 1: 16-bit 2e00|0b10111000000000 d004|0b1101000000000100
|
||||
# OR.F Rb, [Ra], Size
|
||||
:or.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x7 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1
|
||||
{
|
||||
R0608 = R0608 | SIZE1;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 2: 16-bit 4e00|0b100111000000000 b000|0b1011000000000000
|
||||
# OR.PI Ra, [#offset6]
|
||||
:or.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x7 & R0608 & offset6
|
||||
{
|
||||
R0608 = R0608 | offset6;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 3: 16-bit 7c00|0b111110000000000 8200|0b1000001000000000
|
||||
# PRI Rb, Ra, cc_A
|
||||
:pri R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0xe & R0608 & R0305 & CONDCA
|
||||
{
|
||||
#TODO pcodeop or this? also double check
|
||||
if (CONDCA == 0) goto inst_next;
|
||||
local index:4 = 0;
|
||||
local tmp:4 = R0305;
|
||||
if (tmp == 0) goto <LOOP_END>;
|
||||
<LOOP_START>
|
||||
tmp = tmp >> 2;
|
||||
index = index + 1;
|
||||
if (tmp != 0) goto <LOOP_START>;
|
||||
<LOOP_END>
|
||||
R0608 = zext(0x20 * (index == 0)) + (index * zext(index != 0));
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 4: 16-bit 8e00|0b1000111000000000 7020|0b111000000100000
|
||||
# RL Ra, #imm5
|
||||
:rl R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x7 & pcp_op0505=0x0 & imm5
|
||||
{
|
||||
#TODO double check
|
||||
local tmp:4 = R0608;
|
||||
R0608 = R0608 << imm5;
|
||||
$(C) = (tmp & (1 << (32 - imm5))) != 0;
|
||||
tmp = tmp >> (32 - imm5);
|
||||
R0608 = tmp | R0608;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 4: 16-bit 8c00|0b1000110000000000 7220|0b111001000100000
|
||||
# RR Ra, #imm5
|
||||
:rr R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x6 & pcp_op0505=0x0 & imm5
|
||||
{
|
||||
#TODO double check
|
||||
local tmp:4 = R0608;
|
||||
R0608 = R0608 >> imm5;
|
||||
tmp = tmp << (32 - imm5);
|
||||
R0608 = tmp | R0608;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 4: 16-bit 9400|0b1001010000000000 6a20|0b110101000100000
|
||||
# SET Ra, #imm5
|
||||
:set R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xa & pcp_op0505=0x0 & imm5
|
||||
{
|
||||
R0608 = R0608 | (1 << imm5);
|
||||
}
|
||||
|
||||
|
||||
# 5: 16-bit ac00|0b1010110000000000 5000|0b101000000000000
|
||||
# SET.F [Ra], #imm5, Size
|
||||
:set.f [R0608], imm5, SIZE5 is PCPMode=1 & addrmode=0x5 & pcp_op1012=0x3 & R0608 & imm5 & SIZE5
|
||||
{
|
||||
build SIZE5;
|
||||
*[ram]:4 R0608 = SIZE5 | (1 << imm5);
|
||||
}
|
||||
|
||||
|
||||
# 4: 16-bit 8a00|0b1000101000000000 7420|0b111010000100000
|
||||
# SHL Ra, #imm5
|
||||
:shl R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x5 & pcp_op0505=0x0 & imm5
|
||||
{
|
||||
$(C) = (R0608 & (1 << (32 - imm5))) != 0;
|
||||
R0608 = R0608 << imm5;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 4: 16-bit 8800|0b1000100000000000 7620|0b111011000100000
|
||||
# SHR Ra, #imm5
|
||||
:shr R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x4 & pcp_op0505=0x0 & imm5
|
||||
{
|
||||
R0608 = R0608 >> imm5;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 1: 16-bit 3400|0b11010000000000 ca04|0b1100101000000100
|
||||
# ST.F Rb, [Ra], Size
|
||||
:st.f SIZE1W is PCPMode=1 & addrmode=0x1 & pcp_op0912=0xa & pcp_op0202=0x0 & SIZE1W
|
||||
{
|
||||
build SIZE1W;
|
||||
}
|
||||
|
||||
|
||||
# 5: 16-bit b800|0b1011100000000000 4400|0b100010000000000
|
||||
# ST.IF [Ra], #offset5, Size
|
||||
:st.if SIZE5W is PCPMode=1 & addrmode=0x5 & pcp_op1012=0x6 & SIZE5W
|
||||
{
|
||||
build SIZE5W;
|
||||
}
|
||||
|
||||
|
||||
# 3: 16-bit 7400|0b111010000000000 8a00|0b1000101000000000
|
||||
# ST.P Rb, [Ra], cc_A
|
||||
:st.p R0608, [R0305], CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0xa & R0608 & R0305 & CONDCA
|
||||
{
|
||||
if (CONDCA == 0) goto inst_next;
|
||||
local tmp:4 = zext($(DPTR) << 6) + zext(R0305[0,6]);
|
||||
*[ram]:4 tmp = R0608;
|
||||
}
|
||||
|
||||
|
||||
# 2: 16-bit 5400|0b101010000000000 aa00|0b1010101000000000
|
||||
# ST.PI Rb, [#offset6]
|
||||
:st.pi offset6W is PCPMode=1 & addrmode=2 & pcp_op0912=0xa & offset6W
|
||||
{
|
||||
build offset6W;
|
||||
}
|
||||
|
||||
|
||||
# 3: 16-bit 6200|0b110001000000000 9c00|0b1001110000000000
|
||||
# SUB Rb, Ra, cc_A
|
||||
:sub R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x1 & R0608 & R0305 & CONDCA
|
||||
{
|
||||
if (CONDCA == 0) goto inst_next;
|
||||
R0608 = R0608 - R0305;
|
||||
Flags(R0608, R0305);
|
||||
}
|
||||
|
||||
|
||||
# 1: 16-bit 2200|0b10001000000000 dc04|0b1101110000000100
|
||||
# SUB.F Rb, [Ra], Size
|
||||
:sub.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x1 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1
|
||||
{
|
||||
build SIZE1;
|
||||
local tmp:4 = SIZE1;
|
||||
Flags(R0608, tmp);
|
||||
R0608 = R0608 - tmp;
|
||||
}
|
||||
|
||||
|
||||
# 4: 16-bit 8200|0b1000001000000000 7c00|0b111110000000000
|
||||
# SUB.I Ra, #imm6
|
||||
:sub.i R0608, imm6 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x1 & imm6
|
||||
{
|
||||
Flags(R0608, imm6);
|
||||
R0608 = R0608 - imm6;
|
||||
}
|
||||
|
||||
|
||||
# 2: 16-bit 4200|0b100001000000000 bc00|0b1011110000000000
|
||||
# SUB.PI Ra, [#offset6]
|
||||
:sub.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x1 & R0608 & offset6
|
||||
{
|
||||
Flags(R0608, offset6);
|
||||
R0608 = R0608 - offset6;
|
||||
}
|
||||
|
||||
|
||||
# 1: 16-bit 3600|0b11011000000000 c804|0b1100100000000100
|
||||
# XCH.F Rb, [Ra], Size
|
||||
:xch.f SIZE1RW is PCPMode=1 & addrmode=0x1 & pcp_op0912=0xb & pcp_op0202=0x0 & R0608 & SIZE1RW
|
||||
{
|
||||
build SIZE1RW;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 2: 16-bit 5600|0b101011000000000 a800|0b1010100000000000
|
||||
# XCH.PI Ra, [#offset6]
|
||||
:xch.pi offset6RW is PCPMode=1 & addrmode=2 & pcp_op0912=0xb & R0608 & offset6RW
|
||||
{
|
||||
build offset6RW;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 3: 16-bit 7000|0b111000000000000 8e00|0b1000111000000000
|
||||
# XOR Rb, Ra, cc_A
|
||||
:xor R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x8 & R0608 & R0305 & CONDCA
|
||||
{
|
||||
if (CONDCA == 0) goto inst_next;
|
||||
R0608 = R0608 ^ R0305;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 1: 16-bit 3000|0b11000000000000 ce04|0b1100111000000100
|
||||
# XOR.F Rb, [Ra], Size
|
||||
:xor.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x8 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1
|
||||
{
|
||||
R0608 = R0608 ^ SIZE1;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
|
||||
|
||||
# 2: 16-bit 5000|0b101000000000000 ae00|0b1010111000000000
|
||||
# XOR.PI Ra, [#offset6]
|
||||
:xor.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x8 & R0608 & offset6
|
||||
{
|
||||
R0608 = R0608 ^ offset6;
|
||||
$(N) = R0608 s< 0;
|
||||
$(Z) = R0608 == 0;
|
||||
}
|
||||
8
Ghidra/Processors/tricore/data/languages/tricore.pspec
Normal file
8
Ghidra/Processors/tricore/data/languages/tricore.pspec
Normal file
@ -0,0 +1,8 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<processor_spec>
|
||||
<programcounter register="PC"/>
|
||||
<volatile outputop="write" inputop="read">
|
||||
<range space="ram" first="0x0" last="0x20"/>
|
||||
</volatile>
|
||||
</processor_spec>
|
||||
8508
Ghidra/Processors/tricore/data/languages/tricore.sinc
Normal file
8508
Ghidra/Processors/tricore/data/languages/tricore.sinc
Normal file
File diff suppressed because it is too large
Load Diff
13
Ghidra/Processors/tricore/data/languages/tricore.slaspec
Normal file
13
Ghidra/Processors/tricore/data/languages/tricore.slaspec
Normal file
@ -0,0 +1,13 @@
|
||||
@define Tricore ""
|
||||
|
||||
@define TRICORE_GENERIC ""
|
||||
#@define TRICORE_RIDER_D ""
|
||||
#@define TRICORE_RIDER_B ""
|
||||
|
||||
@define TRICORE_V2 ""
|
||||
|
||||
#@define TRICORE_VERBOSE ""
|
||||
|
||||
define endian=little;
|
||||
|
||||
@include "tricore.sinc"
|
||||
337
Ghidra/Processors/tricore/data/manuals/tricore.idx
Normal file
337
Ghidra/Processors/tricore/data/manuals/tricore.idx
Normal file
@ -0,0 +1,337 @@
|
||||
@tc_v131_instructionset_v138.pdf[TriCore Architecture Volume 2: Instruction Set, V1.3 & V1.3.1]
|
||||
ABS, 66
|
||||
ABS.B, 67
|
||||
ABSDIF, 69
|
||||
ABSDIF.B, 71
|
||||
ABSDIF.H, 71
|
||||
ABSDIFS, 73
|
||||
ABSDIFS.H, 75
|
||||
ABS.H, 67
|
||||
ABSS, 76
|
||||
ABSS.H, 77
|
||||
ADD, 78
|
||||
ADD.A, 81
|
||||
ADD.B, 83
|
||||
ADDC, 85
|
||||
ADD.F, 511
|
||||
ADD.H, 83
|
||||
ADDI, 87
|
||||
ADDIH, 88
|
||||
ADDIH.A, 89
|
||||
ADDS, 90
|
||||
ADDSC.A, 96
|
||||
ADDSC.AT, 96
|
||||
ADDS.H, 92
|
||||
ADDS.HU, 92
|
||||
ADDS.U, 94
|
||||
ADDX, 98
|
||||
AND, 100
|
||||
AND.ANDN.T, 102
|
||||
AND.AND.T, 102
|
||||
AND.EQ, 104
|
||||
AND.GE, 105
|
||||
AND.GE.U, 105
|
||||
AND.LT, 107
|
||||
AND.LT.U, 107
|
||||
ANDN, 111
|
||||
AND.NE, 109
|
||||
AND.NOR.T, 102
|
||||
ANDN.T, 112
|
||||
AND.OR.T, 102
|
||||
AND.T, 110
|
||||
BISR, 113
|
||||
BMERGE, 115
|
||||
BSPLIT, 116
|
||||
CACHEA.I, 117
|
||||
CACHEA.W, 120
|
||||
CACHEA.WI, 123
|
||||
CACHEI.W, 126
|
||||
CACHEI.WI, 128
|
||||
CADD, 130
|
||||
CADDN, 132
|
||||
CALL, 134
|
||||
CALLA, 137
|
||||
CALLI, 139
|
||||
CLO, 141
|
||||
CLO.H, 142
|
||||
CLS, 143
|
||||
CLS.H, 144
|
||||
CLZ, 145
|
||||
CLZ.H, 146
|
||||
CMOV, 147
|
||||
CMOVN, 148
|
||||
CMP.F, 513
|
||||
CSUB, 149
|
||||
CSUBN, 150
|
||||
DEBUG, 151
|
||||
DEXTR, 152
|
||||
DISABLE, 153
|
||||
DIV.F, 515
|
||||
DSYNC, 154
|
||||
DVADJ, 155
|
||||
DVINIT, 157
|
||||
DVINIT.B, 157
|
||||
DVINIT.BU, 157
|
||||
DVINIT.H, 157
|
||||
DVINIT.HU, 157
|
||||
DVINIT.U, 157
|
||||
DVSTEP, 162
|
||||
DVSTEP.U, 162
|
||||
ENABLE, 165
|
||||
EQ, 166
|
||||
EQ.A, 168
|
||||
EQANY.B, 171
|
||||
EQANY.H, 171
|
||||
EQ.B, 169
|
||||
EQ.H, 169
|
||||
EQ.W, 169
|
||||
EQZ.A, 173
|
||||
EXTR, 174
|
||||
EXTR.U, 174
|
||||
FTOI, 517
|
||||
FTOIZ, 518
|
||||
FTOQ31, 519
|
||||
FTOQ31Z, 521
|
||||
FTOU, 523
|
||||
FTOUZ, 524
|
||||
GE, 176
|
||||
GE.A, 178
|
||||
GE.U, 176
|
||||
IMASK, 179
|
||||
INSERT, 182
|
||||
INSN.T, 181
|
||||
INS.T, 181
|
||||
ISYNC, 185
|
||||
ITOF, 525
|
||||
IXMAX, 186
|
||||
IXMAX.U, 186
|
||||
IXMIN, 188
|
||||
IXMIN.U, 188
|
||||
J, 190
|
||||
JA, 191
|
||||
JEQ, 192
|
||||
JEQ.A, 194
|
||||
JGE, 195
|
||||
JGE.U, 195
|
||||
JGEZ, 197
|
||||
JGTZ, 198
|
||||
JI, 199
|
||||
JL, 200
|
||||
JLA, 201
|
||||
JLEZ, 202
|
||||
JLI, 203
|
||||
JLT, 204
|
||||
JLT.U, 204
|
||||
JLTZ, 206
|
||||
JNE, 207
|
||||
JNE.A, 209
|
||||
JNED, 210
|
||||
JNEI, 212
|
||||
JNZ, 214
|
||||
JNZ.A, 215
|
||||
JNZ.T, 216
|
||||
JZ, 217
|
||||
JZ.A, 218
|
||||
JZ.T, 219
|
||||
LD.A, 220
|
||||
LD.B, 224
|
||||
LD.BU, 224
|
||||
LD.D, 229
|
||||
LD.DA, 232
|
||||
LD.H, 235
|
||||
LD.HU, 238
|
||||
LDLCX, 246
|
||||
LDMST, 247
|
||||
LD.Q, 240
|
||||
LDUCX, 250
|
||||
LD.W, 242
|
||||
LEA, 251
|
||||
LOOP, 253
|
||||
LOOPU, 255
|
||||
LT, 256
|
||||
LT.A, 259
|
||||
LT.B, 260
|
||||
LT.BU, 260
|
||||
LT.H, 262
|
||||
LT.HU, 262
|
||||
LT.U, 256
|
||||
LT.W, 264
|
||||
LT.WU, 264
|
||||
MADD, 265
|
||||
MADD.F, 526
|
||||
MADD.H, 268
|
||||
MADDM.H, 282
|
||||
MADDMS.H, 282
|
||||
MADD.Q, 272
|
||||
MADDR.H, 286
|
||||
MADDR.Q, 291
|
||||
MADDRS.H, 286
|
||||
MADDRS.Q, 291
|
||||
MADDS, 265
|
||||
MADDS.H, 268
|
||||
MADDS.Q, 272
|
||||
MADDS.U, 279
|
||||
MADDSU.H, 293
|
||||
MADDSUM.H, 297
|
||||
MADDSUMS.H, 297
|
||||
MADDSUR.H, 301
|
||||
MADDSURS.H, 301
|
||||
MADDSUS.H, 293
|
||||
MADD.U, 279
|
||||
MAX, 306
|
||||
MAX.B, 308
|
||||
MAX.BU, 308
|
||||
MAX.H, 310
|
||||
MAX.HU, 310
|
||||
MAX.U, 306
|
||||
MFCR, 311
|
||||
MIN, 312
|
||||
MIN.B, 314
|
||||
MIN.BU, 314
|
||||
MIN.H, 316
|
||||
MIN.HU, 316
|
||||
MIN.U, 312
|
||||
MOV, 317
|
||||
MOV.A, 319
|
||||
MOV.AA, 321
|
||||
MOV.D, 322
|
||||
MOVH, 324
|
||||
MOVH.A, 325
|
||||
MOV.U, 323
|
||||
MSUB, 326
|
||||
MSUBAD.H, 343
|
||||
MSUBADM.H, 347
|
||||
MSUBADMS.H, 347
|
||||
MSUBADR.H, 351
|
||||
MSUBADRS.H, 351
|
||||
MSUBADS.H, 343
|
||||
MSUB.F, 528
|
||||
MSUB.H, 329
|
||||
MSUBM.H, 356
|
||||
MSUBMS.H, 356
|
||||
MSUB.Q, 333
|
||||
MSUBR.H, 360
|
||||
MSUBR.Q, 365
|
||||
MSUBRS.H, 360
|
||||
MSUBRS.Q, 365
|
||||
MSUBS, 326
|
||||
MSUBS.H, 329
|
||||
MSUBS.Q, 333
|
||||
MSUBS.U, 340
|
||||
MSUB.U, 340
|
||||
MTCR, 367
|
||||
MUL, 368
|
||||
MUL.F, 530
|
||||
MUL.H, 371
|
||||
MULM.H, 379
|
||||
MUL.Q, 374
|
||||
MULR.H, 382
|
||||
MULR.Q, 385
|
||||
MULS, 368
|
||||
MULS.U, 377
|
||||
MUL.U, 377
|
||||
NAND, 387
|
||||
NAND.T, 388
|
||||
NE, 389
|
||||
NE.A, 390
|
||||
NEZ.A, 391
|
||||
NOP, 392
|
||||
NOR, 393
|
||||
NOR.T, 394
|
||||
NOT, 395
|
||||
OR, 396
|
||||
OR.ANDN.T, 398
|
||||
OR.AND.T, 398
|
||||
OR.EQ, 400
|
||||
OR.GE, 401
|
||||
OR.GE.U, 401
|
||||
OR.LT, 403
|
||||
OR.LT.U, 403
|
||||
ORN, 407
|
||||
OR.NE, 405
|
||||
OR.NOR.T, 398
|
||||
ORN.T, 408
|
||||
OR.OR.T, 398
|
||||
OR.T, 406
|
||||
PACK, 409
|
||||
PARITY, 412
|
||||
Q31TOF, 532
|
||||
QSEED.F, 533
|
||||
RET, 413
|
||||
RFE, 415
|
||||
RFM, 417
|
||||
RSLCX, 419
|
||||
RSTV, 420
|
||||
RSUB, 421
|
||||
RSUBS, 423
|
||||
RSUBS.U, 423
|
||||
SAT.B, 425
|
||||
SAT.BU, 427
|
||||
SAT.H, 428
|
||||
SAT.HU, 430
|
||||
SEL, 431
|
||||
SELN, 432
|
||||
SH, 433
|
||||
SHA, 446
|
||||
SHA.H, 449
|
||||
SH.ANDN.T, 443
|
||||
SH.AND.T, 443
|
||||
SHAS, 451
|
||||
SH.EQ, 435
|
||||
SH.GE, 436
|
||||
SH.GE.U, 436
|
||||
SH.H, 438
|
||||
SH.LT, 440
|
||||
SH.LT.U, 440
|
||||
SH.NAND.T, 443
|
||||
SH.NE, 442
|
||||
SH.NOR.T, 443
|
||||
SH.ORN.T, 443
|
||||
SH.OR.T, 443
|
||||
SH.XNOR.T, 443
|
||||
SH.XOR.T, 443
|
||||
ST.A, 453
|
||||
ST.B, 457
|
||||
ST.D, 460
|
||||
ST.DA, 463
|
||||
ST.H, 466
|
||||
STLCX, 476
|
||||
ST.Q, 469
|
||||
ST.T, 471
|
||||
STUCX, 477
|
||||
ST.W, 472
|
||||
SUB, 478
|
||||
SUB.A, 480
|
||||
SUB.B, 481
|
||||
SUBC, 483
|
||||
SUB.F, 535
|
||||
SUB.H, 481
|
||||
SUBS, 484
|
||||
SUBS.H, 486
|
||||
SUBS.HU, 486
|
||||
SUBS.U, 484
|
||||
SUBX, 488
|
||||
SVLCX, 489
|
||||
SWAP.W, 491
|
||||
SYSCALL, 494
|
||||
TLBDEMAP, 541
|
||||
TLBFLUSH.A, 542
|
||||
TLBFLUSH.B, 542
|
||||
TLBMAP, 544
|
||||
TLBPROBE.A, 546
|
||||
TLBPROBE.I, 548
|
||||
TRAPSV, 495
|
||||
TRAPV, 496
|
||||
UNPACK, 497
|
||||
UPDFL, 537
|
||||
UTOF, 539
|
||||
XNOR, 499
|
||||
XNOR.T, 500
|
||||
XOR, 501
|
||||
XOR.EQ, 503
|
||||
XOR.GE, 504
|
||||
XOR.GE.U, 504
|
||||
XOR.LT, 506
|
||||
XOR.LT.U, 506
|
||||
XOR.NE, 508
|
||||
XOR.T, 509
|
||||
358
Ghidra/Processors/tricore/data/manuals/tricore2.idx
Normal file
358
Ghidra/Processors/tricore/data/manuals/tricore2.idx
Normal file
@ -0,0 +1,358 @@
|
||||
@Infineon-TC2xx_Architecture_vol2-UM-v01_00-EN.pdf[tcarch_vol2_a4.book]
|
||||
ABS, 51
|
||||
ABS.B, 52
|
||||
ABSDIF, 54
|
||||
ABSDIF.B, 55
|
||||
ABSDIF.H, 55
|
||||
ABSDIFS, 57
|
||||
ABSDIFS.H, 58
|
||||
ABS.H, 52
|
||||
ABSS, 59
|
||||
ABSS.H, 60
|
||||
ADD, 61
|
||||
ADD.A, 64
|
||||
ADD.B, 65
|
||||
ADDC, 67
|
||||
ADD.F, 461
|
||||
ADD.H, 65
|
||||
ADDI, 68
|
||||
ADDIH, 69
|
||||
ADDIH.A, 70
|
||||
ADDS, 71
|
||||
ADDSC.A, 76
|
||||
ADDSC.AT, 76
|
||||
ADDS.H, 73
|
||||
ADDS.HU, 73
|
||||
ADDS.U, 75
|
||||
ADDX, 78
|
||||
AND, 79
|
||||
AND.ANDN.T, 81
|
||||
AND.AND.T, 81
|
||||
AND.EQ, 83
|
||||
AND.GE, 84
|
||||
AND.GE.U, 84
|
||||
AND.LT, 86
|
||||
AND.LT.U, 86
|
||||
ANDN, 90
|
||||
AND.NE, 88
|
||||
AND.NOR.T, 81
|
||||
ANDN.T, 91
|
||||
AND.OR.T, 81
|
||||
AND.T, 89
|
||||
BISR, 92
|
||||
BMERGE, 94
|
||||
BSPLIT, 95
|
||||
CACHEA.I, 96
|
||||
CACHEA.W, 98
|
||||
CACHEA.WI, 100
|
||||
CACHEI.I, 104
|
||||
CACHEI.W, 102
|
||||
CACHEI.WI, 106
|
||||
CADD, 108
|
||||
CADDN, 110
|
||||
CALL, 112
|
||||
CALLA, 114
|
||||
CALLI, 116
|
||||
CLO, 118
|
||||
CLO.H, 119
|
||||
CLS, 120
|
||||
CLS.H, 121
|
||||
CLZ, 122
|
||||
CLZ.H, 123
|
||||
CMOV, 124
|
||||
CMOVN, 125
|
||||
CMP.F, 462
|
||||
CMPSWAP.W, 126
|
||||
COP, 493
|
||||
CRC32, 128
|
||||
CSUB, 129
|
||||
CSUBN, 130
|
||||
DEBUG, 131
|
||||
DEXTR, 132
|
||||
DISABLE, 133
|
||||
DIV, 137
|
||||
DIV.F, 463
|
||||
DIV.U, 137
|
||||
DSYNC, 134
|
||||
DVADJ, 135
|
||||
DVINIT, 139
|
||||
DVINIT.B, 139
|
||||
DVINIT.BU, 139
|
||||
DVINIT.H, 139
|
||||
DVINIT.HU, 139
|
||||
DVINIT.U, 139
|
||||
DVSTEP, 142
|
||||
DVSTEP.U, 142
|
||||
ENABLE, 144
|
||||
EQ, 145
|
||||
EQ.A, 147
|
||||
EQANY.B, 150
|
||||
EQANY.H, 150
|
||||
EQ.B, 148
|
||||
EQ.H, 148
|
||||
EQ.W, 148
|
||||
EQZ.A, 152
|
||||
EXTR, 153
|
||||
EXTR.U, 153
|
||||
FCALL, 155
|
||||
FCALLA, 156
|
||||
FCALLI, 157
|
||||
FRET, 158
|
||||
FTOI, 464
|
||||
FTOIZ, 465
|
||||
FTOQ31, 466
|
||||
FTOQ31Z, 467
|
||||
FTOU, 468
|
||||
FTOUZ, 469
|
||||
GE, 159
|
||||
GE.A, 161
|
||||
GE.U, 159
|
||||
IMASK, 162
|
||||
INSERT, 165
|
||||
INSN.T, 164
|
||||
INS.T, 164
|
||||
ISYNC, 167
|
||||
ITOF, 470
|
||||
IXMAX, 168
|
||||
IXMAX.U, 168
|
||||
IXMIN, 170
|
||||
IXMIN.U, 170
|
||||
J, 172
|
||||
JA, 173
|
||||
JEQ, 174
|
||||
JEQ.A, 176
|
||||
JGE, 177
|
||||
JGE.U, 177
|
||||
JGEZ, 179
|
||||
JGTZ, 180
|
||||
JI, 181
|
||||
JL, 182
|
||||
JLA, 183
|
||||
JLEZ, 184
|
||||
JLI, 185
|
||||
JLT, 186
|
||||
JLT.U, 186
|
||||
JLTZ, 188
|
||||
JNE, 189
|
||||
JNE.A, 191
|
||||
JNED, 192
|
||||
JNEI, 193
|
||||
JNZ, 194
|
||||
JNZ.A, 195
|
||||
JNZ.T, 196
|
||||
JZ, 197
|
||||
JZ.A, 198
|
||||
JZ.T, 199
|
||||
LD.A, 200
|
||||
LD.B, 203
|
||||
LD.BU, 203
|
||||
LD.D, 208
|
||||
LD.DA, 210
|
||||
LD.DD, 212
|
||||
LD.H, 214
|
||||
LD.HU, 214
|
||||
LDLCX, 224
|
||||
LDMST, 225
|
||||
LD.Q, 219
|
||||
LDUCX, 227
|
||||
LD.W, 221
|
||||
LEA, 228
|
||||
LOOP, 229
|
||||
LOOPU, 230
|
||||
LT, 231
|
||||
LT.A, 233
|
||||
LT.B, 234
|
||||
LT.BU, 234
|
||||
LT.H, 235
|
||||
LT.HU, 235
|
||||
LT.U, 231
|
||||
LT.W, 236
|
||||
LT.WU, 236
|
||||
MADD, 237
|
||||
MADD.F, 471
|
||||
MADD.H, 240
|
||||
MADDM.H, 252
|
||||
MADDMS.H, 252
|
||||
MADD.Q, 244
|
||||
MADDR.H, 255
|
||||
MADDR.Q, 259
|
||||
MADDRS.H, 255
|
||||
MADDRS.Q, 259
|
||||
MADDS, 237
|
||||
MADDS.H, 240
|
||||
MADDS.Q, 244
|
||||
MADDS.U, 250
|
||||
MADDSU.H, 261
|
||||
MADDSUM.H, 265
|
||||
MADDSUMS.H, 265
|
||||
MADDSUR.H, 268
|
||||
MADDSURS.H, 268
|
||||
MADDSUS.H, 261
|
||||
MADD.U, 250
|
||||
MAX, 272
|
||||
MAX.B, 274
|
||||
MAX.BU, 274
|
||||
MAX.H, 275
|
||||
MAX.HU, 275
|
||||
MAX.U, 272
|
||||
MFCR, 276
|
||||
MFFR, 473
|
||||
MIN, 277
|
||||
MIN.B, 279
|
||||
MIN.BU, 279
|
||||
MIN.H, 280
|
||||
MIN.HU, 280
|
||||
MIN.U, 277
|
||||
MOV, 281
|
||||
MOV.A, 284
|
||||
MOV.AA, 285
|
||||
MOV.D, 286
|
||||
MOVH, 288
|
||||
MOVH.A, 289
|
||||
MOV.U, 287
|
||||
MSUB, 290
|
||||
MSUBAD.H, 305
|
||||
MSUBADM.H, 309
|
||||
MSUBADMS.H, 309
|
||||
MSUBADR.H, 312
|
||||
MSUBADRS.H, 312
|
||||
MSUBADS.H, 305
|
||||
MSUB.F, 474
|
||||
MSUB.H, 293
|
||||
MSUBM.H, 316
|
||||
MSUBMS.H, 316
|
||||
MSUB.Q, 297
|
||||
MSUBR.H, 319
|
||||
MSUBR.Q, 323
|
||||
MSUBRS.H, 319
|
||||
MSUBRS.Q, 323
|
||||
MSUBS, 290
|
||||
MSUBS.H, 293
|
||||
MSUBS.Q, 297
|
||||
MSUBS.U, 303
|
||||
MSUB.U, 303
|
||||
MTCR, 325
|
||||
MTFR, 476
|
||||
MUL, 326
|
||||
MUL.F, 477
|
||||
MUL.H, 329
|
||||
MULM.H, 336
|
||||
MULMS.H, 338
|
||||
MUL.Q, 331
|
||||
MULR.H, 339
|
||||
MULR.Q, 341
|
||||
MULS, 326
|
||||
MULS.U, 334
|
||||
MUL.U, 334
|
||||
NAND, 342
|
||||
NAND.T, 343
|
||||
NE, 344
|
||||
NE.A, 345
|
||||
NEZ.A, 346
|
||||
NOP, 347
|
||||
NOR, 348
|
||||
NOR.T, 349
|
||||
NOT, 350
|
||||
OR, 351
|
||||
OR.ANDN.T, 353
|
||||
OR.AND.T, 353
|
||||
OR.EQ, 355
|
||||
OR.GE, 356
|
||||
OR.GE.U, 356
|
||||
OR.LT, 358
|
||||
OR.LT.U, 358
|
||||
ORN, 362
|
||||
OR.NE, 360
|
||||
OR.NOR.T, 353
|
||||
ORN.T, 363
|
||||
OR.OR.T, 353
|
||||
OR.T, 361
|
||||
PACK, 364
|
||||
PARITY, 366
|
||||
Q31TOF, 478
|
||||
QSEED.F, 479
|
||||
RESTORE, 367
|
||||
RET, 368
|
||||
RFE, 370
|
||||
RFM, 372
|
||||
RSLCX, 373
|
||||
RSTV, 374
|
||||
RSUB, 375
|
||||
RSUBS, 376
|
||||
RSUBS.U, 376
|
||||
SAT.B, 377
|
||||
SAT.BU, 378
|
||||
SAT.H, 379
|
||||
SAT.HU, 380
|
||||
SEL, 381
|
||||
SELN, 382
|
||||
SH, 383
|
||||
SHA, 394
|
||||
SHA.H, 396
|
||||
SH.ANDN.T, 392
|
||||
SH.AND.T, 392
|
||||
SHAS, 398
|
||||
SH.EQ, 385
|
||||
SH.GE, 386
|
||||
SH.GE.U, 386
|
||||
SH.H, 388
|
||||
SH.LT, 389
|
||||
SH.LT.U, 389
|
||||
SH.NAND.T, 392
|
||||
SH.NE, 391
|
||||
SH.NOR.T, 392
|
||||
SH.ORN.T, 392
|
||||
SH.OR.T, 392
|
||||
SH.XNOR.T, 392
|
||||
SH.XOR.T, 392
|
||||
ST.A, 400
|
||||
ST.B, 403
|
||||
ST.D, 406
|
||||
ST.DA, 409
|
||||
ST.DD, 411
|
||||
ST.H, 413
|
||||
STLCX, 422
|
||||
ST.Q, 416
|
||||
ST.T, 418
|
||||
STUCX, 423
|
||||
ST.W, 419
|
||||
SUB, 424
|
||||
SUB.A, 426
|
||||
SUB.B, 427
|
||||
SUBC, 429
|
||||
SUB.F, 480
|
||||
SUB.H, 427
|
||||
SUBS, 430
|
||||
SUBS.H, 432
|
||||
SUBS.HU, 432
|
||||
SUBS.U, 430
|
||||
SUBX, 434
|
||||
SVLCX, 435
|
||||
SWAPMSK.W, 439
|
||||
SWAP.W, 436
|
||||
SYSCALL, 442
|
||||
TLBDEMAP, 484
|
||||
TLBFLUSH.A, 485
|
||||
TLBFLUSH.B, 485
|
||||
TLBMAP, 486
|
||||
TLBPROBE.A, 487
|
||||
TLBPROBE.I, 489
|
||||
TRAPSV, 443
|
||||
TRAPV, 444
|
||||
UNPACK, 445
|
||||
UPDFL, 481
|
||||
UTOF, 482
|
||||
WAIT, 447
|
||||
XNOR, 448
|
||||
XNOR.T, 449
|
||||
XOR, 450
|
||||
XOR.EQ, 451
|
||||
XOR.GE, 452
|
||||
XOR.GE.U, 452
|
||||
XOR.LT, 454
|
||||
XOR.LT.U, 454
|
||||
XOR.NE, 456
|
||||
XOR.T, 457
|
||||
XPOSE.B, 458
|
||||
XPOSE.H, 458
|
||||
YIELD, 491
|
||||
Loading…
Reference in New Issue
Block a user