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'origin/GP-2014_ghidorahrex_PR-4223_agatti_68000-pack-unpk'
(Closes #4223)
This commit is contained in:
Ryan Kurtz 2022-09-16 13:26:27 -04:00
commit 79947c37f6
1 changed files with 19 additions and 2 deletions
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Ghidra/Processors/68000/data/languages/68000.sinc
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@ -1578,7 +1578,16 @@ macro negResFlags(result) {
:ori "#"^d8,"CCR" is opbig=0 & op37=7 & op02=4; d8 { packflags(SR); SR=SR|d8; unpackflags(SR); }
:ori "#"^d16,SR is SR; opbig=0x00 & d8base=0x7c; d16 { packflags(SR); SR=SR|d16; unpackflags(SR); }
:pack Tyb,Txb,"#"d16 is op=8 & op48=20 & Txb & Tyb; d16 unimpl
:pack Tyw,Txw,"#"d16 is op=8 & op48=20 & Txw & Tyw & rmbit=0; d16 {
local value = (Tyw & 0x0F0F) + d16;
Txw = (Txw & 0xFF00) | ((value & 0x0F00) >> 4) | (value & 0x000F);
}
:pack Tyw,Txb,"#"d16 is op=8 & op48=20 & Tyw & Txb & rmbit=1; d16 {
local value = (Tyw & 0x0F0F) + d16;
local result:2 = ((value & 0x0F00) >> 4) | (value & 0x000F);
Txb = result:1;
}
:pea eaptr is (opbig=0x48 & op67=1 & $(CTL_ADDR_MODES))... & eaptr { SP = SP-4; *SP = eaptr; }
@ -1807,7 +1816,15 @@ ptestLevel: "#"^mregn is mregn { export *[const]:1 mregn; }
:unlk regan is opbig=0x4e & op37=11 & regan { SP = regan; regan = *SP; SP = SP+4; }
:unpk Tyb,Txb,"#"^d16 is op=8 & Txb & op48=24 & Tyb; d16 unimpl
:unpk Tyw,Txw,"#"^d16 is op=8 & Txw & op48=24 & Tyw & rmbit=0; d16 {
Txw = (Txw & 0xF0F0) | ((((Tyw & 0x00F0) << 4) | (Tyw & 0x000F)) + d16);
}
:unpk Tyb,Txw,"#"^d16 is op=8 & Tyb & op48=24 & Txw & rmbit=1; d16 {
local source:2 = zext(Tyb);
source = (((source & 0x00F0) << 4) | (source & 0x000F)) + d16;
Txw = (Txw & 0xF0F0) | source;
}
# Floating Point Instructions