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Fixed MIPS bitpattern endian mixup

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This commit is contained in:
ghidorahrex 2021-09-17 12:03:14 -04:00
parent 0655f76e91
commit 7321e2a09a
2 changed files with 2 additions and 2 deletions
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2
Ghidra/Processors/MIPS/data/patterns/MIPS_BE_patterns.xml
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@ -7,7 +7,7 @@
<data>0x03e00008 0x........ 0x00000000 0x00000000 0x00000000 </data> <!-- RETN : delayslot filler -->
<data>0x08...... 0x27 0xbd 0....... ......00</data> <!-- J xyz : _ADDIU This is probably a shared return-->
<data>0x1000.... 0x27 0xbd 0....... ......00</data> <!-- B xyz : _ADDIU This is probably a shared return-->
<data>..001000 00000... 0x20 0x03 0x0. 0x.. 0xbd 0x27 </data> <!-- JR t9 : _ADDIU -->
<data>0x03 0x20 00000... ..001000 0x27 0xbd 0x0. 0x.. </data> <!-- JR t9 : _ADDIU -->
</prepatterns>
<postpatterns>
<data>00100111 10111101 1....... ......00</data> <!-- ADDIU SP,SP,-xxxx -->

2
Ghidra/Processors/MIPS/data/patterns/MIPS_LE_patterns.xml
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@ -7,7 +7,7 @@
<data>0x0800e003 0x........ 0x00000000 0x00000000 0x00000000 </data> <!-- RETN : delayslot filler -->
<data>0x......08 ......00 0....... 0xbd 0x27 </data> <!-- J xyz : _ADDIU This is probably a shared return-->
<data>0x....0010 ......00 0....... 0xbd 0x27</data> <!-- B xyz : _ADDIU This is probably a shared return-->
<data>0x03 0x20 00000... ..001000 0x27 0xbd 0x0. 0x.. </data> <!-- JR t9 : _ADDIU -->
<data>..001000 00000... 0x20 0x03 0x0. 0x.. 0xbd 0x27 </data> <!-- JR t9 : _ADDIU -->
</prepatterns>
<postpatterns>
<data>......00 1....... 10111101 00100111</data> <!-- ADDIU SP,SP,-xxxx -->