diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc
index 027144c10b..97bb0a9743 100644
--- a/Ghidra/Processors/x86/data/languages/ia.sinc
+++ b/Ghidra/Processors/x86/data/languages/ia.sinc
@@ -809,6 +809,7 @@ m64:  "qword ptr" Mem  	is Mem      { export *:8 Mem; }
 # m80: Mem    is Mem      { export *:10 Mem; }
 m128: "xmmword ptr" Mem	is Mem      { export *:16 Mem; }
 m256: "ymmword ptr" Mem	is Mem      { export *:32 Mem; }
+m512: "64b ptr" Mem	    is Mem      { export *:64 Mem; }
 
 # spec versions of the m8/m16/m32/... tables explicitly print the operand size
 spec_m8: "byte ptr "^Mem     is Mem      { export *:1 Mem; }
@@ -5574,6 +5575,30 @@ define pcodeop minps;
 :MOVQ         rm64, XmmReg   is $(LONGMODE_ON) & vexMode=0 &  opsize=2 & $(PRE_66) & byte=0x0F; byte=0x7E; rm64 & XmmReg ...         { rm64 = XmmReg(0); }
 @endif
 
+
+:MOVDIRI Mem,Reg32        is $(LONGMODE_OFF) & vexMode=0 & $(PRE_NO)  & byte=0x0F; byte=0x38; byte=0xF9; Mem & Reg32 ...     { *Mem = Reg32; }
+@ifdef IA64
+:MOVDIRI Mem,Reg64        is  vexMode=0 & $(PRE_NO)        & $(REX_W) & byte=0x0F; byte=0x38; byte=0xF9; Mem & Reg64 ...     { *Mem = Reg64; }
+@endif
+
+define pcodeop movdir64b;
+:MOVDIR64B    Reg16, m512 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & addrsize=0 & byte=0x0F; byte=0x38; byte=0xF8; Reg16 ... & m512 {
+	movdir64b(Reg16, m512);
+}
+:MOVDIR64B    Reg32, m512 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & addrsize=1 & byte=0x0F; byte=0x38; byte=0xF8; Reg32 ... & m512 {
+	movdir64b(Reg32, m512);
+}
+
+@ifdef IA64
+:MOVDIR64B    Reg32, m512 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & addrsize=1 & byte=0x0F; byte=0x38; byte=0xF8; Reg32 ... & m512 {
+	movdir64b(Reg32, m512);
+}
+
+:MOVDIR64B    Reg64, m512 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xF8; Reg64 ... & m512 {
+	movdir64b(Reg64, m512);
+}
+@endif
+
 :MOVDDUP      XmmReg, m64         is vexMode=0 &  $(PRE_F2) & byte=0x0F; byte=0x12; m64 & XmmReg ...
 {
     XmmReg[0,64] = m64;