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Correctly implemented missing arm thumb AL conditional

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ghidorahrex 2021-10-19 09:34:12 -04:00
parent 2b0e703fa8
commit 5ff2fa62b1
1 changed files with 1 additions and 1 deletions
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Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
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@ -331,7 +331,7 @@ it_thfcc: "gt" is fcond=12 { tmp:1 = !ZR && (NG == OV); export tmp; }
it_thfcc: "le" is fcond=13 { tmp:1 = !ZR && (NG == OV); export tmp; }
it_thfcc: "al" is fcond=14 { tmp:1 = 1; export tmp; }
@define IT_THFCC "it_thfcc & (thc0707=0 | thc0606=0 | thc0505=0)"
@define IT_THFCC "it_thfcc & (thc0707=0 | thc0606=0 | thc0505=0 | thc0404=0)"
ByteRotate: "#"^rot is throt [rot = throt << 3; ] { export *[const]:1 rot; }