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Merge remote-tracking branch 'origin/patch'

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ghidra1 2022-04-20 12:53:14 -04:00
commit 47f76c78d6
5 changed files with 86 additions and 28 deletions
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12
Ghidra/Features/Base/src/main/java/ghidra/program/util/VarnodeContext.java
View File

@ -340,7 +340,7 @@ public class VarnodeContext implements ProcessorContext {
return isStackSpaceName(regSpace.getName());
}
/**
* Check if spaceName is associated with the stack
*
@ -849,6 +849,16 @@ public class VarnodeContext implements ProcessorContext {
allLastSet.put(node, addressSet);
}
addressSet.add(address);
// for registers with parent larger register, must store that they were
// last set at this address as well.
if (node.isRegister()) {
Register parentRegister = trans.getRegister(node).getParentRegister();
if (parentRegister != null) {
node = trans.getVarnode(parentRegister);
addSetVarnodeToLastSetLocations(node, address);
}
}
}
/**

36
Ghidra/Processors/MIPS/data/languages/mips.ldefs
View File

@ -4,7 +4,7 @@
endian="big"
size="32"
variant="default"
version="1.5"
version="1.6"
slafile="mips32be.sla"
processorspec="mips32.pspec"
manualindexfile="../manuals/mipsM16.idx"
@ -20,7 +20,7 @@
endian="little"
size="32"
variant="default"
version="1.5"
version="1.6"
slafile="mips32le.sla"
processorspec="mips32.pspec"
manualindexfile="../manuals/mipsM16.idx"
@ -36,7 +36,7 @@
endian="big"
size="32"
variant="R6"
version="1.5"
version="1.6"
slafile="mips32R6be.sla"
processorspec="mips32R6.pspec"
manualindexfile="../manuals/mipsMic.idx"
@ -50,7 +50,7 @@
endian="little"
size="32"
variant="R6"
version="1.5"
version="1.6"
slafile="mips32R6le.sla"
processorspec="mips32R6.pspec"
manualindexfile="../manuals/mipsMic.idx"
@ -64,7 +64,7 @@
endian="big"
size="64"
variant="default"
version="1.5"
version="1.6"
slafile="mips64be.sla"
processorspec="mips64.pspec"
manualindexfile="../manuals/mipsM16.idx"
@ -80,7 +80,7 @@
endian="little"
size="64"
variant="default"
version="1.5"
version="1.6"
slafile="mips64le.sla"
processorspec="mips64.pspec"
manualindexfile="../manuals/mipsM16.idx"
@ -97,7 +97,7 @@
endian="big"
size="64"
variant="micro"
version="1.5"
version="1.6"
slafile="mips64be.sla"
processorspec="mips64micro.pspec"
manualindexfile="../manuals/mipsMic.idx"
@ -112,7 +112,7 @@
endian="little"
size="64"
variant="micro"
version="1.5"
version="1.6"
slafile="mips64le.sla"
processorspec="mips64micro.pspec"
manualindexfile="../manuals/mipsMic.idx"
@ -128,7 +128,7 @@
endian="big"
size="64"
variant="R6"
version="1.5"
version="1.6"
slafile="mips64be.sla"
processorspec="mips64R6.pspec"
manualindexfile="../manuals/mipsMic.idx"
@ -143,7 +143,7 @@
endian="little"
size="64"
variant="R6"
version="1.5"
version="1.6"
slafile="mips64le.sla"
processorspec="mips64R6.pspec"
manualindexfile="../manuals/mipsMic.idx"
@ -159,7 +159,7 @@
endian="big"
size="32"
variant="64-32addr"
version="1.5"
version="1.6"
slafile="mips64be.sla"
processorspec="mips64.pspec"
manualindexfile="../manuals/mipsM16.idx"
@ -179,7 +179,7 @@
endian="little"
size="32"
variant="64-32addr"
version="1.5"
version="1.6"
slafile="mips64le.sla"
processorspec="mips64.pspec"
manualindexfile="../manuals/mipsM16.idx"
@ -200,7 +200,7 @@
endian="little"
size="32"
variant="64-32addr-micro"
version="1.5"
version="1.6"
slafile="mips64le.sla"
processorspec="mips64micro.pspec"
manualindexfile="../manuals/mipsMic.idx"
@ -220,7 +220,7 @@
endian="big"
size="32"
variant="64-32addr-micro"
version="1.5"
version="1.6"
slafile="mips64be.sla"
processorspec="mips64micro.pspec"
manualindexfile="../manuals/mipsMic.idx"
@ -239,7 +239,7 @@
endian="big"
size="32"
variant="64-32addr-R6"
version="1.5"
version="1.6"
slafile="mips64be.sla"
processorspec="mips64R6.pspec"
manualindexfile="../manuals/mipsMic.idx"
@ -258,7 +258,7 @@
endian="little"
size="32"
variant="64-32addr-R6"
version="1.5"
version="1.6"
slafile="mips64le.sla"
processorspec="mips64R6.pspec"
manualindexfile="../manuals/mipsMic.idx"
@ -278,7 +278,7 @@
endian="big"
size="32"
variant="micro"
version="1.5"
version="1.6"
slafile="mips32be.sla"
processorspec="mips32micro.pspec"
manualindexfile="../manuals/mipsMic.idx"
@ -293,7 +293,7 @@
endian="little"
size="32"
variant="micro"
version="1.5"
version="1.6"
slafile="mips32le.sla"
processorspec="mips32micro.pspec"
manualindexfile="../manuals/mipsMic.idx"

32
Ghidra/Processors/MIPS/data/languages/mips.sinc
View File

@ -357,6 +357,18 @@ define register offset=0x2700 size=$(REGSIZE) [
# Some other internal registers
define register offset=0x3000 size=$(REGSIZE) [ hi lo hi1 lo1 hi2 lo2 hi3 lo3 tsp ];
define register offset=0x3200 size=$(REGSIZE) [
HW_CPUNUM HW_SYNCI_STEP HW_CC HW_CCRe
HW_PerfCtr HW_XNP HW_RES6 HW_RES7
HW_RES8 HW_RES9 HW_RES10 HW_RES11
HW_RES12 HW_RES13 HW_RES14 HW_RES15
HW_RES16 HW_RES17 HW_RES18 HW_RES19
HW_RES20 HW_RES21 HW_RES22 HW_RES23
HW_RES24 HW_RES25 HW_RES26 HW_RES27
HW_RES28 HW_ULR HW_RESIM30 HW_RESIM31
];
define register offset=0x3F00 size=1 [ ISAModeSwitch ];
# Define context bits
@ -435,6 +447,7 @@ define context contextreg
;
# Instruction fields
define token instr(32)
@ -493,6 +506,7 @@ define token instr(32)
rd0_5 = (11,15)
rd0_6 = (11,15)
rd0_7 = (11,15)
rd_hw = (11,15)
cp2cprSel0 = (11,15)
cp2cprSel1 = (11,15)
cp2cprSel2 = (11,15)
@ -524,6 +538,7 @@ define token instr(32)
zero5 = (6,10)
wsbh = (6,10)
bp3 = (6,8)
sel_0608 = (6,8)
sa2 = (6,7)
bp2 = (6,7)
zero6 = (3,10)
@ -551,6 +566,17 @@ attach variables [ rs rt rd base index baser6 ] [
t8 t9 k0 k1 gp sp s8 ra
];
attach variables [ rd_hw ] [
HW_CPUNUM HW_SYNCI_STEP HW_CC HW_CCRe
HW_PerfCtr HW_XNP HW_RES6 HW_RES7
HW_RES8 HW_RES9 HW_RES10 HW_RES11
HW_RES12 HW_RES13 HW_RES14 HW_RES15
HW_RES26 HW_RES17 HW_RES18 HW_RES19
HW_RES20 HW_RES21 HW_RES22 HW_RES23
HW_RES24 HW_RES25 HW_RES26 HW_RES27
HW_RES28 HW_ULR HW_RESIM30 HW_RESIM31
];
@ifdef MIPS64
attach variables [ rs32 rt32 rd32 ] [
zero_lo at_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo
@ -887,11 +913,11 @@ define pcodeop countLeadingZeros;
# extractField(value, msbd, lsb)
define pcodeop extractField;
# getHWRegister(regnum)
define pcodeop getHWRegister;
# setShadow(sgpr, value)
define pcodeop setShadow;
# getHWRegister(reg, sel)
define pcodeop getHWRegister;
# gpr = getShadow(sgpr)
define pcodeop getShadow;

9
Ghidra/Processors/MIPS/data/languages/mips32Instructions.sinc
View File

@ -529,8 +529,13 @@ define pcodeop special2;
}
# 0111 1100 000t tttt dddd d000 0011 1011
:rdhwr RT, RDsrc is $(AMODE) & prime=0x1F & rs=0 & fct2=0 & fct=0x3B & RT & RDsrc {
RT = getHWRegister(RDsrc);
:rdhwr RT, rd_hw is $(AMODE) & prime=0x1F & rs=0 & fct2=0 & fct=0x3B & RT & rd_hw & rd!=4 {
RT = getHWRegister(rd_hw);
}
# 0111 1100 000t tttt dddd d000 0011 1011
:rdhwr RT, rd_hw, sel_0608 is $(AMODE) & REL6=1 & prime=0x1F & rs=0 & spec2=0 & fct=0x3B & RT & rd_hw & rd=4 & sel_0608 {
RT = getHWRegister(rd_hw, sel_0608:1);
}
# 0100 0001 010t tttt dddd d000 0000 0000

25
Ghidra/Processors/MIPS/data/languages/mipsmicro.sinc
View File

@ -42,6 +42,7 @@ define token micinstr (16)
mic_rs32_0a=(0,4)
mic_rs32_0b=(0,4)
mic_rs32_0lo=(0,4)
mic_rs32_hw=(0,4)
mic_rs32_5=(5,9)
mic_rt32_0=(0,4)
@ -187,6 +188,17 @@ define token micinstrb (16)
attach variables [ mic_rd7 mic_rd1 mic_rt4 mic_rs1 mic_rs7 mic_rs0 mic_rs4 mic_rt3 mic_rt7 mic_base4 ]
[ s0 s1 v0 v1 a0 a1 a2 a3 ];
attach variables [ mic_rs32_hw ] [
HW_CPUNUM HW_SYNCI_STEP HW_CC HW_CCRe
HW_PerfCtr HW_XNP HW_RES6 HW_RES7
HW_RES8 HW_RES9 HW_RES10 HW_RES11
HW_RES12 HW_RES13 HW_RES14 HW_RES15
HW_RES16 HW_RES17 HW_RES18 HW_RES19
HW_RES20 HW_RES21 HW_RES22 HW_RES23
HW_RES24 HW_RES25 HW_RES26 HW_RES27
HW_RES28 HW_ULR HW_RESIM30 HW_RESIM31
];
@ifdef MIPS64
attach variables [ mic_rd7lo mic_rd1lo mic_rt4lo mic_rs1lo mic_rs7lo mic_rs0lo mic_rs4lo mic_rt3lo mic_rt7lo ]
[ s0_lo s1_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo ];
@ -2769,8 +2781,8 @@ STORE_TOP16: STORE_SREG^ra,EXT_CODE4E(sp) is mic_listr6 & REL6=1 & STORE_SREG &
micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);
}
:rdhwr mic_rt32_5, mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0110101100 {
mic_rt32_5 = getHWRegister(mic_rs32_0);
:rdhwr mic_rt32_5, mic_rs32_hw is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rt32_5 & mic_rs32_hw ; micb_poolax=0b111100 & micb_axf=0b0110101100 {
mic_rt32_5 = getHWRegister(mic_rs32_hw);
}
:sub.PS micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=2 & micb_fxf3=0b01110000 {
@ -3663,8 +3675,13 @@ STORE_TOP16: STORE_SREG^ra,EXT_CODE4E(sp) is mic_listr6 & REL6=1 & STORE_SREG &
micb_rd32 = sext(tmp);
}
:rdhwr mic_rt32_5, mic_rs32_0, micb_sel is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rt32_5 & mic_rs32_0 ; micb_sel & micb_z14=0 & micb_bit10=0 & micb_axf2=0b0111000000 {
mic_rt32_5 = getHWRegister(mic_rs32_0, micb_sel:1);
#sel only valid for PerfCtr
:rdhwr mic_rt32_5, mic_rs32_hw, micb_sel is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rt32_5 & mic_rs32_hw & mic_rs32_0=4; micb_sel & micb_z14=0 & micb_bit10=0 & micb_axf2=0b0111000000 {
mic_rt32_5 = getHWRegister(mic_rs32_hw, micb_sel:1);
}
:rdhwr mic_rt32_5, mic_rs32_hw is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rt32_5 & mic_rs32_hw & mic_rs32_0!=4; micb_sel=0 & micb_z14=0 & micb_bit10=0 & micb_axf2=0b0111000000 {
mic_rt32_5 = getHWRegister(mic_rs32_hw);
}
:rint.S mic_fd, mic_fs_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs_5 & mic_fd ; micb_fd=0 & micb_fmt9=0 & micb_fxf5=0b000100000 {