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AA64: Separate vector subtraction into components

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Sleigh-InSPECtor 2024-05-16 15:00:22 +09:30
parent cae9190c13
commit 4239afbdec
1 changed files with 3 additions and 1 deletions
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Ghidra/Processors/AARCH64/data/languages/AARCH64neon.sinc
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@ -7728,7 +7728,9 @@ is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S
# simd infix TMPD1 = Rn_VPR64.2S f* Rm_VPR64.2S on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] f* Rm_VPR64.2S[0,32];
TMPD1[32,32] = Rn_VPR64.2S[32,32] f* Rm_VPR64.2S[32,32];
Rd_VPR64.2S = Rd_VPR64.2S f- TMPD1;
# simd infix Rd_VPR64.2S = Rd_VPR64.2S f- TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] f- TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] f- TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}