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Merge remote-tracking branch 'origin/GT-3390_ghidorahrex_PR-1201_aladur_M6809Support'

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This commit is contained in:
Ryan Kurtz 2019-12-11 14:16:15 -05:00
commit 40069dcaab
9 changed files with 1606 additions and 1 deletions
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7
Ghidra/Processors/6805/certification.manifest
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@ -5,3 +5,10 @@ data/languages/6805.cspec||GHIDRA||||END|
data/languages/6805.ldefs||GHIDRA||||END|
data/languages/6805.pspec||GHIDRA||reviewed||END|
data/languages/6805.slaspec||GHIDRA||||END|
data/languages/6809.cspec||GHIDRA||||END|
data/languages/6809.pspec||GHIDRA||||END|
data/languages/6809.slaspec||GHIDRA||||END|
data/languages/6x09.sinc||GHIDRA||||END|
data/languages/6x09_exg_tfr.sinc||GHIDRA||||END|
data/languages/6x09_pull.sinc||GHIDRA||||END|
data/languages/6x09_push.sinc||GHIDRA||||END|

13
Ghidra/Processors/6805/data/languages/6805.ldefs
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@ -16,6 +16,17 @@
<external_name tool="IDA-PRO" name="6803"/>
<external_name tool="IDA-PRO" name="6805"/>
<external_name tool="IDA-PRO" name="6808"/>
<external_name tool="IDA-PRO" name="6809"/>
</language>
<language processor="6809"
endian="big"
size="16"
variant="default"
version="1.0"
slafile="6809.sla"
processorspec="6809.pspec"
id="6809:BE:16:default">
<description>6809 Microprocessor</description>
<compiler name="default" spec="6809.cspec" id="default"/>
<external_name tool="IDA-PRO" name="6809"/>
</language>
</language_definitions>

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Ghidra/Processors/6805/data/languages/6809.cspec Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="RAM"/>
</global>
<stackpointer register="S" space="RAM" growth="negative"/>
<default_proto>
<prototype name="__stdcall" extrapop="2" stackshift="2">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="B"/>
</pentry>
<pentry minsize="2" maxsize="2">
<register name="X"/>
</pentry>
<pentry minsize="2" maxsize="2">
<register name="Y"/>
</pentry>
<pentry minsize="2" maxsize="2">
<register name="U"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
</output>
<unaffected>
<register name="S"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>

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Ghidra/Processors/6805/data/languages/6809.pspec Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
</processor_spec>

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Ghidra/Processors/6805/data/languages/6809.slaspec Normal file
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# sleigh specification file for Motorola 6809
@define M6809
@include "6x09.sinc"
@include "6x09_push.sinc"
@include "6x09_pull.sinc"
@include "6x09_exg_tfr.sinc"

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Ghidra/Processors/6805/data/languages/6x09.sinc Normal file
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Ghidra/Processors/6805/data/languages/6x09_exg_tfr.sinc Normal file
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# sleigh specification file for Motorola 6809/Hitachi 6309
################################################################
# EXG, TFR helper
################################################################
@ifdef H6309
EXG_r0Tmp: D is reg0_exg=0 & D { exg16_r0 = D; }
EXG_r0Tmp: X is reg0_exg=1 & X { exg16_r0 = X; }
EXG_r0Tmp: Y is reg0_exg=2 & Y { exg16_r0 = Y; }
EXG_r0Tmp: U is reg0_exg=3 & U { exg16_r0 = U; }
EXG_r0Tmp: S is reg0_exg=4 & S { exg16_r0 = S; }
EXG_r0Tmp: PC is reg0_exg=5 & PC { exg16_r0 = inst_next; }
EXG_r0Tmp: W is reg0_exg=6 & W { exg16_r0 = 0x0; }
EXG_r0Tmp: V is reg0_exg=7 & V { exg16_r0 = 0x0; }
EXG_r0Tmp: A is reg0_exg=8 & A { exg8l_r0 = A; exg8h_r0 = A; }
EXG_r0Tmp: B is reg0_exg=9 & B { exg8l_r0 = B; exg8h_r0 = B; }
EXG_r0Tmp: CC is reg0_exg=10 & CC { exg8l_r0 = CC; exg8h_r0 = CC;}
EXG_r0Tmp: DP is reg0_exg=12 & DP { exg8l_r0 = DP; exg8h_r0 = DP;}
EXG_r0Tmp: 0 is reg0_exg=13 { exg16_r0 = 0x0; }
EXG_r0Tmp: 0 is reg0_exg=14 { exg16_r0 = 0x0; }
EXG_r0Tmp: E is reg0_exg=15 & E { exg8l_r0 = E; exg8h_r0 = E; }
EXG_r0Tmp: F is reg0_exg=16 & F { exg8l_r0 = F; exg8h_r0 = F; }
EXG_r1Tmp: D is reg1_exg=0 & D { exg16_r1 = D; }
EXG_r1Tmp: X is reg1_exg=1 & X { exg16_r1 = X; }
EXG_r1Tmp: Y is reg1_exg=2 & Y { exg16_r1 = Y; }
EXG_r1Tmp: U is reg1_exg=3 & U { exg16_r1 = U; }
EXG_r1Tmp: S is reg1_exg=4 & S { exg16_r1 = S; }
EXG_r1Tmp: PC is reg1_exg=5 & PC { exg16_r1 = inst_next; }
EXG_r1Tmp: W is reg1_exg=6 & W { exg16_r1 = 0x0; }
EXG_r1Tmp: V is reg1_exg=7 & V { exg16_r1 = 0x0; }
EXG_r1Tmp: A is reg1_exg=8 & A { exg8l_r1 = A; exg8h_r1 = A; }
EXG_r1Tmp: B is reg1_exg=9 & B { exg8l_r1 = B; exg8h_r1 = B; }
EXG_r1Tmp: CC is reg1_exg=10 & CC { exg8l_r1 = CC; exg8h_r1 = CC;}
EXG_r1Tmp: DP is reg1_exg=12 & DP { exg8l_r1 = DP; exg8h_r1 = DP;}
EXG_r1Tmp: 0 is reg1_exg=13 { exg16_r1 = 0x0; }
EXG_r1Tmp: 0 is reg1_exg=14 { exg16_r1 = 0x0; }
EXG_r1Tmp: E is reg1_exg=15 & E { exg8l_r1 = E; exg8h_r1 = E; }
EXG_r1Tmp: F is reg1_exg=16 & F { exg8l_r1 = F; exg8h_r1 = F; }
EXG_r0Set: D is reg0_exg=0 & D { D = exg16_r1; }
EXG_r0Set: X is reg0_exg=1 & X { X = exg16_r1; }
EXG_r0Set: Y is reg0_exg=2 & Y { Y = exg16_r1; }
EXG_r0Set: U is reg0_exg=3 & U { U = exg16_r1; }
EXG_r0Set: S is reg0_exg=4 & S { S = exg16_r1; }
EXG_r0Set: PC is reg0_exg=5 & PC { PC = exg16_r1; } # must GOTO
EXG_r0Set: W is reg0_exg=6 & W { W = exg16_r1; }
EXG_r0Set: V is reg0_exg=7 & V { V = exg16_r1; }
EXG_r0Set: A is reg0_exg=8 & A { A = exg8h_r1; }
EXG_r0Set: B is reg0_exg=9 & B { B = exg8l_r1; }
EXG_r0Set: CC is reg0_exg=10 & CC { CC = exg8l_r1; }
EXG_r0Set: DP is reg0_exg=11 & DP { DP = exg8h_r1; }
EXG_r0Set: 0 is reg0_exg=12 { }
EXG_r0Set: 0 is reg0_exg=13 { }
EXG_r0Set: E is reg0_exg=14 & E { E = exg8h_r1; }
EXG_r0Set: F is reg0_exg=15 & F { F = exg8l_r1; }
EXG_r1Set: D is reg1_exg=0 & D { D = exg16_r0; }
EXG_r1Set: X is reg1_exg=1 & X { X = exg16_r0; }
EXG_r1Set: Y is reg1_exg=2 & Y { Y = exg16_r0; }
EXG_r1Set: U is reg1_exg=3 & U { U = exg16_r0; }
EXG_r1Set: S is reg1_exg=4 & S { S = exg16_r0; }
EXG_r1Set: PC is reg1_exg=5 & PC { PC = exg16_r0; } # must GOTO
EXG_r1Set: W is reg1_exg=6 & W { W = exg16_r0; }
EXG_r1Set: V is reg1_exg=7 & V { V = exg16_r0; }
EXG_r1Set: A is reg1_exg=8 & A { A = exg8h_r0; }
EXG_r1Set: B is reg1_exg=9 & B { B = exg8l_r0; }
EXG_r1Set: CC is reg1_exg=10 & CC { CC = exg8l_r0; }
EXG_r1Set: DP is reg1_exg=11 & DP { DP = exg8h_r0; }
EXG_r1Set: 0 is reg1_exg=12 { }
EXG_r1Set: 0 is reg1_exg=13 { }
EXG_r1Set: E is reg1_exg=14 & E { E = exg8h_r0; }
EXG_r1Set: F is reg1_exg=15 & F { F = exg8l_r0; }
@endif
@ifdef M6809
EXG_r0Tmp: D is reg0_exg=0 & D { exg16_r0 = D; }
EXG_r0Tmp: X is reg0_exg=1 & X { exg16_r0 = X; }
EXG_r0Tmp: Y is reg0_exg=2 & Y { exg16_r0 = Y; }
EXG_r0Tmp: U is reg0_exg=3 & U { exg16_r0 = U; }
EXG_r0Tmp: S is reg0_exg=4 & S { exg16_r0 = S; }
EXG_r0Tmp: PC is reg0_exg=5 & PC { exg16_r0 = inst_next; }
EXG_r0Tmp: "inv" is reg0_exg=6 { exg16_r0 = 0xFFFF; }
EXG_r0Tmp: "inv" is reg0_exg=7 { exg16_r0 = 0xFFFF; }
EXG_r0Tmp: A is reg0_exg=8 & A { exg8l_r0 = A; exg8h_r0 = 0xFF; }
EXG_r0Tmp: B is reg0_exg=9 & B { exg8l_r0 = B; exg8h_r0 = 0xFF; }
EXG_r0Tmp: CC is reg0_exg=10 & CC { exg8l_r0 = CC; exg8h_r0 = CC;}
EXG_r0Tmp: DP is reg0_exg=11 & DP { exg8l_r0 = DP; exg8h_r0 = DP;}
EXG_r0Tmp: "inv" is reg0_exg=12 { exg16_r0 = 0xFFFF; }
EXG_r0Tmp: "inv" is reg0_exg=13 { exg16_r0 = 0xFFFF; }
EXG_r0Tmp: "inv" is reg0_exg=14 { exg16_r0 = 0xFFFF; }
EXG_r0Tmp: "inv" is reg0_exg=15 { exg16_r0 = 0xFFFF; }
EXG_r1Tmp: D is reg1_exg=0 & D { exg16_r1 = D; }
EXG_r1Tmp: X is reg1_exg=1 & X { exg16_r1 = X; }
EXG_r1Tmp: Y is reg1_exg=2 & Y { exg16_r1 = Y; }
EXG_r1Tmp: U is reg1_exg=3 & U { exg16_r1 = U; }
EXG_r1Tmp: S is reg1_exg=4 & S { exg16_r1 = S; }
EXG_r1Tmp: PC is reg1_exg=5 & PC { exg16_r1 = inst_next; }
EXG_r1Tmp: "inv" is reg1_exg=6 { exg16_r1 = 0xFFFF; }
EXG_r1Tmp: "inv" is reg1_exg=7 { exg16_r1 = 0xFFFF; }
EXG_r1Tmp: A is reg1_exg=8 & A { exg8l_r1 = A; exg8h_r1 = 0xFF; }
EXG_r1Tmp: B is reg1_exg=9 & B { exg8l_r1 = B; exg8h_r1 = 0xFF; }
EXG_r1Tmp: CC is reg1_exg=10 & CC { exg8l_r1 = CC; exg8h_r1 = 0xFF;}
EXG_r1Tmp: DP is reg1_exg=11 & DP { exg8l_r1 = DP; exg8h_r1 = 0xFF;}
EXG_r1Tmp: "inv" is reg1_exg=12 { exg16_r1 = 0xFFFF; }
EXG_r1Tmp: "inv" is reg1_exg=13 { exg16_r1 = 0xFFFF; }
EXG_r1Tmp: "inv" is reg1_exg=14 { exg16_r1 = 0xFFFF; }
EXG_r1Tmp: "inv" is reg1_exg=15 { exg16_r1 = 0xFFFF; }
EXG_r0Set: D is reg0_exg=0 & D { D = exg16_r1; }
EXG_r0Set: X is reg0_exg=1 & X { X = exg16_r1; }
EXG_r0Set: Y is reg0_exg=2 & Y { Y = exg16_r1; }
EXG_r0Set: U is reg0_exg=3 & U { U = exg16_r1; }
EXG_r0Set: S is reg0_exg=4 & S { S = exg16_r1; }
EXG_r0Set: PC is reg0_exg=5 & PC { PC = exg16_r1; } # must GOTO
EXG_r0Set: "inv" is reg0_exg=6 { }
EXG_r0Set: "inv" is reg0_exg=7 { }
EXG_r0Set: A is reg0_exg=8 & A { A = exg8l_r1; }
EXG_r0Set: B is reg0_exg=9 & B { B = exg8l_r1; }
EXG_r0Set: CC is reg0_exg=10 & CC { CC = exg8l_r1; }
EXG_r0Set: DP is reg0_exg=11 & DP { DP = exg8l_r1; }
EXG_r0Set: "inv" is reg0_exg=12 { }
EXG_r0Set: "inv" is reg0_exg=13 { }
EXG_r0Set: "inv" is reg0_exg=14 { }
EXG_r0Set: "inv" is reg0_exg=15 { }
EXG_r1Set: D is reg1_exg=0 & D { D = exg16_r0; } # Must to r1 set first so A,D = A,B switch
EXG_r1Set: X is reg1_exg=1 & X { X = exg16_r0; }
EXG_r1Set: Y is reg1_exg=2 & Y { Y = exg16_r0; }
EXG_r1Set: U is reg1_exg=3 & U { U = exg16_r0; }
EXG_r1Set: S is reg1_exg=4 & S { S = exg16_r0; }
EXG_r1Set: PC is reg1_exg=5 & PC { PC = exg16_r0; } # must GOTO
EXG_r1Set: "inv" is reg1_exg=6 { }
EXG_r1Set: "inv" is reg1_exg=7 { }
EXG_r1Set: A is reg1_exg=8 & A { A = exg8l_r0; }
EXG_r1Set: B is reg1_exg=9 & B { B = exg8l_r0; }
EXG_r1Set: CC is reg1_exg=10 & CC { CC = exg8l_r0; }
EXG_r1Set: DP is reg1_exg=11 & DP { DP = exg8l_r0; }
EXG_r1Set: "inv" is reg1_exg=12 { }
EXG_r1Set: "inv" is reg1_exg=13 { }
EXG_r1Set: "inv" is reg1_exg=14 { }
EXG_r1Set: "inv" is reg1_exg=15 { }
@endif
EXG_GOTO: is reg0_exg=5 | reg1_exg=5 { goto [PC]; }
EXG_GOTO: is reg0_exg & reg1_exg { } # PC not set
TFR_GOTO: is reg1_exg=5 { goto [PC]; }
TFR_GOTO: is reg1_exg { } # PC not set
# Exchange two registers
:EXG EXG_r0Set,EXG_r1Set is op=0x1E; EXG_r0Set & EXG_r1Set & EXG_r0Tmp & EXG_r1Tmp & EXG_GOTO
{
build EXG_r0Tmp;
build EXG_r1Tmp;
build EXG_r1Set;
build EXG_r0Set;
build EXG_GOTO;
}
# Transfer register to another register
:TFR EXG_r0Set,EXG_r1Set is op=0x1F; EXG_r0Set & EXG_r1Set & EXG_r0Tmp & TFR_GOTO
{
build EXG_r0Tmp;
build EXG_r1Set;
build TFR_GOTO;
}

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Ghidra/Processors/6805/data/languages/6x09_pull.sinc Normal file
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# sleigh specification file for Motorola 6809/Hitachi 6309
#################################################################
# PULS helper
################################################################
puls0: CC is CC & imm80=1 { Pull1(S, CC); }
puls0: is imm80=0 { }
puls1: puls0" "A is A & imm81=1 & puls0 { Pull1(S, A); }
puls1: puls0 is imm81=0 & puls0 { }
puls2: puls1" "B is B & imm82=1 & puls1 { Pull1(S, B); }
puls2: puls1 is imm82=0 & puls1 { }
puls3: puls2" "DP is DP & imm83=1 & puls2 { Pull1(S, DP); }
puls3: puls2 is imm83=0 & puls2 { }
puls4: puls3" "X is X & imm84=1 & puls3 { Pull2(S, X); }
puls4: puls3 is imm84=0 & puls3 { }
puls5: puls4" "Y is Y & imm85=1 & puls4 { Pull2(S, Y); }
puls5: puls4 is imm85=0 & puls4 { }
puls6: puls5" "U is U & imm86=1 & puls5 { Pull2(S, U); }
puls6: puls5 is imm86=0 & puls5 { }
puls7: puls6" "PC is PC & imm87=1 & puls6 { local t:2 = inst_next; Pull2(S, t); }
puls7: puls6 is imm87=0 & puls6 { }
:PULS puls7 is op=0x35; puls7 { }
################################################################
# PULU helper
################################################################
pulu0: CC is CC & imm80=1 { Pull1(U, CC); }
pulu0: is imm80=0 { }
pulu1: pulu0" "A is A & imm81=1 & pulu0 { Pull1(U, A); }
pulu1: pulu0 is imm81=0 & pulu0 { }
pulu2: pulu1" "B is B & imm82=1 & pulu1 { Pull1(U, B); }
pulu2: pulu1 is imm82=0 & pulu1 { }
pulu3: pulu2" "DP is DP & imm83=1 & pulu2 { Pull1(U, DP); }
pulu3: pulu2 is imm83=0 & pulu2 { }
pulu4: pulu3" "X is X & imm84=1 & pulu3 { Pull2(U, X); }
pulu4: pulu3 is imm84=0 & pulu3 { }
pulu5: pulu4" "Y is Y & imm85=1 & pulu4 { Pull2(U, Y); }
pulu5: pulu4 is imm85=0 & pulu4 { }
pulu6: pulu5" "S is S & imm86=1 & pulu5 { Pull2(U, S); }
pulu6: pulu5 is imm86=0 & pulu5 { }
pulu7: pulu6" "PC is PC & imm87=1 & pulu6 { local t:2 = inst_next; Pull2(U, t); }
pulu7: pulu6 is imm87=0 & pulu6 { }
:PULU pulu7 is op=0x37; pulu7 { }

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Ghidra/Processors/6805/data/languages/6x09_push.sinc Normal file
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# sleigh specification file for Motorola 6809/Hitachi 6309
################################################################
# PSHS helper
################################################################
pshs0: CC is CC & imm80=1 { Push1(S, CC); }
pshs0: is imm80=0 { }
pshs1: pshs0" "A is A & imm81=1 & pshs0 { Push1(S, A); }
pshs1: pshs0 is imm81=0 & pshs0 { }
pshs2: pshs1" "B is B & imm82=1 & pshs1 { Push1(S, B); }
pshs2: pshs1 is imm82=0 & pshs1 { }
pshs3: pshs2" "DP is DP & imm83=1 & pshs2 { Push1(S, DP); }
pshs3: pshs2 is imm83=0 & pshs2 { }
pshs4: pshs3" "X is X & imm84=1 & pshs3 { Push2(S, X); }
pshs4: pshs3 is imm84=0 & pshs3 { }
pshs5: pshs4" "Y is Y & imm85=1 & pshs4 { Push2(S, Y); }
pshs5: pshs4 is imm85=0 & pshs4 { }
pshs6: pshs5" "U is U & imm86=1 & pshs5 { Push2(S, U); }
pshs6: pshs5 is imm86=0 & pshs5 { }
pshs7: pshs6" "PC is PC & imm87=1 & pshs6 { local t:2 = inst_next; Push2(S, t); }
pshs7: pshs6 is imm87=0 & pshs6 { }
:PSHS pshs7 is op=0x34; pshs7 { }
################################################################
# PSHU helper
################################################################
pshu0: CC is CC & imm80=1 { Push1(S, CC); }
pshu0: is imm80=0 { }
pshu1: pshu0" "A is A & imm81=1 & pshu0 { Push1(S, A); }
pshu1: pshu0 is imm81=0 & pshu0 { }
pshu2: pshu1" "B is B & imm82=1 & pshu1 { Push1(S, B); }
pshu2: pshu1 is imm82=0 & pshu1 { }
pshu3: pshu2" "DP is DP & imm83=1 & pshu2 { Push1(U, DP); }
pshu3: pshu2 is imm83=0 & pshu2 { }
pshu4: pshu3" "X is X & imm84=1 & pshu3 { Push2(U, X); }
pshu4: pshu3 is imm84=0 & pshu3 { }
pshu5: pshu4" "Y is Y & imm85=1 & pshu4 { Push2(U, Y); }
pshu5: pshu4 is imm85=0 & pshu4 { }
pshu6: pshu5" "S is S & imm86=1 & pshu5 { Push2(U, S); }
pshu6: pshu5 is imm86=0 & pshu5 { }
pshu7: pshu6" "PC is PC & imm87=1 & pshu6 { local t:2 = inst_next; Push2(U, t); }
pshu7: pshu6 is imm87=0 & pshu6 { }
:PSHU pshu7 is op=0x36; pshu7 { }