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x86: Allow repeated REP prefixes

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The semantic is determined by the prefix byte that is placed closest to
instruction opcode.
This commit is contained in:
Eric Kilmer 2022-09-10 18:50:33 -04:00 committed by James
parent 26f84198ea
commit 3b0d7d34bf
1 changed files with 2 additions and 2 deletions
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Ghidra/Processors/x86/data/languages/ia.sinc
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@ -1508,8 +1508,8 @@ macro fucompe(val1, val2) {
:^instruction is instrPhase=0 & over=0x65; instruction [ segover=6; ] {} # GS override
:^instruction is instrPhase=0 & over=0x66; instruction [ opsize=opsize $xor 1; mandover = mandover $xor 1; ] {} # Operand size override
:^instruction is instrPhase=0 & over=0x67; instruction [ addrsize=addrsize $xor 1; ] {} # Address size override
:^instruction is instrPhase=0 & over=0xf2; instruction [ repneprefx=1; ] {}
:^instruction is instrPhase=0 & over=0xf3; instruction [ repprefx=1; ] {}
:^instruction is instrPhase=0 & over=0xf2; instruction [ repneprefx=1; repprefx=0; ] {}
:^instruction is instrPhase=0 & over=0xf3; instruction [ repneprefx=0; repprefx=1; ] {}
@ifdef IA64
#