mirror of
https://github.com/NationalSecurityAgency/ghidra.git
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8048: Reformat to begin and end each semantic section with NL (unless empty)
This commit is contained in:
Marcus Comstedt
parent
4f6e4bc172
commit
3a8e59319a
@ -240,113 +240,302 @@ Rind: @ri is ri & rifill=0 {
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local ptr:1 = ri; regbank(ptr); export *[INTMEM]:1 ptr;
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}
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@endif
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Ri: Rind is Rind { export *[INTMEM]:1 Rind; }
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RiX: Rind is Rind { export *[EXTMEM]:1 Rind; }
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Ri: Rind is Rind {
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export *[INTMEM]:1 Rind;
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}
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RiX: Rind is Rind {
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export *[EXTMEM]:1 Rind;
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}
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PData: @A is A {
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local addr:2 = inst_next; addr[0,7] = A; export *[CODE]:1 addr; }
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local addr:2 = inst_next; addr[0,7] = A; export *[CODE]:1 addr;
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}
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P3Data: @A is A {
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local addr:2 = 0x300; addr[0,7] = A; export *[CODE]:1 addr; }
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local addr:2 = 0x300; addr[0,7] = A; export *[CODE]:1 addr;
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}
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AddrInd: PData is PData {
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local addr:2 = inst_next; addr[0,7] = PData; export *[CODE]:1 addr; }
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Ab: abit is abit { local bit:1 = (A>>abit)&1; export bit; }
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Data: "#"^data is data { export *[const]:1 data; }
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Imm: Data is oplo=3; Data { export Data; }
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local addr:2 = inst_next; addr[0,7] = PData; export *[CODE]:1 addr;
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}
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Ab: abit is abit {
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local bit:1 = (A>>abit)&1; export bit;
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}
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Data: "#"^data is data {
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export *[const]:1 data;
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}
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Imm: Data is oplo=3; Data {
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export Data;
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}
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Addr8: addr is addr8 [ addr = (inst_next $and 0xf00)+addr8; ] {
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export *[CODE]:1 addr; }
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export *[CODE]:1 addr;
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}
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Addr12: addr is aopaddr & adata [ addr = (DFB*2048)+(aopaddr*256)+adata; ] {
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export *[CODE]:1 addr; }
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Bus: "BUS" is epsilon { local tmp:1 = 0; export *[PORT]:1 tmp; }
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Pp: pp is pp & ppfill=2 { export *[PORT]:1 pp; }
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Xpp: xpp is xpp & ppfill=3 { local tmp:1 = xpp+4; export *[PORT]:1 tmp; }
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export *[CODE]:1 addr;
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}
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Bus: "BUS" is epsilon {
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local tmp:1 = 0; export *[PORT]:1 tmp;
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}
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Pp: pp is pp & ppfill=2 {
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export *[PORT]:1 pp;
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}
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Xpp: xpp is xpp & ppfill=3 {
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local tmp:1 = xpp+4; export *[PORT]:1 tmp;
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}
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Cc: "C" is ophi=15 { export C; }
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Cc: "F0" is ophi=11 { export F0; }
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Cc: "F1" is ophi=7 { export F1; }
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Cc: "NC" is ophi=14 { tmp:1 = !C; export tmp; }
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Cc: "NI" is ophi=8 { tmp:1 = getExtInt(); tmp = !tmp; export tmp; }
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Cc: "NT0" is ophi=2 { tmp:1 = getT0(); tmp = !tmp; export tmp; }
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Cc: "NT1" is ophi=4 { tmp:1 = getT1(); tmp = !tmp; export tmp; }
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Cc: "NZ" is ophi=9 { tmp:1 = A!=0; export tmp; }
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Cc: "TF" is ophi=1 { tmp:1 = getTF(); export tmp; }
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Cc: "T0" is ophi=3 { tmp:1 = getT0(); export tmp; }
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Cc: "T1" is ophi=5 { tmp:1 = getT1(); export tmp; }
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Cc: "Z" is ophi=12 { tmp:1 = A==0; export tmp; }
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Cc: "C" is ophi=15 {
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export C;
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}
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Cc: "F0" is ophi=11 {
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export F0;
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}
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Cc: "F1" is ophi=7 {
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export F1;
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}
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Cc: "NC" is ophi=14 {
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tmp:1 = !C; export tmp;
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}
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Cc: "NI" is ophi=8 {
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tmp:1 = getExtInt(); tmp = !tmp; export tmp;
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}
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Cc: "NT0" is ophi=2 {
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tmp:1 = getT0(); tmp = !tmp; export tmp;
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}
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Cc: "NT1" is ophi=4 {
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tmp:1 = getT1(); tmp = !tmp; export tmp;
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}
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Cc: "NZ" is ophi=9 {
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tmp:1 = A!=0; export tmp;
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}
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Cc: "TF" is ophi=1 {
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tmp:1 = getTF(); export tmp;
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}
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Cc: "T0" is ophi=3 {
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tmp:1 = getT0(); export tmp;
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}
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Cc: "T1" is ophi=5 {
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tmp:1 = getT1(); export tmp;
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}
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Cc: "Z" is ophi=12 {
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tmp:1 = A==0; export tmp;
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}
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# Conventience tables for opcodes taking both Rn and Ri (and Imm)
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Rni: Rn is Rn { export Rn; }
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Rni: Ri is Ri { export Ri; }
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RniI: Rni is Rni { export Rni; }
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RniI: Imm is Imm { export Imm; }
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Rni: Rn is Rn {
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export Rn;
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}
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Rni: Ri is Ri {
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export Ri;
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}
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RniI: Rni is Rni {
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export Rni;
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}
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RniI: Imm is Imm {
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export Imm;
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}
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# These are not decoded correctly if placed alphabetically...
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:JB^Ab Addr8 is oplo=2 & abfill=1 & Ab; Addr8 { if(Ab) goto Addr8; }
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:J^Cc Addr8 is oplo=6 & Cc; Addr8 { if(Cc) goto Addr8; }
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:CALL Addr12 is aaddrfill=1 & aoplo=4 & Addr12 { funcall(Addr12); }
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:JMP Addr12 is aaddrfill=0 & aoplo=4 & Addr12 { goto Addr12; }
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:DJNZ Rn,Addr8 is ophi=14 & Rn; Addr8 { Rn = Rn - 1; if(Rn != 0) goto Addr8; }
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:JB^Ab Addr8 is oplo=2 & abfill=1 & Ab; Addr8 {
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if(Ab) goto Addr8;
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}
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:J^Cc Addr8 is oplo=6 & Cc; Addr8 {
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if(Cc) goto Addr8;
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}
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:CALL Addr12 is aaddrfill=1 & aoplo=4 & Addr12 {
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funcall(Addr12);
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}
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:JMP Addr12 is aaddrfill=0 & aoplo=4 & Addr12 {
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goto Addr12;
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}
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:DJNZ Rn,Addr8 is ophi=14 & Rn; Addr8 {
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Rn = Rn - 1; if(Rn != 0) goto Addr8;
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}
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:ADD A,Rni is ophi=6 & A & Rni { add(A,A,Rni,0); }
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:ADD A,Imm is (ophi=0 & A)... & Imm { add(A,A,Imm,0); }
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:ADDC A,Rni is ophi=7 & A & Rni { add(A,A,Rni,C); }
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:ADDC A,Imm is (ophi=1 & A)... & Imm { add(A,A,Imm,C); }
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:ANL A,RniI is (ophi=5 & A)... & RniI { A = A & RniI; }
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:ANL Pp,Data is ophi=9 & Pp; Data { Pp = Pp & Data; }
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:ANLD Xpp,A is ophi=9 & Xpp & A { Xpp = Xpp & (A & 0xf); }
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:CLR A is ophi=2 & oplo=7 & A { A = 0; }
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:CLR C is ophi=9 & oplo=7 & C { C = 0; }
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:CLR F0 is ophi=8 & oplo=5 & F0 { F0 = 0; }
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:CLR F1 is ophi=10 & oplo=5 & F1 { F1 = 0; }
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:CPL A is ophi=3 & oplo=7 & A { A = ~A; }
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:CPL C is ophi=10 & oplo=7 & C { C = !C; }
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:CPL F0 is ophi=9 & oplo=5 & F0 { F0 = !F0; }
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:CPL F1 is ophi=11 & oplo=5 & F1 { F1 = !F1; }
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:DA A is ophi=5 & oplo=7 & A { da(A); }
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:DEC A is ophi=0 & oplo=7 & A { A = A - 1; }
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:DEC Rn is ophi=12 & Rn { Rn = Rn - 1; }
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:DIS ExtInt is ophi=1 & oplo=5 & ExtInt { disableExtInt(); }
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:DIS TCntInt is ophi=3 & oplo=5 & TCntInt { disableTCntInt(); }
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:EN ExtInt is ophi=0 & oplo=5 & ExtInt { enableExtInt(); }
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:EN TCntInt is ophi=2 & oplo=5 & TCntInt { enableTCntInt(); }
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:ENT0 Clk is ophi=7 & oplo=5 & Clk { enableClockOutput(); }
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:IN A,Pp is ophi=0 & pp!=0 & A & Pp { A = Pp; }
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:INC A is ophi=1 & oplo=7 & A { A = A + 1; }
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:INC Rni is ophi=1 & Rni { Rni = Rni + 1; }
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:INS A,Bus is ophi=0 & oplo=8 & A & Bus { A = Bus; }
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:JMPP AddrInd is ophi=11 & oplo=3 & AddrInd { goto AddrInd; }
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:MOV A,Imm is (ophi=2 & A)... & Imm { A = Imm; }
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:MOV A,Psw is ophi=12 & oplo=7 & A & Psw { getPSW(A); }
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:MOV A,Rni is ophi=15 & A & Rni { A = Rni; }
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:MOV A,Tmr is ophi=4 & oplo=2 & A & Tmr { A = getTmr(); }
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:MOV Psw,A is ophi=13 & oplo=7 & Psw & A { setPSW(A); }
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:MOV Rni,A is ophi=10 & Rni & A { Rni = A; }
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:MOV Rni,Data is ophi=11 & Rni; Data { Rni = Data; }
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:MOV Tmr,A is ophi=6 & oplo=2 & Tmr & A { setTmr(A); }
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:MOVD A,Xpp is ophi=0 & Xpp & A { A = (Xpp & 0xf); }
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:MOVD Xpp,A is ophi=3 & Xpp & A { Xpp = (A & 0xf); }
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:MOVP A,PData is ophi=10 & oplo=3 & A & PData { A = PData; }
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:MOVP3 A,P3Data is ophi=14 & oplo=3 & A & P3Data { A = P3Data; }
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:MOVX A,RiX is ophi=8 & A & RiX { A = RiX; }
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:MOVX RiX,A is ophi=9 & RiX & A { RiX = A; }
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:NOP is ophi=0 & oplo=0 { nop(); }
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:ORL A,RniI is (ophi=4 & A)... & RniI { A = A | RniI; }
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:ORL Pp,Data is ophi=8 & Pp; Data { Pp = Pp | Data; }
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:ORLD Xpp,A is ophi=8 & Xpp & A { Xpp = Xpp | (A & 0xf); }
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:OUTL Bus,A is ophi=0 & oplo=2 & Bus & A { Bus = A; }
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:OUTL Pp,A is ophi=3 & pp!=0 & Pp & A { Pp = A; }
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:RET is ophi=8 & oplo=3 { pc:2 = 0; popPC(pc); return[pc]; }
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:RETR is ophi=9 & oplo=3 { pc:2 = 0; popPCandPSW(pc); return[pc]; }
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:RL A is ophi=14 & oplo=7 & A { A = (A<<1) | (A>>7); }
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:RLC A is ophi=15 & oplo=7 & A { rotc((A&0x80)>>7, (A<<1)|C); }
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:RR A is ophi=7 & oplo=7 & A { A = (A>>1) | (A<<7); }
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:RRC A is ophi=6 & oplo=7 & A { rotc(A&1, (A>>1)|(C<<7)); }
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:SEL dfb is (ophi=14 | ophi=15) & oplo=5 & dfb { DFB = dfb; }
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:SEL bs is (ophi=12 | ophi=13) & oplo=5 & bs { setbank(bs); }
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:STOP TmrCnt is ophi=6 & oplo=5 & TmrCnt { stopTimerAndEventCounter(); }
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:STRT Cnt is ophi=4 & oplo=5 & Cnt { startEventCounter(); }
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:STRT Tmr is ophi=5 & oplo=5 & Tmr { startTimer(); }
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:SWAP A is ophi=4 & oplo=7 & A { A = (A<<4)|(A>>4); }
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:XCH A,Rni is ophi=2 & A & Rni { xch(A, Rni); }
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:XCHD A,Ri is ophi=3 & A & Ri { xch(A[0,4], Ri[0,4]); }
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:XRL A,RniI is (ophi=13 & A)... & RniI { A = A ^ RniI; }
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:ADD A,Rni is ophi=6 & A & Rni {
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add(A,A,Rni,0);
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}
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:ADD A,Imm is (ophi=0 & A)... & Imm {
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add(A,A,Imm,0);
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}
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:ADDC A,Rni is ophi=7 & A & Rni {
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add(A,A,Rni,C);
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}
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:ADDC A,Imm is (ophi=1 & A)... & Imm {
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add(A,A,Imm,C);
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}
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:ANL A,RniI is (ophi=5 & A)... & RniI {
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A = A & RniI;
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}
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:ANL Pp,Data is ophi=9 & Pp; Data {
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Pp = Pp & Data;
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}
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:ANLD Xpp,A is ophi=9 & Xpp & A {
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Xpp = Xpp & (A & 0xf);
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}
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:CLR A is ophi=2 & oplo=7 & A {
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A = 0;
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}
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:CLR C is ophi=9 & oplo=7 & C {
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C = 0;
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}
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:CLR F0 is ophi=8 & oplo=5 & F0 {
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F0 = 0;
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}
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:CLR F1 is ophi=10 & oplo=5 & F1 {
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F1 = 0;
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}
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:CPL A is ophi=3 & oplo=7 & A {
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A = ~A;
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}
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:CPL C is ophi=10 & oplo=7 & C {
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C = !C;
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}
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:CPL F0 is ophi=9 & oplo=5 & F0 {
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F0 = !F0;
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}
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:CPL F1 is ophi=11 & oplo=5 & F1 {
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F1 = !F1;
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}
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:DA A is ophi=5 & oplo=7 & A {
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da(A);
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}
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:DEC A is ophi=0 & oplo=7 & A {
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A = A - 1;
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}
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:DEC Rn is ophi=12 & Rn {
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Rn = Rn - 1;
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}
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:DIS ExtInt is ophi=1 & oplo=5 & ExtInt {
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disableExtInt();
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}
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:DIS TCntInt is ophi=3 & oplo=5 & TCntInt {
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disableTCntInt();
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}
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:EN ExtInt is ophi=0 & oplo=5 & ExtInt {
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enableExtInt();
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}
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:EN TCntInt is ophi=2 & oplo=5 & TCntInt {
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enableTCntInt();
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}
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:ENT0 Clk is ophi=7 & oplo=5 & Clk {
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enableClockOutput();
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}
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:IN A,Pp is ophi=0 & pp!=0 & A & Pp {
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A = Pp;
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}
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:INC A is ophi=1 & oplo=7 & A {
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A = A + 1;
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}
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:INC Rni is ophi=1 & Rni {
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Rni = Rni + 1;
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}
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:INS A,Bus is ophi=0 & oplo=8 & A & Bus {
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A = Bus;
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}
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:JMPP AddrInd is ophi=11 & oplo=3 & AddrInd {
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goto AddrInd;
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}
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:MOV A,Imm is (ophi=2 & A)... & Imm {
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A = Imm;
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}
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:MOV A,Psw is ophi=12 & oplo=7 & A & Psw {
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getPSW(A);
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}
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:MOV A,Rni is ophi=15 & A & Rni {
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A = Rni;
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}
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:MOV A,Tmr is ophi=4 & oplo=2 & A & Tmr {
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A = getTmr();
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}
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:MOV Psw,A is ophi=13 & oplo=7 & Psw & A {
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setPSW(A);
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}
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:MOV Rni,A is ophi=10 & Rni & A {
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Rni = A;
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}
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:MOV Rni,Data is ophi=11 & Rni; Data {
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Rni = Data;
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}
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:MOV Tmr,A is ophi=6 & oplo=2 & Tmr & A {
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setTmr(A);
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}
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:MOVD A,Xpp is ophi=0 & Xpp & A {
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A = (Xpp & 0xf);
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}
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:MOVD Xpp,A is ophi=3 & Xpp & A {
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Xpp = (A & 0xf);
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}
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:MOVP A,PData is ophi=10 & oplo=3 & A & PData {
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A = PData;
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}
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:MOVP3 A,P3Data is ophi=14 & oplo=3 & A & P3Data {
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A = P3Data;
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}
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:MOVX A,RiX is ophi=8 & A & RiX {
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A = RiX;
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}
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:MOVX RiX,A is ophi=9 & RiX & A {
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RiX = A;
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}
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:NOP is ophi=0 & oplo=0 {
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nop();
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}
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:ORL A,RniI is (ophi=4 & A)... & RniI {
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A = A | RniI;
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}
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:ORL Pp,Data is ophi=8 & Pp; Data {
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Pp = Pp | Data;
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}
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:ORLD Xpp,A is ophi=8 & Xpp & A {
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Xpp = Xpp | (A & 0xf);
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}
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:OUTL Bus,A is ophi=0 & oplo=2 & Bus & A {
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Bus = A;
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}
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:OUTL Pp,A is ophi=3 & pp!=0 & Pp & A {
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Pp = A;
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}
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:RET is ophi=8 & oplo=3 {
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pc:2 = 0; popPC(pc); return[pc];
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}
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:RETR is ophi=9 & oplo=3 {
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pc:2 = 0; popPCandPSW(pc); return[pc];
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}
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:RL A is ophi=14 & oplo=7 & A {
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A = (A<<1) | (A>>7);
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}
|
||||
:RLC A is ophi=15 & oplo=7 & A {
|
||||
rotc((A&0x80)>>7, (A<<1)|C);
|
||||
}
|
||||
:RR A is ophi=7 & oplo=7 & A {
|
||||
A = (A>>1) | (A<<7);
|
||||
}
|
||||
:RRC A is ophi=6 & oplo=7 & A {
|
||||
rotc(A&1, (A>>1)|(C<<7));
|
||||
}
|
||||
:SEL dfb is (ophi=14 | ophi=15) & oplo=5 & dfb {
|
||||
DFB = dfb;
|
||||
}
|
||||
:SEL bs is (ophi=12 | ophi=13) & oplo=5 & bs {
|
||||
setbank(bs);
|
||||
}
|
||||
:STOP TmrCnt is ophi=6 & oplo=5 & TmrCnt {
|
||||
stopTimerAndEventCounter();
|
||||
}
|
||||
:STRT Cnt is ophi=4 & oplo=5 & Cnt {
|
||||
startEventCounter();
|
||||
}
|
||||
:STRT Tmr is ophi=5 & oplo=5 & Tmr {
|
||||
startTimer();
|
||||
}
|
||||
:SWAP A is ophi=4 & oplo=7 & A {
|
||||
A = (A<<4)|(A>>4);
|
||||
}
|
||||
:XCH A,Rni is ophi=2 & A & Rni {
|
||||
xch(A, Rni);
|
||||
}
|
||||
:XCHD A,Ri is ophi=3 & A & Ri {
|
||||
xch(A[0,4], Ri[0,4]);
|
||||
}
|
||||
:XRL A,RniI is (ophi=13 & A)... & RniI {
|
||||
A = A ^ RniI;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user