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GP-2197: Added additional EMACS instructions to coldfire
This commit is contained in:
ghidorahrex
parent
947bf43cb5
commit
362bb9dfa3
@ -7,10 +7,10 @@ define space ram type=ram_space size=4 default;
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define space register type=register_space size=4;
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define register offset=0 size=4 [ D0 D1 D2 D3 D4 D5 D6 D7 ]; # Data registers
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define register offset=0 size=2 [ _ D0w _ D1w _ D2w _ D3w _ D4w _ D5w _ D6w _ D7w];
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define register offset=0 size=2 [ D0u D0w D1u D1w D2u D2w D3u D3w D4u D4w D5u D5w D6u D6w D7u D7w];
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define register offset=0 size=1 [ _ _ _ D0b _ _ _ D1b _ _ _ D2b _ _ _ D3b _ _ _ D4b _ _ _ D5b _ _ _ D6b _ _ _ D7b ];
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define register offset=0x20 size=4 [ A0 A1 A2 A3 A4 A5 A6 SP ]; # Address registers
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define register offset=0x20 size=2 [ _ A0w _ A1w _ A2w _ A3w _ A4w _ A5w _ A6w _ A7w];
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define register offset=0x20 size=2 [ A0u A0w A1u A1w A2u A2w A3u A3w A4u A4w A5u A5w A6u A6w A7u A7w];
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define register offset=0x20 size=1 [ _ _ _ A0b _ _ _ A1b _ _ _ A2b _ _ _ A3b _ _ _ A4b _ _ _ A5b _ _ _ A6b _ _ _ A7b ];
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define register offset=0x40 size=1 [ TF SVF IPL XF NF ZF VF CF ]; # Condition flags
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define register offset=0x50 size=4 PC; # Program counter register
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@ -102,6 +102,8 @@ define token instr (16)
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d8base = (0,7) signed
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@ifdef COLDFIRE
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reg03y = (0,3)
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reg03ywu = (0,3)
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reg03ywl = (0,3)
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op47 = (4,7)
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op611 = (6,11)
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op6 = (6,6)
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@ -109,6 +111,10 @@ define token instr (16)
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acclsb = (7,7)
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d911 = (9,11)
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reg315 = (3, 15)
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reg9dnu = (9,11)
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reg9dnl = (9,11)
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reg9anu = (9,11)
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reg9anl = (9,11)
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@endif
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;
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@ -151,8 +157,15 @@ define token extword (16)
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fc02 = (0,2)
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ctl = (0,11)
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@ifdef COLDFIRE
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sfact = (9,10)
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accmsb = (4,4)
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sfact = (9,10)
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accmsb = (4,4)
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reg03yu = (0,3)
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reg03yl = (0,3)
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ereg03y = (0,3)
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accw = (2,3)
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reg12x = (12,15)
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reg12xwu = (12,15)
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reg12xwl = (12,15)
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@endif
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;
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@ -298,7 +311,15 @@ attach variables [ reganb regsanb ] [ A0b A1b A2b A3b A4b A5b A6b
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attach variables [ fsrc fdst fdcos fdsin ] [ FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 ];
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@ifdef COLDFIRE
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attach variables [ reg03y ] [ D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 SP ];
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attach variables [ reg03y ereg03y reg12x ] [ D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 SP ];
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attach variables [reg03ywu reg12xwu reg03yu ] [ D0u D1u D2u D3u D4u D5u D6u D7u A0u A1u A2u A3u A4u A5u A6u A7u ];
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attach variables [reg03ywl reg12xwl reg03yl ] [ D0w D1w D2w D3w D4w D5w D6w D7w A0w A1w A2w A3w A4w A5w A6w A7w ];
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attach variables [reg9dnu] [ D0u D1u D2u D3u D4u D5u D6u D7u ];
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attach variables [reg9dnl] [ D0w D1w D2w D3w D4w D5w D6w D7w ];
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attach variables [reg9anu] [ A0u A1u A2u A3u A4u A5u A6u A7u ];
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attach variables [reg9anl] [ A0w A1w A2w A3w A4w A5w A6w A7w ];
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attach variables [accw] [ACC0 ACC1 ACC2 ACC3];
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attach values d911 [ -1 1 2 3 4 5 6 7 ];
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@endif
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@ -2515,15 +2536,24 @@ fsubrnd: "d" is fopmode=0x6c {}
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@ifdef COLDFIRE
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worl: ".w" is wl=0 {}
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worl: ".l" is wl=1 {}
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uorl7: ".l" is bs=0 {}
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uorl7: ".u" is bs=1 {}
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uorl6: ".l" is IS=0 {}
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uorl6: ".u" is IS=1 {}
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macregy: reg03ywl is reg03ywl; IS=0 { export reg03ywl; }
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macregy: reg03ywu is reg03ywu; IS=1 { export reg03ywu; }
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macregx: reg9dnl is reg9dnl & op6=0; bs=0 { export reg9dnl; }
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macregx: reg9dnu is reg9dnu & op6=0; bs=1 { export reg9dnu; }
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macregx: reg9anl is reg9anl & op6=1; bs=0 { export reg9anl; }
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macregx: reg9anu is reg9anu & op6=1; bs=1 { export reg9anu; }
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macrw: reg9dn is reg9dn & op6=0 { export reg9dn; }
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macrw: reg9an is reg9an & op6=1 { export reg9an; }
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scalefactor: "" is sfact=0 { export 0:1; }
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macregy_e: ereg03y is ereg03y { export ereg03y; }
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macregyl: reg03yl is reg03yl & IS=0 { export reg03yl; }
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macregyl: reg03yu is reg03yu & IS=1 { export reg03yu; }
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macregxl: reg12xwl is reg12xwl & bs=0 { export reg12xwl; }
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macregxl: reg12xwu is reg12xwu & bs=1 { export reg12xwu; }
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scalefactor: "" is sfact=0 { export 0:1; }
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scalefactor: "<<1" is sfact=1 { export 1:1; }
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scalefactor: ">>1" is sfact=3 { export 2:1; }
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@ -2541,20 +2571,106 @@ define pcodeop findFirstOne;
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resflags(regdn);
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}
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:mac^worl reg03y^uorl6, reg9dn^uorl7^scalefactor, accreg is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=0 & worl & uorl6 & uorl7 & scalefactor) ... & accreg ...
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# MAC effective address table
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# size=long
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m_eal: (regan) is mode=2 & regan { export *:4 regan; }
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m_eal: (regan)+ is mode=3 & regan { local tmp = regan; regan = regan + 4; export *:4 tmp; }
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m_eal: -(regan) is mode=4 & regan { regan = regan - 4; export *:4 regan; }
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m_eal: (d16,regan) is mode=5 & regan; d16 { local tmp = regan + d16; export *:4 tmp; }
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:maaac.l reg03y, reg9dn^scalefactor, accreg, accw is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ...
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{
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local tmp = reg03y * reg9dn;
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tmp = tmp << (scalefactor == 1) * 1;
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tmp = tmp >> (scalefactor == 2) * 1;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg + tmp;
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accw = accw + tmp;
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}
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:mac^worl reg03y^uorl6, reg9an^uorl7^scalefactor, accreg is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=0 & worl & uorl6 & uorl7 & scalefactor) ... & accreg ...
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:maaac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ...
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{
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local tmp = reg03y * reg9an;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg + tmp;
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accw = accw + tmp;
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}
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:maaac.w macregy, macregx^scalefactor, accreg, accw is (op=10 & op8=0 & op45=0 ; fbit=0 & wl=0 & scalefactor & accw & odsize=1) ... & macregy ... & macregx ... & accreg ...
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{
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local tmp = macregy * macregx;
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tmp = tmp << (scalefactor == 1) * 1;
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tmp = tmp >> (scalefactor == 2) * 1;
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accreg = accreg + sext(tmp);
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accw = accw + sext(tmp);
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}
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:mac.l reg03y, reg9dn^scalefactor, accreg is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor) ... & accreg ...
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{
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local tmp = reg03y * reg9dn;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg + tmp;
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}
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:mac.l reg03y, reg9an^scalefactor, accreg is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor) ... & accreg ...
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{
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local tmp = reg03y * reg9an;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg + tmp;
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}
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:mac.w macregy, macregx^scalefactor, accreg is (op=10 & op8=0 & op45=0 ; fbit=0 & wl=0 & scalefactor) ... & macregy ... & macregx ... & accreg ...
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{
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local tmp = macregy * macregx;
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tmp = tmp << (scalefactor == 1) * 1;
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tmp = tmp >> (scalefactor == 2) * 1;
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accreg = accreg + sext(tmp);
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}
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#mac with load
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:mac.w macregyl, macregxl^scalefactor, m_eal, macrw, accreg is ((op=10 & macrw & op8=0 ; macregxl & fbit=0 & macregyl & wl=0 & scalefactor) ... & accreg ...) ... & m_eal
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{
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local tmp = macregyl * macregxl;
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tmp = tmp << (scalefactor == 1) * 1;
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tmp = tmp >> (scalefactor == 2) * 1;
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accreg = accreg + sext(tmp);
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macrw = m_eal;
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}
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:mac.l macregy_e, reg12x^scalefactor, m_eal, macrw, accreg is ((op=10 & macrw & op6=0 & op8=0 ; reg12x & fbit=0 & wl=1 & scalefactor & macregy_e) ... & accreg ...) ... & m_eal
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{
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local tmp = macregy_e * reg12x;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg + tmp;
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macrw = m_eal;
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}
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:masac.l reg03y, reg9dn^scalefactor, accreg, accw is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ...
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{
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local tmp = reg03y * reg9dn;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg + tmp;
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accw = accw - tmp;
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}
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:masac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ...
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{
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local tmp = reg03y * reg9an;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg + tmp;
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accw = accw - tmp;
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}
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:masac.w macregy, macregx^scalefactor, accreg, accw is (op=10 & op8=0 & op45=0 ; fbit=0 & wl=0 & scalefactor & accw & odsize=3) ... & macregy ... & macregx ... & accreg ...
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{
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local tmp = macregy * macregx;
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tmp = tmp << (scalefactor == 1) * 1;
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tmp = tmp >> (scalefactor == 2) * 1;
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accreg = accreg + sext(tmp);
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accw = accw - sext(tmp);
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}
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moveaccreg: ACC0 is ACC0 & op0910=0 { export ACC0; }
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moveaccreg: ACC1 is ACC1 & op0910=1 { export ACC1; }
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@ -2592,20 +2708,102 @@ moveaccreg2: ACC3 is ACC3 & op01=3 { export ACC3; }
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:move.l eal, MASK is (op=10 & op611=52 & MASK & (mode=0 | mode=1 | mode=7)) ... & eal { MASK = eal; }
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:msac^worl reg03y^uorl6, reg9dn^uorl7^scalefactor, accreg is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=1 & worl & uorl6 & uorl7 & scalefactor) ... & accreg ...
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:msaac.l reg03y, reg9dn^scalefactor, accreg, accw is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ...
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{
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local tmp = reg03y * reg9dn;
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tmp = tmp << (scalefactor == 1) * 1;
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tmp = tmp >> (scalefactor == 2) * 1;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg - tmp;
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accw = accw + tmp;
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}
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:msac^worl reg03y^uorl6, reg9an^uorl7^scalefactor, accreg is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & worl & uorl6 & uorl7 & scalefactor) ... & accreg ...
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:msaac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ...
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{
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local tmp = reg03y * reg9an;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg - tmp;
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accw = accw + tmp;
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}
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:msaac.w macregy, macregx^scalefactor, accreg, accw is (op=10 & op8=0 & op45=0 ; fbit=1 & wl=0 & scalefactor & accw & odsize=1) ... & macregy ... & macregx ... & accreg ...
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{
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local tmp = macregy * macregx;
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tmp = tmp << (scalefactor == 1) * 1;
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tmp = tmp >> (scalefactor == 2) * 1;
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accreg = accreg - sext(tmp);
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accw = accw + sext(tmp);
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}
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:msac.l reg03y, reg9dn^scalefactor, accreg is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor) ... & accreg ...
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{
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local tmp = reg03y * reg9dn;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg - tmp;
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}
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:msac.l reg03y, reg9an^scalefactor, accreg is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor) ... & accreg ...
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{
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local tmp = reg03y * reg9an;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg - tmp;
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}
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:msac.w macregy, macregx^scalefactor, accreg is (op=10 & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=0 & scalefactor) ... & macregy ... & macregx ... & accreg ...
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{
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local tmp = macregy * macregx;
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tmp = tmp << (scalefactor == 1) * 1;
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tmp = tmp >> (scalefactor == 2) * 1;
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accreg = accreg - sext(tmp);
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}
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# MSAC with load
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:msac.w macregyl, macregxl^scalefactor, m_eal, macrw, accreg is ((op=10 & macrw & op8=0 ; macregxl & fbit=1 & macregyl & wl=0 & scalefactor) ... & accreg ...) ... & m_eal
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{
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local tmp = macregyl * macregxl;
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tmp = tmp << (scalefactor == 1) * 1;
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tmp = tmp >> (scalefactor == 2) * 1;
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accreg = accreg - sext(tmp);
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macrw = m_eal;
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}
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:msac.l macregy_e, reg12x^scalefactor, m_eal, macrw, accreg is ((op=10 & macrw & op8=0 ; reg12x & fbit=1 & wl=1 & scalefactor & macregy_e) ... & accreg ...) ... & m_eal
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{
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local tmp = macregy_e * reg12x;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg - tmp;
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macrw = m_eal;
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}
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:msaac.l reg03y, reg9dn^scalefactor, accreg, accw is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ...
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{
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local tmp = reg03y * reg9dn;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg - tmp;
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accw = accw - tmp;
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}
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:mssac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ...
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{
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local tmp = reg03y * reg9an;
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tmp = tmp << (scalefactor == 1);
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tmp = tmp >> (scalefactor == 2);
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accreg = accreg - tmp;
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accw = accw - tmp;
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}
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:mssac.w macregy, macregx^scalefactor, accreg, accw is (op=10 & op8=0 & op45=0 ; fbit=1 & wl=0 & scalefactor & accw & odsize=3) ... & macregy ... & macregx ... & accreg ...
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{
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local tmp = macregy * macregx;
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tmp = tmp << (scalefactor == 1) * 1;
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tmp = tmp >> (scalefactor == 2) * 1;
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accreg = accreg - sext(tmp);
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accw = accw - sext(tmp);
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}
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@endif
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