From 1e109f94741ce841e544a23d74bc84e7325e5749 Mon Sep 17 00:00:00 2001
From: ghidorahrex <ghidorahrex@users.noreply.github.com>
Date: Mon, 10 May 2021 10:30:10 -0400
Subject: [PATCH] Added Z flag updates for shift instructions. Added missing
 PIC16 instructions

---
 .../data/languages/pic16_instructions.sinc    | 33 ++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc b/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc
index 28e07a0d9e..208d738309 100644
--- a/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc
+++ b/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc
@@ -287,7 +287,7 @@ trisREG: "7"	is l5=7												{ local trl:2 = 0x10E; export *[DATA]:1 trl; } #
 
 @if PROCESSOR == "PIC_16F"
 
-:ADD^fsrk sk6	is op7=0x62 & fsrk & sk6 {
+:ADDFSR fsrk, sk6	is op7=0x62 & fsrk & sk6 {
 	fsrk = fsrk + sk6;
 }
 @endif
@@ -384,6 +384,15 @@ trisREG: "7"	is l5=7												{ local trl:2 = 0x10E; export *[DATA]:1 trl; } #
 	destREG = val;
 }
 
+:ASRF srcREG, D				is op6=0x37 & srcREG & D & destREG					{
+	#  --11 0111 dfff ffff
+	$(C) = srcREG & 0x1;
+	val:1 = srcREG s>> 1;
+	setResultFlags(val);
+	destREG = val;
+	
+}
+
 :BCF srcREG, bit			is op4=0x4 & srcREG & bit							{
 	#  --01 00bb bfff ffff
 	#  0001 0010 0000 0000	->	BCF INDF, #0x4
@@ -612,6 +621,12 @@ trisREG: "7"	is l5=7												{ local trl:2 = 0x10E; export *[DATA]:1 trl; } #
 	call [absAddr11];
 }
 
+:CALLW					is op14=0x000a						{
+	#  --00 0000 0000 1010
+	push(&:2 inst_next);
+	call [W];
+}
+	
 :CLRF srcREG				is op6=0x01 & d=1 & srcREG						{
 	#  --00 0001 1fff ffff
 	#  0000 0001 1000 0000	->	CLRF INDF
@@ -735,6 +750,22 @@ srcFSRk: sk6"["fsrk"]" is fsrk & sk6 {
 	addr:2 = fsrk + sk6; export *[DATA]:1 addr;
 }
 
+:LSLF srcREG, D				is op6=0x35 & srcREG & D & destREG					{
+	#  --11 0111 dfff ffff
+	$(C) = (srcREG & 80) != 0;
+	val:1 = srcREG << 1;
+	setResultFlags(val);
+	destREG = val;
+}
+
+:LSRF srcREG, D				is op6=0x36 & srcREG & D & destREG					{
+	#  --11 0111 dfff ffff
+	$(C) = srcREG & 0x1;
+	val:1 = srcREG >> 1;
+	setResultFlags(val);
+	destREG = val;
+}
+
 :MOVIW srcFSR			is op11=2 & srcFSR {
 	W = srcFSR;
 	setResultFlags(W);