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Merge remote-tracking branch 'origin/patch'

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ghidra1 2022-07-26 18:20:51 -04:00
commit 0590f9336e
3 changed files with 13 additions and 3 deletions
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2
Ghidra/Configurations/Public_Release/src/global/docs/ChangeHistory.html
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@ -14,6 +14,7 @@
<li><I>Processors</I>. Added HC-12 processor support with a Flat 16-bit memory model by splitting HCS12X into HC-12, HCS-12, and HCS-12X processors. (GP-1716, Issue #1570, #4016)</li>
<li><I>Processors</I>. Added ability to specify byte-mapped and overlay memory blocks from processor specification (*.pspec). (GP-2133, Issue #2703)</li>
<li><I>Processors</I>. Added PowerPC e500 processor variant. (GP-2272)</li>
<li><I>Processors</I>. Added support for AARCH64 ilp32 variant. (GP-2355)</li>
</ul>
</blockquote>
<blockquote><p><u>Bugs</u></p>
@ -37,7 +38,6 @@
<li><I>Multi-User:Merge</I>. Corrected long-standing regression bug affecting datatype merge, which was introduced in Ghidra 9.2. This severe error could surface during a datatype conflict merge with a shared project and could prevent a check-in to a Ghidra Server repository. (GP-2066)</li>
<li><I>Processors</I>. Refactored AVR8 to handle 24-bit memory and to correctly index the code address space as a byte or word. (GP-2213, Issue #4333)</li>
<li><I>Processors</I>. ELF PLT import processing changed to avoid static disassembly for ARM/MIPS due to possibility of alternative instruction set. Now relies on disassembly during analysis for such cases. (GP-2256)</li>
<li><I>Processors</I>. Added support for AARCH64 ilp32 variant. (GP-2355)</li>
<li><I>Scripting</I>. Creating a new script via the Script Manager now properly handles the situation where the <B>$HOME/ghidra_scripts</B> directory does not exist. (GP-2282)</li>
<li><I>Sleigh</I>. Fixed a Sleigh Parser threading issue that could cause incorrect p-code generation for languages that use delay slots. (GP-2235, Issue #4332)</li>
</ul>

8
Ghidra/Processors/AARCH64/data/aarch64-pltThunks.xml
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@ -12,4 +12,12 @@
0x20 0x02 0x1f 0xd6 # br x17
</data>
</pattern>
<pattern>
<data> <!-- AARCH64 ELF32 PLT -->
...10000 0x.. 0x.. 1..10000 # adrp x16, PLTGOT + n * 4
0x11 ......10 01...... 0xb9 # ldr x17, [x16, PLTGOT + n * 4]
0x10 ......10 00...... 0x11 # add x16, x16, :lo12:PLTGOT + n * 4
0x20 0x02 0x1f 0xd6 # br x17
</data>
</pattern>
</patternlist>

6
Ghidra/Processors/MIPS/data/languages/mips.sinc
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@ -800,14 +800,16 @@ DXuPos: pos is lsb [ pos = lsb + 32; ] { tmp:1
DinsXSize: mysize is msbd & lsb [ mysize = msbd - lsb + 1 + 32; ] { tmp:1 = mysize; export tmp; }
@endif
@ifdef ISA_VARIANT
macro JXWritePC(addr) {
@ifdef ISA_VARIANT
ISAModeSwitch = (addr & 0x1) != 0;
tmp:$(REGSIZE) = -2;
tmp = tmp & addr;
pc = tmp;
}
@else
pc=addr;
@endif
}
# Floating point formats
#fmt: "S" is format=0x10 { }