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cf50244181
...plus some cleanups and debug improvements (single-step mode) All tests specified in test.sh now pass! This pretty much means full compliance with the RV32I base spec, M and A extensions, as well as correct machine, supervisor and user mode traps/switches. Next up is the SV32 MMU and external devices (UART, CLINT timer).
10 lines
277 B
Plaintext
10 lines
277 B
Plaintext
[submodule "riscv-opcodes"]
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path = riscv-opcodes
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url = https://github.com/riscv/riscv-opcodes
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[submodule "riscv-tests"]
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path = riscv-tests
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url = https://github.com/riscv/riscv-tests
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[submodule "riscv-rust"]
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path = riscv-rust
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url = https://github.com/takahirox/riscv-rust
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