6 Commits

Author	SHA1	Message	Date
pi	1b74a7a85d	update buildroot to 2022	2022-11-25 23:09:11 +01:00
Stefan	b11654cbc9	add micropython with riscv32 port	2021-08-17 09:49:37 +02:00
Stefan	cb6d05178b	add MMU support (SV32) and fix a bunch of bugs	2021-08-17 09:31:46 +02:00
Stefan	ed82c5487f	implement UART, CLINT, device tree, opensbi build ... ...plus some comfort improvements, more testing. This now successfully boots OpenSBI when built like specified in the Makefile!	2021-06-03 22:45:13 +02:00
Stefan	cf50244181	support for all necessary CSRs, privilege modes, traps, atomics ... ...plus some cleanups and debug improvements (single-step mode) All tests specified in test.sh now pass! This pretty much means full compliance with the RV32I base spec, M and A extensions, as well as correct machine, supervisor and user mode traps/switches. Next up is the SV32 MMU and external devices (UART, CLINT timer).	2021-05-28 19:02:11 +02:00
Stefan	64e2d0b45c	initial commit ... passes all RV32IM tests (run './test.sh all') instructions.txt is extracted from takahirox/riscv-rust	2021-05-28 15:10:51 +02:00