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3); + RunPerlPP(FilesToWatch[i], gen); + AssetDatabase.ImportAsset(gen); + } + else + { + AssetDatabase.ImportAsset(FilesToWatch[i]); + } + } + } + } + + static void RunPerlPP(string input, string output) + { + Debug.Log("[AutoImport] Running perlpp in " + System.Environment.CurrentDirectory); + + var args = $"/C {PathToPerlPP} -o {output} {input}"; + var p = new System.Diagnostics.Process + { + StartInfo = new System.Diagnostics.ProcessStartInfo( + @"cmd.exe", + args + ) + { + WorkingDirectory = System.Environment.CurrentDirectory, + UseShellExecute = false, + RedirectStandardOutput = true, + RedirectStandardError = true + } + }; + p.Start(); + p.WaitForExit(); + Debug.Log("[AutoImport] perlpp out: " + p.StandardOutput.ReadToEnd()); + Debug.Log("[AutoImport] perlpp err: " + p.StandardError.ReadToEnd()); + } +} +#endif \ No newline at end of file diff --git a/_Nix/AutoImport.cs.meta b/_Nix/AutoImport.cs.meta new file mode 100755 index 00000000..ab1f5d75 --- /dev/null +++ b/_Nix/AutoImport.cs.meta @@ -0,0 +1,11 @@ +fileFormatVersion: 2 +guid: 6bdc17426a56c254e8feaccdd271248d +MonoImporter: + externalObjects: {} + serializedVersion: 2 + defaultReferences: [] + executionOrder: 0 + icon: {instanceID: 0} + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/NixControl.asset b/_Nix/NixControl.asset new file mode 100755 index 00000000..c47d8578 --- /dev/null +++ b/_Nix/NixControl.asset @@ -0,0 +1,1023 @@ +%YAML 1.1 +%TAG !u! tag:unity3d.com,2011: +--- !u!114 &11400000 +MonoBehaviour: + m_ObjectHideFlags: 0 + m_CorrespondingSourceObject: {fileID: 0} + m_PrefabInstance: {fileID: 0} + m_PrefabAsset: {fileID: 0} + m_GameObject: {fileID: 0} + m_Enabled: 1 + m_EditorHideFlags: 0 + m_Script: {fileID: 11500000, guid: c333ccfdd0cbdbc4ca30cef2dd6e6b9b, type: 3} + m_Name: NixControl + m_EditorClassIdentifier: + serializedUdonProgramAsset: {fileID: 11400000, guid: 0edd87c6e79dba24aa89cd0adf6c16ef, + type: 2} + udonAssembly: + assemblyError: + sourceCsScript: {fileID: 11500000, guid: 32d551b771daedb4980227a82dc09b45, type: 3} + behaviourSyncMode: 0 + behaviourIDHeapVarName: __refl_const_intnl_udonTypeID + compileErrors: [] + hasInteractEvent: 0 + serializationData: + SerializedFormat: 2 + SerializedBytes: + ReferencedUnityObjects: + - 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"reset/load" : "running"; + StatusText.text = $"State: {stateT}\n"; + if (run) + { + var ticks = (int)TickSlider.value; + var fpsCol = fps < 40 ? "red" : "green"; + StatusText.text += $"{ticks} (ticks) * " + + $"{fps} (UPS/FPS) = {ticks * fps} IPS"; + } + + // DEBUG + // CRT.material.SetInt("_DoTick", CRT.material.GetInt("_DoTick") + 1); + } + + public void DialEnable() + { + var state = (int)Dial.GetProgramVariable("NextState"); + run = state == 1; + + if (!run) + { + CurProgram.ApplyTexture(); + CRT.material.SetInt("_DoTick", 1); + CRT.material.SetInt("_Init", 1); + Debug.SetProgramVariable("RenderCam", false); + Debug.SetProgramVariable("UartPtr", 0); + Debug.SetProgramVariable("UartTag", 0); + Debug.SetProgramVariable("newlines", 0); + Debug.SetProgramVariable("linelength", 0); + Debug.SetProgramVariable("LocalText", ""); + CRT.material.SetInt("_UdonUARTInChar", 0); + CRT.material.SetInt("_UdonUARTInTag", 0); + CRT.material.SetInt("_UdonUARTPtr", 0); + UartOut.text = ""; + Keyboard.queue = ""; + CRT.updateMode = CustomRenderTextureUpdateMode.OnDemand; + } + else + { + CurProgram.ApplyTexture(); + Debug.SetProgramVariable("RenderCam", true); + CRT.material.SetInt("_Init", 1); + disableInit = 2; + CRT.material.SetInt("_DoTick", 0); + CRT.updateMode = CustomRenderTextureUpdateMode.Realtime; + } + } + + public void TickSliderChange() + { + CRT.material.SetInt("_Ticks", (int)TickSlider.value); + } + + public void ProgramSelectChanged() + { + CurProgram.TurnOff(); + CurProgram = Programs[ProgramSelect.value]; + CurProgram.TurnOn(); + CurProgram.ApplyTexture(); + } +} diff --git a/_Nix/NixControl.cs.meta b/_Nix/NixControl.cs.meta new file mode 100755 index 00000000..60160a00 --- /dev/null +++ b/_Nix/NixControl.cs.meta @@ -0,0 +1,11 @@ +fileFormatVersion: 2 +guid: 32d551b771daedb4980227a82dc09b45 +MonoImporter: + externalObjects: {} + serializedVersion: 2 + defaultReferences: [] + executionOrder: 0 + icon: {instanceID: 0} + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/NixDebug.asset b/_Nix/NixDebug.asset new file mode 100755 index 00000000..d9a8efdf --- /dev/null +++ b/_Nix/NixDebug.asset @@ -0,0 +1,1682 @@ +%YAML 1.1 +%TAG !u! tag:unity3d.com,2011: +--- !u!114 &11400000 +MonoBehaviour: + m_ObjectHideFlags: 0 + m_CorrespondingSourceObject: {fileID: 0} + m_PrefabInstance: {fileID: 0} + m_PrefabAsset: {fileID: 0} + m_GameObject: {fileID: 0} + m_Enabled: 1 + m_EditorHideFlags: 0 + m_Script: {fileID: 11500000, guid: c333ccfdd0cbdbc4ca30cef2dd6e6b9b, type: 3} + m_Name: NixDebug + m_EditorClassIdentifier: + serializedUdonProgramAsset: {fileID: 11400000, guid: 3032e288f79bb15498c860f35c9037a0, + type: 2} + udonAssembly: + assemblyError: + sourceCsScript: {fileID: 11500000, guid: 71e2d556b88cc8247b0e36e78a72e458, type: 3} + behaviourSyncMode: 0 + behaviourIDHeapVarName: __refl_const_intnl_udonTypeID + compileErrors: [] + hasInteractEvent: 0 + serializationData: + SerializedFormat: 2 + SerializedBytes: + ReferencedUnityObjects: + - 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(int)newUartPtrRaw : 0; + + if (EnableToggle.isOn) { + // Enter single step mode when breakpoint detected + var dbgTick = load_debug_do_tick(); + if (dbgTick == 0xffffffffU) { + vm_mat.SetInt("_DoTick", 1); + } + + // var load_debug_arb_0x = load_debug_arb_0(); + // var load_debug_arb_1x = load_debug_arb_1(); + // var load_debug_arb_2x = load_debug_arb_2(); + // var load_debug_arb_3x = load_debug_arb_3(); + // var load_debug_arb_4x = load_debug_arb_4(); + // var load_debug_arb_5x = load_debug_arb_5(); + // var load_debug_arb_6x = load_debug_arb_6(); + // var load_debug_arb_7x = load_debug_arb_7(); + + var pc = load_pc(); + + DbgText.text = $@"stats: +pc : 0x{pc.ToString("X8")} +instr. : 0x{load_debug_last_ins().ToString("X8")} +clock : {load_clock()} +stall : {load_debug_last_stall()} +#stall : {load_stall_count()} +#trap : {load_trap_count()} +#commit : {load_commits()} +priv. : {load_csr__privilege()} +uartptr : {UartPtr.ToString("X2")}/{newUartPtr.ToString("X2")} +mstatus : 0x{load_csr(0x300).ToString("X8")} +dbgtick : {dbgTick} +dbgarb0 : {load_debug_arb_0()}" +/*chkcsr : 0x{load_debug_csr_val().ToString("X8")}" +/*chkmem : 0x{load_debug_mem_val().ToString("X8")}*/ + $@" + + + +zz=0x{load_xreg0().ToString("X8")} ra=0x{load_xreg1().ToString("X8")} sp=0x{load_xreg2().ToString("X8")} gp=0x{load_xreg3().ToString("X8")} +tp=0x{load_xreg4().ToString("X8")} t0=0x{load_xreg5().ToString("X8")} t1=0x{load_xreg6().ToString("X8")} t2=0x{load_xreg7().ToString("X8")} +fp=0x{load_xreg8().ToString("X8")} s1=0x{load_xreg9().ToString("X8")} a0=0x{load_xreg10().ToString("X8")} a1=0x{load_xreg11().ToString("X8")} +a2=0x{load_xreg12().ToString("X8")} a3=0x{load_xreg13().ToString("X8")} a4=0x{load_xreg14().ToString("X8")} a5=0x{load_xreg15().ToString("X8")} +a6=0x{load_xreg16().ToString("X8")} a7=0x{load_xreg17().ToString("X8")} s2=0x{load_xreg18().ToString("X8")} s3=0x{load_xreg19().ToString("X8")} +s4=0x{load_xreg20().ToString("X8")} s5=0x{load_xreg21().ToString("X8")} s6=0x{load_xreg22().ToString("X8")} s7=0x{load_xreg23().ToString("X8")} +s8=0x{load_xreg24().ToString("X8")} s9=0x{load_xreg25().ToString("X8")} 10=0x{load_xreg26().ToString("X8")} 11=0x{load_xreg27().ToString("X8")} +t3=0x{load_xreg28().ToString("X8")} t4=0x{load_xreg29().ToString("X8")} t5=0x{load_xreg30().ToString("X8")} t6=0x{load_xreg31().ToString("X8")}" +/* +arb0=0x{load_debug_arb_0x.ToString("X8")} arb1=0x{load_debug_arb_1x.ToString("X8")} arb2=0x{load_debug_arb_2x.ToString("X8")} arb3=0x{load_debug_arb_3x.ToString("X8")} +arb4=0x{load_debug_arb_4x.ToString("X8")} arb5=0x{load_debug_arb_5x.ToString("X8")} arb6=0x{load_debug_arb_6x.ToString("X8")} arb7=0x{load_debug_arb_7x.ToString("X8")}*/ + $@" + +"; + + // ARB=0x{(load_debug_arb_0x ^ load_debug_arb_1x ^ load_debug_arb_2x ^ load_debug_arb_3x ^ load_debug_arb_4x ^ load_debug_arb_5x ^ load_debug_arb_6x ^ load_debug_arb_7x ^ pc).ToString("X8")} + } + + var changed = false; + while (newUartPtr != UartPtr) { + UartPtr++; + if (UartPtr == UART_BUFFER_SIZE) { UartPtr = 0; } + var tmp = getUartBuffer(UartPtr); + if (tmp == 0) continue; + + if (tmp == 8) { // backspace + if (linelength == 0) { + linelength = 79; + newlines--; + } else { + linelength--; + } + LocalText = LocalText.Substring(0, LocalText.Length - 1); + changed = true; + continue; + } + + // Basic ANSI escape support + // TODO: implement correctly... + if (tmp == 27) { // ASCII ESC + ansi_escape_sm = ANSI_SM_ESC_RECEIVED; + continue; + } + + if (ansi_escape_sm == ANSI_SM_ESC_RECEIVED) { + if (tmp == ((int)'[')) { + ansi_escape_sm = ANSI_SM_CTRL_RECEIVED; + } else { + ansi_escape_sm = ANSI_SM_NONE; + } + continue; + } + + if (ansi_escape_sm == ANSI_SM_CTRL_RECEIVED) { + if (tmp >= 0x20 && tmp <= 0x3F) { + // data, ignored for now + } else { + // termination (or invalid) + ansi_escape_sm = ANSI_SM_NONE; + } + continue; + } + + var c = (char)tmp; + LocalText += c; + changed = true; + if (c == '\n') { + newlines++; + linelength = 0; + } else { + linelength++; + if (linelength >= 80) { + linelength = 0; + newlines++; + LocalText += '\n'; + } + } + if (newlines > 30) { + LocalText = LocalText.Substring(LocalText.IndexOf('\n') + 1); + newlines--; + } + } + vm_mat.SetInt("_UdonUARTPtr", UartPtr); + + if (Networking.LocalPlayer.isMaster && changed) { + MasterText = LocalText; + this.RequestSerialization(); + MasterTextbox.text = MasterText; + } + + var caretStr = caret ? "█" : ""; + caret = !caret; + UartOut.text = LocalText + caretStr; + + var curTag = load_uart__input_tag(); + if (curTag == UartTag) { + Keyboard.CharToVM(); + } + + // DEBUG + + //Debug.Log("TRACE: 0x" + load_debug_last_ins().ToString("X8") + " @ " + load_pc().ToString("X8")); + + // Debug.Log("TEST begin"); + // int prev = -1; + // for (int i = 0; i < 256; i++) { + // px = decodePackedColor(i % 128, i / 128); + // if (px[0] != prev + 1) { + // Debug.Log("DISCREPANCY! @" + i + " got: " + px[0] + " wanted: " + (prev + 1) + " dbg: " + prev2); + // } + // prev = (int)px[0]; + // } + // Debug.Log("TEST done"); + } + + public bool RenderCam = false; + void Update() + { + if (cam.enabled) + { + cam.enabled = false; + } + + lastUpdate--; + if (lastUpdate <= 0) + { + cam.enabled = RenderCam; + lastUpdate = UpdateEveryXFrames; + } + } + + public override void OnDeserialization() + { + MasterTextbox.text = MasterText; + } + + // auto-generated in 'types.h': + + #region LOAD + private const int UART_BUFFER_SIZE = 64; + private int[] addr_lin(int lin) { + int[] ret = new int[3]; + ret[2] = lin & 0x3; // c + lin = lin >> 2; + ret[0] = lin % 128; // x + ret[1] = lin / 128; // y + return ret; + } + private uint load_csr__privilege() { return decodePackedData(48, 0, 2); } + private uint load_uart__rbr_thr_ier_iir() { return decodePackedData(48, 0, 3); } + private uint load_uart__lcr_mcr_lsr_scr() { return decodePackedData(49, 0, 0); } + private uint load_uart__thre_ip() { return decodePackedData(49, 0, 1); } + private uint load_uart__interrupting() { return decodePackedData(49, 0, 2); } + private uint load_uart__input_tag() { return decodePackedData(49, 0, 3); } + private uint load_clint__msip() { return decodePackedData(50, 0, 0); } + private uint load_clint__mtimecmp_lo() { return decodePackedData(50, 0, 1); } + private uint load_clint__mtimecmp_hi() { return decodePackedData(50, 0, 2); } + private uint load_clint__mtime_lo() { return decodePackedData(50, 0, 3); } + private uint load_clint__mtime_hi() { return decodePackedData(51, 0, 0); } + private uint load_uart_buffer__ptr() { return decodePackedData(51, 0, 1); } + private uint load_mmu__mode() { return decodePackedData(67, 0, 2); } + private uint load_mmu__ppn() { return decodePackedData(67, 0, 3); } + private uint load_stall() { return decodePackedData(68, 0, 0); } + private uint load_clock() { return decodePackedData(68, 0, 1); } + private uint load_commits() { return decodePackedData(68, 0, 2); } + private uint load_xreg0() { return decodePackedData(68, 0, 3); } + private uint load_xreg1() { return decodePackedData(69, 0, 0); } + private uint load_xreg2() { return decodePackedData(69, 0, 1); } + private uint load_xreg3() { return decodePackedData(69, 0, 2); } + private uint load_xreg4() { return decodePackedData(69, 0, 3); } + private uint load_xreg5() { return decodePackedData(70, 0, 0); } + private uint load_xreg6() { return decodePackedData(70, 0, 1); } + private uint load_xreg7() { return decodePackedData(70, 0, 2); } + private uint load_xreg8() { return decodePackedData(70, 0, 3); } + private uint load_xreg9() { return decodePackedData(71, 0, 0); } + private uint load_xreg10() { return decodePackedData(71, 0, 1); } + private uint load_xreg11() { return decodePackedData(71, 0, 2); } + private uint load_xreg12() { return decodePackedData(71, 0, 3); } + private uint load_xreg13() { return decodePackedData(72, 0, 0); } + private uint load_xreg14() { return decodePackedData(72, 0, 1); } + private uint load_xreg15() { return decodePackedData(72, 0, 2); } + private uint load_xreg16() { return decodePackedData(72, 0, 3); } + private uint load_xreg17() { return decodePackedData(73, 0, 0); } + private uint load_xreg18() { return decodePackedData(73, 0, 1); } + private uint load_xreg19() { return decodePackedData(73, 0, 2); } + private uint load_xreg20() { return decodePackedData(73, 0, 3); } + private uint load_xreg21() { return decodePackedData(74, 0, 0); } + private uint load_xreg22() { return decodePackedData(74, 0, 1); } + private uint load_xreg23() { return decodePackedData(74, 0, 2); } + private uint load_xreg24() { return decodePackedData(74, 0, 3); } + private uint load_xreg25() { return decodePackedData(75, 0, 0); } + private uint load_xreg26() { return decodePackedData(75, 0, 1); } + private uint load_xreg27() { return decodePackedData(75, 0, 2); } + private uint load_xreg28() { return decodePackedData(75, 0, 3); } + private uint load_xreg29() { return decodePackedData(76, 0, 0); } + private uint load_xreg30() { return decodePackedData(76, 0, 1); } + private uint load_xreg31() { return decodePackedData(76, 0, 2); } + private uint load_pc() { return decodePackedData(76, 0, 3); } + private uint load_reservation_en() { return decodePackedData(77, 0, 0); } + private uint load_reservation_addr() { return decodePackedData(77, 0, 1); } + private uint load_memop_src_v() { return decodePackedData(77, 0, 2); } + private uint load_memop_dst_v() { return decodePackedData(77, 0, 3); } + private uint load_memop_src_p() { return decodePackedData(78, 0, 0); } + private uint load_memop_dst_p() { return decodePackedData(78, 0, 1); } + private uint load_memop_n() { return decodePackedData(78, 0, 2); } + private uint load_stall_count() { return decodePackedData(78, 0, 3); } + private uint load_trap_count() { return decodePackedData(79, 0, 0); } + private uint load_debug_do_tick() { return decodePackedData(79, 0, 1); } + private uint load_debug_last_ins() { return decodePackedData(79, 0, 2); } + private uint load_debug_last_stall() { return decodePackedData(79, 0, 3); } + private uint load_debug_arb_0() { return decodePackedData(80, 0, 0); } + private uint load_csr(int addr) { + int lin = (addr >> 2) + 324; + return decodePackedData(lin % 128, lin / 128, addr & 0x3); + } + private uint getUartBuffer(int idx) { + + int lin = idx + 206; + int[] acc = addr_lin(lin); + return decodePackedData(acc[0], acc[1], acc[2]); + } + #endregion +} diff --git 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("Framebuffer height (chars)", Int) = 60 + + _Atlas_Width ("Atlas width (chars)", Int) = 64 + _Atlas_Height ("Atlas height (chars)", Int) = 8 + + _CharBorder ("Character Border", Range(0, 1)) = 0.1 + } + SubShader + { + Tags { "RenderType"="Opaque" } + Cull Off + Blend One Zero + + Pass + { + CGPROGRAM + #pragma target 5.0 + #pragma vertex vert + #pragma fragment frag + + #include "UnityCG.cginc" + + float4 _BGColor, _FGColor; + sampler2D _Font; + Texture2D _RVC; + #define STATE_TEX _RVC + uint _FB_Width, _FB_Height; + uint _Atlas_Width, _Atlas_Height; + float _CharBorder; + + #include "helpers.cginc" + #include "src/types.h" + + struct appdata + { + float4 vertex : POSITION; + float2 uv : TEXCOORD0; + }; + + v2f vert (appdata v) + { + v2f o; + o.vertex = UnityObjectToClipPos(v.vertex); + o.uv = v.uv; + return o; + } + + static uint2 s_dim; + + float4 frag(v2f i) : SV_Target { + STATE_TEX.GetDimensions(s_dim.x, s_dim.y); + + uint2 fb_idx = uint2(_FB_Width * i.uv.x, _FB_Height * i.uv.y); + float2 char_pos = frac(i.uv * float2(_FB_Width, _FB_Height)); + + char_pos *= 1.0 + _CharBorder; + char_pos -= _CharBorder * 0.5; + + if (char_pos.x < 0.04 || char_pos.y < 0.04 || char_pos.x > 0.96 || char_pos.y > 0.96) + return _BGColor; + + /* uint c = get_fb_char(fb_idx); */ + uint c = '7'; + + float2 atlas_offset = float2(c % _Atlas_Width, (c / _Atlas_Width) + 1) * + float2(1.0/_Atlas_Width, 1.0/_Atlas_Height); + atlas_offset.y = 1 - atlas_offset.y; + float2 true_uv = atlas_offset + (char_pos * float2(1.0/_Atlas_Width, 1.0/_Atlas_Height)); + + float4 font_mask = tex2D(_Font, true_uv); + + return lerp(_BGColor, _FGColor, font_mask.r); + } + ENDCG + } + } +} diff --git a/_Nix/rvc/console.shader.meta b/_Nix/rvc/console.shader.meta new file mode 100755 index 00000000..3aa289e0 --- /dev/null +++ b/_Nix/rvc/console.shader.meta @@ -0,0 +1,9 @@ +fileFormatVersion: 2 +guid: d796569aa1de841459cda4c17737c5cc +ShaderImporter: + externalObjects: {} + defaultTextures: [] + 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Copyright (c) 2016 Unity Technologies. MIT license (see license.txt) +// modified: change _SelfTexture2D to Texture2D, from sampler2D + +#ifndef UNITY_CUSTOM_TEXTURE_INCLUDED +#define UNITY_CUSTOM_TEXTURE_INCLUDED + +#include "UnityCG.cginc" +#include "UnityStandardConfig.cginc" + +// Keep in sync with CustomRenderTexture.h +#define kCustomTextureBatchSize 16 + +struct appdata_customrendertexture +{ + uint vertexID : SV_VertexID; +}; + +// User facing vertex to fragment shader structure +struct v2f_customrendertexture +{ + float4 vertex : SV_POSITION; + float3 localTexcoord : TEXCOORD0; // Texcoord local to the update zone (== globalTexcoord if no partial update zone is specified) + float3 globalTexcoord : TEXCOORD1; // Texcoord relative to the complete custom texture + uint primitiveID : TEXCOORD2; // Index of the update zone (correspond to the index in the updateZones of the Custom Texture) + float3 direction : TEXCOORD3; // For cube textures, direction of the pixel being rendered in the cubemap +}; + +float2 CustomRenderTextureRotate2D(float2 pos, float angle) +{ + float sn = sin(angle); + float cs = cos(angle); + + return float2( pos.x * cs - pos.y * sn, pos.x * sn + pos.y * cs); +} + +// Internal +float4 CustomRenderTextureCenters[kCustomTextureBatchSize]; +float4 CustomRenderTextureSizesAndRotations[kCustomTextureBatchSize]; +float CustomRenderTexturePrimitiveIDs[kCustomTextureBatchSize]; + +float4 CustomRenderTextureParameters; +#define CustomRenderTextureUpdateSpace CustomRenderTextureParameters.x // Normalized(0)/PixelSpace(1) +#define CustomRenderTexture3DTexcoordW CustomRenderTextureParameters.y +#define CustomRenderTextureIs3D CustomRenderTextureParameters.z + +// User facing uniform variables +float4 _CustomRenderTextureInfo; // x = width, y = height, z = depth, w = face/3DSlice + +// Helpers +#define _CustomRenderTextureWidth _CustomRenderTextureInfo.x +#define _CustomRenderTextureHeight _CustomRenderTextureInfo.y +#define _CustomRenderTextureDepth _CustomRenderTextureInfo.z + +// Those two are mutually exclusive so we can use the same slot +#define _CustomRenderTextureCubeFace _CustomRenderTextureInfo.w +#define _CustomRenderTexture3DSlice _CustomRenderTextureInfo.w + +Texture2D _SelfTexture2D; +samplerCUBE _SelfTextureCube; +sampler3D _SelfTexture3D; + +float3 CustomRenderTextureComputeCubeDirection(float2 globalTexcoord) +{ + float2 xy = globalTexcoord * 2.0 - 1.0; + float3 direction; + if(_CustomRenderTextureCubeFace == 0.0) + { + direction = normalize(float3(1.0, -xy.y, -xy.x)); + } + else if(_CustomRenderTextureCubeFace == 1.0) + { + direction = normalize(float3(-1.0, -xy.y, xy.x)); + } + else if(_CustomRenderTextureCubeFace == 2.0) + { + direction = normalize(float3(xy.x, 1.0, xy.y)); + } + else if(_CustomRenderTextureCubeFace == 3.0) + { + direction = normalize(float3(xy.x, -1.0, -xy.y)); + } + else if(_CustomRenderTextureCubeFace == 4.0) + { + direction = normalize(float3(xy.x, -xy.y, 1.0)); + } + else if(_CustomRenderTextureCubeFace == 5.0) + { + direction = normalize(float3(-xy.x, -xy.y, -1.0)); + } + + return direction; +} + +// standard custom texture vertex shader that should always be used +v2f_customrendertexture CustomRenderTextureVertexShader(appdata_customrendertexture IN) +{ + v2f_customrendertexture OUT; + +#if UNITY_UV_STARTS_AT_TOP + const float2 vertexPositions[6] = + { + { -1.0f, 1.0f }, + { -1.0f, -1.0f }, + { 1.0f, -1.0f }, + { 1.0f, 1.0f }, + { -1.0f, 1.0f }, + { 1.0f, -1.0f } + }; + + const float2 texCoords[6] = + { + { 0.0f, 0.0f }, + { 0.0f, 1.0f }, + { 1.0f, 1.0f }, + { 1.0f, 0.0f }, + { 0.0f, 0.0f }, + { 1.0f, 1.0f } + }; +#else + const float2 vertexPositions[6] = + { + { 1.0f, 1.0f }, + { -1.0f, -1.0f }, + { -1.0f, 1.0f }, + { -1.0f, -1.0f }, + { 1.0f, 1.0f }, + { 1.0f, -1.0f } + }; + + const float2 texCoords[6] = + { + { 1.0f, 1.0f }, + { 0.0f, 0.0f }, + { 0.0f, 1.0f }, + { 0.0f, 0.0f }, + { 1.0f, 1.0f }, + { 1.0f, 0.0f } + }; +#endif + + uint primitiveID = IN.vertexID / 6; + uint vertexID = IN.vertexID % 6; + float3 updateZoneCenter = CustomRenderTextureCenters[primitiveID].xyz; + float3 updateZoneSize = CustomRenderTextureSizesAndRotations[primitiveID].xyz; + float rotation = CustomRenderTextureSizesAndRotations[primitiveID].w * UNITY_PI / 180.0f; + +#if !UNITY_UV_STARTS_AT_TOP + rotation = -rotation; +#endif + + // Normalize rect if needed + if (CustomRenderTextureUpdateSpace > 0.0) // Pixel space + { + // Normalize xy because we need it in clip space. + updateZoneCenter.xy /= _CustomRenderTextureInfo.xy; + updateZoneSize.xy /= _CustomRenderTextureInfo.xy; + } + else // normalized space + { + // Un-normalize depth because we need actual slice index for culling + updateZoneCenter.z *= _CustomRenderTextureInfo.z; + updateZoneSize.z *= _CustomRenderTextureInfo.z; + } + + // Compute rotation + + // Compute quad vertex position + float2 clipSpaceCenter = updateZoneCenter.xy * 2.0 - 1.0; + float2 pos = vertexPositions[vertexID] * updateZoneSize.xy; + pos = CustomRenderTextureRotate2D(pos, rotation); + pos.x += clipSpaceCenter.x; +#if UNITY_UV_STARTS_AT_TOP + pos.y += clipSpaceCenter.y; +#else + pos.y -= clipSpaceCenter.y; +#endif + + // For 3D texture, cull quads outside of the update zone + // This is neeeded in additional to the preliminary minSlice/maxSlice done on the CPU because update zones can be disjointed. + // ie: slices [1..5] and [10..15] for two differents zones so we need to cull out slices 0 and [6..9] + if (CustomRenderTextureIs3D > 0.0) + { + int minSlice = (int)(updateZoneCenter.z - updateZoneSize.z * 0.5); + int maxSlice = minSlice + (int)updateZoneSize.z; + if (_CustomRenderTexture3DSlice < minSlice || _CustomRenderTexture3DSlice >= maxSlice) + { + pos.xy = float2(1000.0, 1000.0); // Vertex outside of ncs + } + } + + OUT.vertex = float4(pos, 0.0, 1.0); + OUT.primitiveID = asuint(CustomRenderTexturePrimitiveIDs[primitiveID]); + OUT.localTexcoord = float3(texCoords[vertexID], CustomRenderTexture3DTexcoordW); + OUT.globalTexcoord = float3(pos.xy * 0.5 + 0.5, CustomRenderTexture3DTexcoordW); +#if UNITY_UV_STARTS_AT_TOP + OUT.globalTexcoord.y = 1.0 - OUT.globalTexcoord.y; +#endif + OUT.direction = CustomRenderTextureComputeCubeDirection(OUT.globalTexcoord.xy); + + return OUT; +} + +struct appdata_init_customrendertexture +{ + float4 vertex : POSITION; + float2 texcoord : TEXCOORD0; +}; + +// User facing vertex to fragment structure for initialization materials +struct v2f_init_customrendertexture +{ + float4 vertex : SV_POSITION; + float3 texcoord : TEXCOORD0; + float3 direction : TEXCOORD1; +}; + +// standard custom texture vertex shader that should always be used for initialization shaders +v2f_init_customrendertexture InitCustomRenderTextureVertexShader (appdata_init_customrendertexture v) +{ + v2f_init_customrendertexture o; + o.vertex = UnityObjectToClipPos(v.vertex); + o.texcoord = float3(v.texcoord.xy, CustomRenderTexture3DTexcoordW); + o.direction = CustomRenderTextureComputeCubeDirection(v.texcoord.xy); + return o; +} + +#endif // UNITY_CUSTOM_TEXTURE_INCLUDED diff --git a/_Nix/rvc/crt.cginc.meta b/_Nix/rvc/crt.cginc.meta new file mode 100755 index 00000000..7998b844 --- /dev/null +++ b/_Nix/rvc/crt.cginc.meta @@ -0,0 +1,9 @@ +fileFormatVersion: 2 +guid: 4332e0e4cd17f2948beb88edbe8c41dc +ShaderImporter: + externalObjects: {} + defaultTextures: [] + nonModifiableTextures: [] + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/data.meta b/_Nix/rvc/data.meta new file mode 100755 index 00000000..9186816c --- /dev/null +++ b/_Nix/rvc/data.meta @@ -0,0 +1,8 @@ +fileFormatVersion: 2 +guid: a7fb73cdccdb3e8458b28b2819da3ba6 +folderAsset: yes +DefaultImporter: + externalObjects: {} + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/data/bare.a.bmp b/_Nix/rvc/data/bare.a.bmp new file mode 100755 index 00000000..f3cad5c4 Binary files /dev/null and b/_Nix/rvc/data/bare.a.bmp differ diff --git a/_Nix/rvc/data/bare.a.bmp.meta b/_Nix/rvc/data/bare.a.bmp.meta new file mode 100755 index 00000000..8548679a --- /dev/null +++ b/_Nix/rvc/data/bare.a.bmp.meta @@ -0,0 +1,116 @@ +fileFormatVersion: 2 +guid: ef865f3ad3e5a0e459ca5ea2f593171a +TextureImporter: + internalIDToNameTable: [] + externalObjects: {} + serializedVersion: 11 + mipmaps: + mipMapMode: 0 + enableMipMap: 0 + sRGBTexture: 0 + linearTexture: 0 + fadeOut: 0 + borderMipMap: 0 + mipMapsPreserveCoverage: 0 + alphaTestReferenceValue: 0.5 + mipMapFadeDistanceStart: 1 + mipMapFadeDistanceEnd: 3 + bumpmap: + convertToNormalMap: 0 + externalNormalMap: 0 + heightScale: 0.25 + normalMapFilter: 0 + isReadable: 0 + streamingMipmaps: 0 + streamingMipmapsPriority: 0 + grayScaleToAlpha: 0 + generateCubemap: 6 + cubemapConvolution: 0 + seamlessCubemap: 0 + textureFormat: 1 + maxTextureSize: 2048 + textureSettings: + serializedVersion: 2 + filterMode: 0 + aniso: 1 + mipBias: 0 + wrapU: 0 + wrapV: 0 + wrapW: 0 + nPOTScale: 1 + lightmap: 0 + compressionQuality: 50 + spriteMode: 0 + spriteExtrude: 1 + spriteMeshType: 1 + alignment: 0 + spritePivot: {x: 0.5, y: 0.5} + spritePixelsToUnits: 100 + spriteBorder: {x: 0, y: 0, z: 0, w: 0} + spriteGenerateFallbackPhysicsShape: 1 + alphaUsage: 1 + alphaIsTransparency: 0 + spriteTessellationDetail: -1 + textureType: 0 + textureShape: 1 + singleChannelComponent: 0 + maxTextureSizeSet: 0 + compressionQualitySet: 0 + textureFormatSet: 0 + applyGammaDecoding: 0 + platformSettings: + - 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1, + (pos.x == 0 ? ((pos.y == 0 ? dim.y : pos.y) - 1) : pos.y) + ); +} + +uint2 next_pos(in uint2 pos, in uint2 dim) { + return uint2( + pos.x == (dim.x - 1) ? 0 : dim.x + 1, + pos.x == (dim.x - 1) ? (pos.y == (dim.y - 1) ? 0 : dim.y - 1) : pos.y + ); +} + +uint idx_uint4(uint4 data, uint idx) { + [flatten] + switch (idx) { + case 0: + return data.x; + case 1: + return data.y; + case 2: + return data.z; + default: + return data.w; + } +} + +struct v2f { + float4 vertex : SV_Position; + float2 uv : TEXCOORD0; +}; + +v2f vert_ortho_fullscreen(appdata_base v) { + v2f o; + + o.vertex = is_ortho ? + float4((v.texcoord.xy-0.5f)*2, 0, 1) : + UnityObjectToClipPos(v.vertex); + + o.uv = v.texcoord.xy; + #if UNITY_UV_STARTS_AT_TOP + o.uv.y = 1 - o.uv.y; + #endif + + return o; +} + +uint4 color_to_uint(float4 col) { + float m = (float)(~(uint)0); + return uint4( + col.r * m, + col.g * m, + col.b * m, + col.a * m + ); +} + +float4 uint_to_color(uint4 data) { + float div = (float)(~(uint)0); + float4 conv = float4( + data.r / div, + data.g / div, + data.b / div, + data.a / div + ); + return conv; +} + +#define PACK_MASK 0xFF +#define PACK_SHIFT 8 +void pack_uint4(in uint4 data, out float3 result[6]) { + result[0] = (data.rgb & PACK_MASK) / 255.0f; + result[1] = ((data.rgb >> PACK_SHIFT) & PACK_MASK) / 255.0f; + result[2] = ((data.rgb >> (PACK_SHIFT*2)) & PACK_MASK) / 255.0f; + result[3] = ((data.rgb >> (PACK_SHIFT*3)) & PACK_MASK) / 255.0f; + result[4].r = (data.a & PACK_MASK) / 255.0f; + result[4].g = ((data.a >> PACK_SHIFT) & PACK_MASK) / 255.0f; + result[4].b = ((data.a >> (PACK_SHIFT*2)) & PACK_MASK) / 255.0f; + result[5].r = ((data.a >> (PACK_SHIFT*3)) & PACK_MASK) / 255.0f; + result[5].gb = 0; +} +#undef PACK_SHIFT +#undef PACK_MASK + +uint unpack_raw_float4(in float4 data) { + uint res = 0; + res |= uint(data.a*255.0f+0.5f) << 24; + res |= uint(data.b*255.0f+0.5f) << 16; + res |= uint(data.g*255.0f+0.5f) << 8; + res |= uint(data.r*255.0f+0.5f); + return res; +} diff --git a/_Nix/rvc/helpers.cginc.meta b/_Nix/rvc/helpers.cginc.meta new file mode 100755 index 00000000..248afa4f --- /dev/null +++ b/_Nix/rvc/helpers.cginc.meta @@ -0,0 +1,9 @@ +fileFormatVersion: 2 +guid: bcabc7a6d67e32c49bf22ab954e4bd0d +ShaderImporter: + externalObjects: {} + defaultTextures: [] + nonModifiableTextures: [] + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/main.shader b/_Nix/rvc/main.shader new file mode 100755 index 00000000..40f3be62 --- /dev/null +++ b/_Nix/rvc/main.shader @@ -0,0 +1,168 @@ +Shader "Nix/rvc" +{ + Properties + { + [ToggleUI] _Init ("Init", float) = 0 + [ToggleUI] _InitRaw ("Init directly from _Data_RAM_RAW", float) = 0 + _Ticks ("Ticks per Frame", Int) = 1024 + _TicksDivisor ("Tick Divisor", Int) = 4 + _UdonUARTPtr ("UART ptr on Udon side", Int) = 0 + + _UdonUARTInChar ("UART input Udon side", Int) = 0 + _UdonUARTInTag ("UART input unique tag", Int) = 0 + + _Data_RAM_R ("RAM Texture R", 2D) = "black" {} + _Data_RAM_G ("RAM Texture G", 2D) = "black" {} + _Data_RAM_B ("RAM Texture B", 2D) = "black" {} + _Data_RAM_A ("RAM Texture A", 2D) = "black" {} + + _Data_RAM_RAW ("RAM Texture RAW", 2D) = "black" {} + + _Data_DTB_R ("Device Tree Binary Texture R", 2D) = "black" {} + _Data_DTB_G ("Device Tree Binary Texture G", 2D) = "black" {} + _Data_DTB_B ("Device Tree Binary Texture B", 2D) = "black" {} + _Data_DTB_A ("Device Tree Binary Texture A", 2D) = "black" {} + + _DoTick ("DEBUG: Perform single step", Int) = 0 + /* _BreakpointLow ("DEBUG: Breakpoint: Enter single step mode at this PC address (low 16)", Int) = 0 */ + /* _BreakpointHigh ("DEBUG: Breakpoint: Enter single step mode at this PC address (high 16)", Int) = 0 */ + /* _BreakpointLowClock ("DEBUG: Breakpoint: Enter single step mode at this clock (low 16)", Int) = 0 */ + /* _BreakpointHighClock ("DEBUG: Breakpoint: Enter single step mode at this clock (high 16)", Int) = 0 */ + /* _CheckCSR ("DEBUG: Display CSR", Int) = 0 */ + /* _CheckMEM ("DEBUG: Display RAM", Int) = 0 */ + /* [ToggleUI] _CheckMEMraw ("DEBUG: Display RAM raw (not | 0x80000000)", Int) = 0 */ + } + SubShader + { + Tags { "RenderType"="Opaque" "IgnoreProjector"="true" } + Cull Off + ZTest Off + Lighting Off + Blend One Zero + + Pass + { + Name "CPUTick" + + CGPROGRAM + #pragma target 5.0 + #pragma vertex CustomRenderTextureVertexShader + #pragma fragment frag + + #define PASS_TICK + + // custom crt include w/ Texture2D self-reference + #include "crt.cginc" + #include "UnityCG.cginc" + + uniform uint _Init, _InitRaw; + uniform uint _Ticks, _TicksDivisor; + uniform uint _UdonUARTPtr, _UdonUARTInChar, _UdonUARTInTag; + uniform uint _DoTick; + /* uniform uint _BreakpointLow, _BreakpointHigh; */ + /* uniform uint _BreakpointLowClock, _BreakpointHighClock; */ + /* uniform uint _CheckCSR; //, _CheckMEM, _CheckMEMraw; */ + /* static uint _Breakpoint, _BreakpointClock; */ + + Texture2D _Data_DTB_R; + Texture2D _Data_DTB_G; + Texture2D _Data_DTB_B; + Texture2D _Data_DTB_A; + + #define STATE_TEX _SelfTexture2D + + static uint2 s_dim; + + #include "helpers.cginc" + + #include "src/types.h" + #include "src/ins.h" + #include "src/uart.h" + #include "src/emu.h" // includes mmu.h, csr.h, mem.h, trap.h + #include "src/cpu.h" + + uint4 frag(v2f_customrendertexture i) : SV_Target { + STATE_TEX.GetDimensions(s_dim.x, s_dim.y); + + uint2 pos = i.globalTexcoord.xy * s_dim; + + _Ticks /= max(_TicksDivisor, 1); + _Ticks = max(_Ticks, 2); + + /* _Breakpoint = _BreakpointLow | (_BreakpointHigh << 16); */ + /* _BreakpointClock = _BreakpointLowClock | (_BreakpointHighClock << 16); */ + + if (_Init) { + if (!_InitRaw) { + cpu = cpu_init(); + } + } else { + if (!pixel_has_state(pos)) { + return STATE_TEX[pos]; + } + + decode(_UdonUARTPtr); + + [fastopt] + for (uint i = 0; i < _Ticks && !cpu.stall; i++) { + cpu_tick(); + } + } + + /* cpu.debug_csr_val = read_csr_raw(_CheckCSR); */ + /* cpu.debug_mem_val = mem_get_word(_CheckMEM | (_CheckMEMraw ? 0 : 0x80000000)); */ + + return encode(pos); + /* return uint4(mem_get_word(0x80000000), 0, 0, 0); */ + /* return uint4(uint(pos.x + 128*pos.y) % 256, 0, 0, 0); */ + } + ENDCG + } + + Pass + { + Name "Commit" + + CGPROGRAM + #pragma target 5.0 + #pragma vertex CustomRenderTextureVertexShader + #pragma fragment frag + + #define PASS_COMMIT + + // custom crt include + #include "crt.cginc" + #include "UnityCG.cginc" + + float _Init, _InitRaw; + + Texture2D _Data_RAM_R; + Texture2D _Data_RAM_G; + Texture2D _Data_RAM_B; + Texture2D _Data_RAM_A; + Texture2D _Data_RAM_RAW; + + #define STATE_TEX _SelfTexture2D + + static uint2 s_dim; + + #include "helpers.cginc" + + #include "src/types.h" + + uint4 frag(v2f_customrendertexture i) : SV_Target { + STATE_TEX.GetDimensions(s_dim.x, s_dim.y); + + uint2 pos = i.globalTexcoord.xy * s_dim; + + if (_Init && _InitRaw) { + return _Data_RAM_RAW[pos]; + } + + decode_for_commit(); + return commit(pos); + } + ENDCG + } + } +} diff --git a/_Nix/rvc/main.shader.meta b/_Nix/rvc/main.shader.meta new file mode 100755 index 00000000..e79e12e5 --- /dev/null +++ b/_Nix/rvc/main.shader.meta @@ -0,0 +1,9 @@ +fileFormatVersion: 2 +guid: 6ee21bb85e36aaa439fa6f9c31141333 +ShaderImporter: + externalObjects: {} + defaultTextures: [] + nonModifiableTextures: [] + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src.meta b/_Nix/rvc/src.meta new file mode 100755 index 00000000..f7040f56 --- /dev/null +++ b/_Nix/rvc/src.meta @@ -0,0 +1,8 @@ +fileFormatVersion: 2 +guid: 9d0773faab281b541af9270c0e5d7008 +folderAsset: yes +DefaultImporter: + externalObjects: {} + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/cpu.h b/_Nix/rvc/src/cpu.h new file mode 100755 index 00000000..2974e847 --- /dev/null +++ b/_Nix/rvc/src/cpu.h @@ -0,0 +1,49 @@ +#ifndef CPU_H +#define CPU_H + +cpu_t cpu_init() { + cpu_t ret = (cpu_t)0; + + ret.xreg11 = 0x1020; // linux? device tree? + ret.pc = 0x80000000; + ret.reservation_en = false; + + ret.uart.rbr_thr_ier_iir = 0x00000000; + ret.uart.lcr_mcr_lsr_scr = 0x00200000; // LSR_THR_EMPTY is set + + ret.csr.privilege = 3; // PRIV_MACHINE + + return ret; +} + +void cpu_tick() { + // DEBUG: single stepping + if (_DoTick && _DoTick == cpu.debug_do_tick) { + return; + } + cpu.debug_do_tick = _DoTick; + + /* cpu.debug_arb_0 = */ + /* cpu.debug_arb_1 = */ + /* cpu.debug_arb_2 = */ + /* cpu.debug_arb_3 = */ + /* cpu.debug_arb_4 = */ + /* cpu.debug_arb_5 = */ + /* cpu.debug_arb_6 = */ + /* cpu.debug_arb_7 = 0; */ + + cpu.clock++; + emulate(); + + /* if ((_BreakpointClock && _BreakpointClock == cpu.clock) || (_Breakpoint && _Breakpoint == cpu.pc)) { */ + /* cpu.debug_do_tick = 0xffffffff; */ + /* _DoTick = cpu.debug_do_tick; */ + /* } */ + + if (cpu.stall) { + cpu.stall_count++; + return; + } +} + +#endif diff --git a/_Nix/rvc/src/cpu.h.meta b/_Nix/rvc/src/cpu.h.meta new file mode 100755 index 00000000..ccd02fab --- /dev/null +++ b/_Nix/rvc/src/cpu.h.meta @@ -0,0 +1,95 @@ +fileFormatVersion: 2 +guid: a4e6e621af577d74b9555b1025599b09 +PluginImporter: + externalObjects: {} + serializedVersion: 2 + iconMap: {} + executionOrder: {} + defineConstraints: [] + isPreloaded: 0 + isOverridable: 0 + isExplicitlyReferenced: 0 + validateReferences: 1 + platformData: + - first: + '': Any + second: + enabled: 0 + settings: + Exclude Android: 0 + Exclude Editor: 0 + Exclude Linux: 0 + Exclude Linux64: 0 + Exclude LinuxUniversal: 0 + Exclude OSXUniversal: 0 + Exclude Win: 0 + Exclude Win64: 0 + - first: + Android: Android + second: + enabled: 1 + settings: + CPU: ARMv7 + - first: + Any: + second: + enabled: 1 + settings: {} + - first: + Editor: Editor + second: + enabled: 1 + settings: + CPU: AnyCPU + DefaultValueInitialized: true + OS: AnyOS + - first: + Facebook: Win + second: + enabled: 0 + settings: + CPU: AnyCPU + - first: + Facebook: Win64 + second: + enabled: 0 + settings: + CPU: AnyCPU + - first: + Standalone: Linux + second: + enabled: 1 + settings: + CPU: x86 + - first: + Standalone: Linux64 + second: + enabled: 1 + settings: + CPU: x86_64 + - first: + Standalone: LinuxUniversal + second: + enabled: 1 + settings: {} + - first: + Standalone: OSXUniversal + second: + enabled: 1 + settings: + CPU: AnyCPU + - first: + Standalone: Win + second: + enabled: 1 + settings: + CPU: AnyCPU + - first: + Standalone: Win64 + second: + enabled: 1 + settings: + CPU: AnyCPU + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/csr.h b/_Nix/rvc/src/csr.h new file mode 100755 index 00000000..4f454b99 --- /dev/null +++ b/_Nix/rvc/src/csr.h @@ -0,0 +1,197 @@ +#ifndef CSR_H +#define CSR_H + + + +/* must match set/line count above, shift by two to ignore byte offset */ +#define RAM_L1_TAG(a) ((a >> 2) & 0xf) + + +#define CSR_USTATUS 0x000 +#define CSR_UIE 0x004 +#define CSR_UTVEC 0x005 +#define _CSR_USCRATCH 0x040 +#define CSR_UEPC 0x041 +#define CSR_UCAUSE 0x042 +#define CSR_UTVAL 0x043 +#define _CSR_UIP 0x044 +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define _CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define _CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define _CSR_PMPCFG0 0x3a0 +#define _CSR_PMPADDR0 0x3b0 +#define CSR_MCYCLE 0xb00 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define _CSR_INSERT 0xc02 +#define CSR_MHARTID 0xf14 + +#define CSR_MEMOP_OP 0x0b0 +#define CSR_MEMOP_SRC 0x0b1 +#define CSR_MEMOP_DST 0x0b2 +#define CSR_MEMOP_N 0x0b3 + +bool has_csr_access_privilege(uint addr) { + uint privilege = (addr >> 8) & 0x3; + return privilege <= cpu.csr.privilege; +} + +// SSTATUS, SIE, and SIP are subsets of MSTATUS, MIE, and MIP +uint read_csr_raw(uint address) { + address &= 0x1fff; + + uint read_mask = 0xffffffff; + + [branch] + switch (address) { + case CSR_MISA: return 0x40141101; // 0b01000000000101000001000100000001 = RV32AIMSU + case CSR_SSTATUS: address = CSR_MSTATUS; read_mask = 0x000de162; break; + case CSR_SIE: address = CSR_MIE; read_mask = 0x222; break; + case CSR_SIP: address = CSR_MIP; read_mask = 0x222; break; + case CSR_TIME: return cpu.clint.mtime_lo; + case CSR_MCYCLE: return cpu.clock; + case CSR_CYCLE: return cpu.clock; + case CSR_MHARTID: return 0; + case CSR_SATP: return (cpu.mmu.mode << 31) | cpu.mmu.ppn; + } + + uint ret; + + if (false) {} + else if (cpu.cache.csr_cache_0_addr == address) { ret = cpu.cache.csr_cache_0_val; } +else if (cpu.cache.csr_cache_1_addr == address) { ret = cpu.cache.csr_cache_1_val; } +else if (cpu.cache.csr_cache_2_addr == address) { ret = cpu.cache.csr_cache_2_val; } +else if (cpu.cache.csr_cache_3_addr == address) { ret = cpu.cache.csr_cache_3_val; } +else if (cpu.cache.csr_cache_4_addr == address) { ret = cpu.cache.csr_cache_4_val; } +else if (cpu.cache.csr_cache_5_addr == address) { ret = cpu.cache.csr_cache_5_val; } +else if (cpu.cache.csr_cache_6_addr == address) { ret = cpu.cache.csr_cache_6_val; } +else if (cpu.cache.csr_cache_7_addr == address) { ret = cpu.cache.csr_cache_7_val; } +else if (cpu.cache.csr_cache_8_addr == address) { ret = cpu.cache.csr_cache_8_val; } +else if (cpu.cache.csr_cache_9_addr == address) { ret = cpu.cache.csr_cache_9_val; } +else if (cpu.cache.csr_cache_10_addr == address) { ret = cpu.cache.csr_cache_10_val; } +else if (cpu.cache.csr_cache_11_addr == address) { ret = cpu.cache.csr_cache_11_val; } +else if (cpu.cache.csr_cache_12_addr == address) { ret = cpu.cache.csr_cache_12_val; } +else if (cpu.cache.csr_cache_13_addr == address) { ret = cpu.cache.csr_cache_13_val; } +else if (cpu.cache.csr_cache_14_addr == address) { ret = cpu.cache.csr_cache_14_val; } +else if (cpu.cache.csr_cache_15_addr == address) { ret = cpu.cache.csr_cache_15_val; } + + else { + // fallback, read value from CSR texture area + ret = tex_get_csr(address); + } + + return ret & read_mask; +} + +void write_csr_raw(uint address, uint value) { + uint where = address & 0x1fff; + uint what = value; + uint modify_mask = 0; + ins_ret nop = ins_ret_noop(); + [branch] + switch (address) { + case CSR_SSTATUS: + where = CSR_MSTATUS; + modify_mask = 0x000de162; + break; + case CSR_SIE: + where = CSR_MIE; + modify_mask = 0x222; + break; + case CSR_SIP: + where = CSR_MIP; + modify_mask = 0x222; + break; + case CSR_MIDELEG: + what &= 0x666; // from qemu + break; + case CSR_MEMOP_SRC: + cpu.memop_src_v = what; + return; + case CSR_MEMOP_DST: + cpu.memop_dst_v = what; + return; + case CSR_MEMOP_N: + cpu.memop_n = what; + return; + case CSR_MEMOP_OP: + cpu.stall = STALL_MEMOP_COPY; + return; + }; + + if (modify_mask) { + what = (read_csr_raw(where) & ~modify_mask) | (value & modify_mask); + } + + if (false) {} +else if (cpu.cache.csr_cache_0_addr == 0xffffffff || cpu.cache.csr_cache_0_addr == where) { cpu.cache.csr_cache_0_addr = where; cpu.cache.csr_cache_0_val = what; return; } +else if (cpu.cache.csr_cache_1_addr == 0xffffffff || cpu.cache.csr_cache_1_addr == where) { cpu.cache.csr_cache_1_addr = where; cpu.cache.csr_cache_1_val = what; return; } +else if (cpu.cache.csr_cache_2_addr == 0xffffffff || cpu.cache.csr_cache_2_addr == where) { cpu.cache.csr_cache_2_addr = where; cpu.cache.csr_cache_2_val = what; return; } +else if (cpu.cache.csr_cache_3_addr == 0xffffffff || cpu.cache.csr_cache_3_addr == where) { cpu.cache.csr_cache_3_addr = where; cpu.cache.csr_cache_3_val = what; return; } +else if (cpu.cache.csr_cache_4_addr == 0xffffffff || cpu.cache.csr_cache_4_addr == where) { cpu.cache.csr_cache_4_addr = where; cpu.cache.csr_cache_4_val = what; return; } +else if (cpu.cache.csr_cache_5_addr == 0xffffffff || cpu.cache.csr_cache_5_addr == where) { cpu.cache.csr_cache_5_addr = where; cpu.cache.csr_cache_5_val = what; return; } +else if (cpu.cache.csr_cache_6_addr == 0xffffffff || cpu.cache.csr_cache_6_addr == where) { cpu.cache.csr_cache_6_addr = where; cpu.cache.csr_cache_6_val = what; return; } +else if (cpu.cache.csr_cache_7_addr == 0xffffffff || cpu.cache.csr_cache_7_addr == where) { cpu.cache.csr_cache_7_addr = where; cpu.cache.csr_cache_7_val = what; return; } +else if (cpu.cache.csr_cache_8_addr == 0xffffffff || cpu.cache.csr_cache_8_addr == where) { cpu.cache.csr_cache_8_addr = where; cpu.cache.csr_cache_8_val = what; return; } +else if (cpu.cache.csr_cache_9_addr == 0xffffffff || cpu.cache.csr_cache_9_addr == where) { cpu.cache.csr_cache_9_addr = where; cpu.cache.csr_cache_9_val = what; return; } +else if (cpu.cache.csr_cache_10_addr == 0xffffffff || cpu.cache.csr_cache_10_addr == where) { cpu.cache.csr_cache_10_addr = where; cpu.cache.csr_cache_10_val = what; return; } +else if (cpu.cache.csr_cache_11_addr == 0xffffffff || cpu.cache.csr_cache_11_addr == where) { cpu.cache.csr_cache_11_addr = where; cpu.cache.csr_cache_11_val = what; return; } +else if (cpu.cache.csr_cache_12_addr == 0xffffffff || cpu.cache.csr_cache_12_addr == where) { cpu.cache.csr_cache_12_addr = where; cpu.cache.csr_cache_12_val = what; return; } +else if (cpu.cache.csr_cache_13_addr == 0xffffffff || cpu.cache.csr_cache_13_addr == where) { cpu.cache.csr_cache_13_addr = where; cpu.cache.csr_cache_13_val = what; return; } +else if (cpu.cache.csr_cache_14_addr == 0xffffffff || cpu.cache.csr_cache_14_addr == where) { cpu.cache.csr_cache_14_addr = where; cpu.cache.csr_cache_14_val = what; return; } + + + // cache overflow, stall to avoid fillup + cpu.cache.csr_cache_15_addr = where; + cpu.cache.csr_cache_15_val = what; + cpu.stall = STALL_CSR_CACHE; +} + + +uint get_csr(uint address, inout ins_ret ret) { + if (has_csr_access_privilege(address)) { + uint r = read_csr_raw(address); + return r; + } else { + ret.trap.en = true; + ret.trap.type = trap_IllegalInstruction; + ret.trap.value = cpu.pc; + return 0; + } +} + +void set_csr(uint address, uint value, inout ins_ret ret) { + bool read_only = ((address >> 10) & 0x3) == 0x3; + if (has_csr_access_privilege(address) && !read_only) { + if (address == CSR_SATP) { + mmu_update(value); + return; + } + write_csr_raw(address, value); + } else { + ret.trap.en = true; + ret.trap.type = trap_IllegalInstruction; + ret.trap.value = cpu.pc; + } +} + +#endif diff --git a/_Nix/rvc/src/csr.h.meta b/_Nix/rvc/src/csr.h.meta new file mode 100755 index 00000000..7ad76603 --- /dev/null +++ b/_Nix/rvc/src/csr.h.meta @@ -0,0 +1,27 @@ +fileFormatVersion: 2 +guid: d1647512864dd72488b5ea192795f284 +PluginImporter: + externalObjects: {} + serializedVersion: 2 + iconMap: {} + executionOrder: {} + defineConstraints: [] + isPreloaded: 0 + isOverridable: 0 + isExplicitlyReferenced: 0 + validateReferences: 1 + platformData: + - first: + Any: + second: + enabled: 1 + settings: {} + - first: + Editor: Editor + second: + enabled: 0 + settings: + DefaultValueInitialized: true + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/csr.h.pp b/_Nix/rvc/src/csr.h.pp new file mode 100755 index 00000000..9874dc7f --- /dev/null +++ b/_Nix/rvc/src/csr.h.pp @@ -0,0 +1,170 @@ +#ifndef CSR_H +#define CSR_H + + + +#define CSR_USTATUS 0x000 +#define CSR_UIE 0x004 +#define CSR_UTVEC 0x005 +#define _CSR_USCRATCH 0x040 +#define CSR_UEPC 0x041 +#define CSR_UCAUSE 0x042 +#define CSR_UTVAL 0x043 +#define _CSR_UIP 0x044 +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define _CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define _CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define _CSR_PMPCFG0 0x3a0 +#define _CSR_PMPADDR0 0x3b0 +#define CSR_MCYCLE 0xb00 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define _CSR_INSERT 0xc02 +#define CSR_MHARTID 0xf14 + +#define CSR_MEMOP_OP 0x0b0 +#define CSR_MEMOP_SRC 0x0b1 +#define CSR_MEMOP_DST 0x0b2 +#define CSR_MEMOP_N 0x0b3 + +bool has_csr_access_privilege(uint addr) { + uint privilege = (addr >> 8) & 0x3; + return privilege <= cpu.csr.privilege; +} + +// SSTATUS, SIE, and SIP are subsets of MSTATUS, MIE, and MIP +uint read_csr_raw(uint address) { + address &= 0x1fff; + + uint read_mask = 0xffffffff; + + [branch] + switch (address) { + case CSR_MISA: return 0x40141101; // 0b01000000000101000001000100000001 = RV32AIMSU + case CSR_SSTATUS: address = CSR_MSTATUS; read_mask = 0x000de162; break; + case CSR_SIE: address = CSR_MIE; read_mask = 0x222; break; + case CSR_SIP: address = CSR_MIP; read_mask = 0x222; break; + case CSR_TIME: return cpu.clint.mtime_lo; + case CSR_MCYCLE: return cpu.clock; + case CSR_CYCLE: return cpu.clock; + case CSR_MHARTID: return 0; + case CSR_SATP: return (cpu.mmu.mode << 31) | cpu.mmu.ppn; + } + + uint ret; + + if (false) {} + + else { + // fallback, read value from CSR texture area + ret = tex_get_csr(address); + } + + return ret & read_mask; +} + +void write_csr_raw(uint address, uint value) { + uint where = address & 0x1fff; + uint what = value; + uint modify_mask = 0; + ins_ret nop = ins_ret_noop(); + [branch] + switch (address) { + case CSR_SSTATUS: + where = CSR_MSTATUS; + modify_mask = 0x000de162; + break; + case CSR_SIE: + where = CSR_MIE; + modify_mask = 0x222; + break; + case CSR_SIP: + where = CSR_MIP; + modify_mask = 0x222; + break; + case CSR_MIDELEG: + what &= 0x666; // from qemu + break; + case CSR_MEMOP_SRC: + cpu.memop_src_v = what; + return; + case CSR_MEMOP_DST: + cpu.memop_dst_v = what; + return; + case CSR_MEMOP_N: + cpu.memop_n = what; + return; + case CSR_MEMOP_OP: + cpu.stall = STALL_MEMOP_COPY; + return; + }; + + if (modify_mask) { + what = (read_csr_raw(where) & ~modify_mask) | (value & modify_mask); + } + + if (false) {} + + + // cache overflow, stall to avoid fillup + cpu.cache.csr_cache__addr = where; + cpu.cache.csr_cache__val = what; + cpu.stall = STALL_CSR_CACHE; +} + + +uint get_csr(uint address, inout ins_ret ret) { + if (has_csr_access_privilege(address)) { + uint r = read_csr_raw(address); + return r; + } else { + ret.trap.en = true; + ret.trap.type = trap_IllegalInstruction; + ret.trap.value = cpu.pc; + return 0; + } +} + +void set_csr(uint address, uint value, inout ins_ret ret) { + bool read_only = ((address >> 10) & 0x3) == 0x3; + if (has_csr_access_privilege(address) && !read_only) { + if (address == CSR_SATP) { + mmu_update(value); + return; + } + write_csr_raw(address, value); + } else { + ret.trap.en = true; + ret.trap.type = trap_IllegalInstruction; + ret.trap.value = cpu.pc; + } +} + +#endif diff --git a/_Nix/rvc/src/csr.h.pp.meta b/_Nix/rvc/src/csr.h.pp.meta new file mode 100755 index 00000000..58525c2b --- /dev/null +++ b/_Nix/rvc/src/csr.h.pp.meta @@ -0,0 +1,7 @@ +fileFormatVersion: 2 +guid: b91567c90da19ff419c6b2718558ab3c +DefaultImporter: + externalObjects: {} + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/emu.h b/_Nix/rvc/src/emu.h new file mode 100755 index 00000000..739fb07a --- /dev/null +++ b/_Nix/rvc/src/emu.h @@ -0,0 +1,703 @@ +#ifndef EMU_H +#define EMU_H + +#include "mmu.h" + +#define AS_SIGNED(val) (asint(val)) +#define AS_UNSIGNED(val) (asuint(val)) + +// this is just a leftover from C, where AS_SIGNED/AS_UNSIGNED needed this as consts +// please don't judge me +#define ZERO 0 +#define ONE 1 + +#define DEF(name, fmt_t, code) \ + void emu_##name(uint ins_word, inout ins_ret ret, fmt_t ins) { code } + +#define WR_RD(code) { ret.write_reg = ins.rd; ret.write_val = AS_UNSIGNED(code); } +#define WR_PC(code) { ret.pc_val = AS_UNSIGNED(code); } +#define WR_CSR(code) { ret.csr_write = ins.csr; ret.csr_val = AS_UNSIGNED(code); } +#define WR_MEM(addr, code, size) { ret.mem_wr_addr = addr; ret.mem_wr_size = size; ret.mem_wr_value = AS_UNSIGNED(code); } + +/* + * BEGIN INSTRUCTIONS + */ + +static uint prepared_mem_val; + +DEF(add, FormatR, { // rv32i + WR_RD(AS_SIGNED(xreg(ins.rs1)) + AS_SIGNED(xreg(ins.rs2))); +}) +DEF(addi, FormatI, { // rv32i + WR_RD(AS_SIGNED(xreg(ins.rs1)) + AS_SIGNED(ins.imm)); +}) +DEF(amoswap_w, FormatR, { // rv32a + uint tmp = prepared_mem_val; + WR_MEM(xreg(ins.rs1), (xreg(ins.rs2)), 32) + WR_RD(tmp) +}) +DEF(amoadd_w, FormatR, { // rv32a + WR_MEM(xreg(ins.rs1), (xreg(ins.rs2) + prepared_mem_val), 32) + WR_RD(prepared_mem_val) +}) +DEF(amoxor_w, FormatR, { // rv32a + WR_MEM(xreg(ins.rs1), (xreg(ins.rs2) ^ prepared_mem_val), 32) + WR_RD(prepared_mem_val) +}) +DEF(amoand_w, FormatR, { // rv32a + WR_MEM(xreg(ins.rs1), (xreg(ins.rs2) & prepared_mem_val), 32) + WR_RD(prepared_mem_val) +}) +DEF(amoor_w, FormatR, { // rv32a + WR_MEM(xreg(ins.rs1), (xreg(ins.rs2) | prepared_mem_val), 32) + WR_RD(prepared_mem_val) +}) +DEF(amomin_w, FormatR, { // rv32a + uint sec = xreg(ins.rs2); + WR_MEM(xreg(ins.rs1), (AS_SIGNED(sec) < AS_SIGNED(prepared_mem_val) ? sec : prepared_mem_val), 32) + WR_RD(prepared_mem_val) +}) +DEF(amomax_w, FormatR, { // rv32a + uint sec = xreg(ins.rs2); + WR_MEM(xreg(ins.rs1), (AS_SIGNED(sec) > AS_SIGNED(prepared_mem_val) ? sec : prepared_mem_val), 32) + WR_RD(prepared_mem_val) +}) +DEF(amominu_w, FormatR, { // rv32a + uint sec = xreg(ins.rs2); + WR_MEM(xreg(ins.rs1), (AS_UNSIGNED(sec) < AS_UNSIGNED(prepared_mem_val) ? sec : prepared_mem_val), 32) + WR_RD(prepared_mem_val) +}) +DEF(amomaxu_w, FormatR, { // rv32a + uint sec = xreg(ins.rs2); + WR_MEM(xreg(ins.rs1), (AS_UNSIGNED(sec) > AS_UNSIGNED(prepared_mem_val) ? sec : prepared_mem_val), 32) + WR_RD(prepared_mem_val) +}) +DEF(and, FormatR, { // rv32i + WR_RD(xreg(ins.rs1) & xreg(ins.rs2)) +}) +DEF(andi, FormatI, { // rv32i + WR_RD(xreg(ins.rs1) & ins.imm) +}) +DEF(auipc, FormatU, { // rv32i + WR_RD(cpu.pc + ins.imm) +}) +DEF(beq, FormatB, { // rv32i + if (xreg(ins.rs1) == xreg(ins.rs2)) { + WR_PC(cpu.pc + ins.imm); + } +}) +DEF(bge, FormatB, { // rv32i + if (AS_SIGNED(xreg(ins.rs1)) >= AS_SIGNED(xreg(ins.rs2))) { + WR_PC(cpu.pc + ins.imm); + } +}) +DEF(bgeu, FormatB, { // rv32i + if (AS_UNSIGNED(xreg(ins.rs1)) >= AS_UNSIGNED(xreg(ins.rs2))) { + WR_PC(cpu.pc + ins.imm); + } +}) +DEF(blt, FormatB, { // rv32i + if (AS_SIGNED(xreg(ins.rs1)) < AS_SIGNED(xreg(ins.rs2))) { + WR_PC(cpu.pc + ins.imm); + } +}) +DEF(bltu, FormatB, { // rv32i + if (AS_UNSIGNED(xreg(ins.rs1)) < AS_UNSIGNED(xreg(ins.rs2))) { + WR_PC(cpu.pc + ins.imm); + } +}) +DEF(bne, FormatB, { // rv32i + if (xreg(ins.rs1) != xreg(ins.rs2)) { + WR_PC(cpu.pc + ins.imm); + } +}) +DEF(csrrc, FormatCSR, { // system + uint rs = xreg(ins.rs); + if (rs != 0) { + WR_CSR(ins.value & ~rs); + } + WR_RD(ins.value) +}) +DEF(csrrci, FormatCSR, { // system + if (ins.rs != 0) { + WR_CSR(ins.value & (~ins.rs)); + } + WR_RD(ins.value) +}) +DEF(csrrs, FormatCSR, { // system + uint rs = xreg(ins.rs); + if (rs != 0) { + WR_CSR(ins.value | rs); + } + WR_RD(ins.value) +}) +DEF(csrrsi, FormatCSR, { // system + if (ins.rs != 0) { + WR_CSR(ins.value | ins.rs); + } + WR_RD(ins.value) +}) +DEF(csrrw, FormatCSR, { // system + WR_CSR(xreg(ins.rs)); + WR_RD(ins.value) +}) +DEF(csrrwi, FormatCSR, { // system + WR_CSR(ins.rs); + WR_RD(ins.value) +}) +DEF(div, FormatR, { // rv32m + uint dividend = xreg(ins.rs1); + uint divisor = xreg(ins.rs2); + uint result; + if (divisor == 0) { + result = 0xFFFFFFFF; + } else if (dividend == 0x80000000 && divisor == 0xFFFFFFFF) { + result = dividend; + } else { + int tmp = AS_SIGNED(dividend) / AS_SIGNED(divisor); + result = AS_UNSIGNED(tmp); + } + WR_RD(result) +}) +DEF(divu, FormatR, { // rv32m + uint dividend = xreg(ins.rs1); + uint divisor = xreg(ins.rs2); + uint result; + if (divisor == 0) { + result = 0xFFFFFFFF; + } else { + result = dividend / divisor; + } + WR_RD(result) +}) +DEF(ebreak, FormatEmpty, { // system + // unnecessary? +}) +DEF(ecall, FormatEmpty, { // system + /* if (xreg(17) == 93) { */ + /* // EXIT CALL - only used for self-tests */ + /* uint status = xreg(10); */ + /* cpu.stall = STALL_EXIT_CALL; */ + /* write_csr_raw(0x200, status); */ + /* } else { */ + ret.trap.en = true; + ret.trap.value = cpu.pc; + if (cpu.csr.privilege == PRIV_USER) { + ret.trap.type = trap_EnvironmentCallFromUMode; + } else if (cpu.csr.privilege == PRIV_SUPERVISOR) { + ret.trap.type = trap_EnvironmentCallFromSMode; + } else { // PRIV_MACHINE + ret.trap.type = trap_EnvironmentCallFromMMode; + } + /* } */ +}) +DEF(fence, FormatEmpty, { // rv32i + // skip +}) +DEF(fence_i, FormatEmpty, { // rv32i + cpu.stall = STALL_FENCE; +}) +DEF(jal, FormatJ, { // rv32i + WR_RD(cpu.pc + 4); + WR_PC(cpu.pc + ins.imm); +}) +DEF(jalr, FormatI, { // rv32i + WR_RD(cpu.pc + 4); + WR_PC(xreg(ins.rs1) + ins.imm); +}) +DEF(lb, FormatI, { // rv32i + uint tmp = sign_extend(prepared_mem_val & 0xff, 8); + WR_RD(tmp) +}) +DEF(lbu, FormatI, { // rv32i + uint tmp = prepared_mem_val & 0xff; + WR_RD(tmp) +}) +DEF(lh, FormatI, { // rv32i + uint tmp = sign_extend(prepared_mem_val & 0xffff, 16); + WR_RD(tmp) +}) +DEF(lhu, FormatI, { // rv32i + uint tmp = prepared_mem_val & 0xffff; + WR_RD(tmp) +}) +DEF(lr_w, FormatR, { // rv32a + uint addr = xreg(ins.rs1); + uint tmp = prepared_mem_val; + cpu.reservation_en = true; + cpu.reservation_addr = addr; + WR_RD(tmp) +}) +DEF(lui, FormatU, { // rv32i + WR_RD(ins.imm) +}) +DEF(lw, FormatI, { // rv32i + // would need sign extend for xlen > 32 + WR_RD(prepared_mem_val) +}) +DEF(mret, FormatEmpty, { // system + uint newpc = get_csr(CSR_MEPC, ret); + if (!ret.trap.en) { + uint status = read_csr_raw(CSR_MSTATUS); + uint mpie = (status >> 7) & 1; + uint mpp = (status >> 11) & 0x3; + uint mprv = mpp == PRIV_MACHINE ? ((status >> 17) & 1) : 0; + uint new_status = (status & ~0x21888) | (mprv << 17) | (mpie << 3) | (1 << 7); + write_csr_raw(CSR_MSTATUS, new_status); + cpu.csr.privilege = mpp; + WR_PC(newpc) + } +}) +DEF(mul, FormatR, { // rv32m + uint tmp = AS_SIGNED(xreg(ins.rs1)) * AS_SIGNED(xreg(ins.rs2)); + WR_RD(tmp) +}) +DEF(mulh, FormatR, { // rv32m + // FIXME: mulh-family instructions have to use double precision floating points internally atm... + // umul/imul (https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/umul--sm4---asm-) + // do exist, but appear to be unusable? + precise double op1 = AS_SIGNED(xreg(ins.rs1)); + precise double op2 = AS_SIGNED(xreg(ins.rs2)); + uint tmp = uint((op1 * op2) / 4294967296.0l); // '/ 4294967296' == '>> 32' + WR_RD(tmp) +}) +DEF(mulhsu, FormatR, { // rv32m + // is the signed/unsigned stuff even correct? who knows... + precise double op1 = AS_SIGNED(xreg(ins.rs1)); + precise double op2 = AS_UNSIGNED(xreg(ins.rs2)); + uint tmp = uint((op1 * op2) / 4294967296.0l); // '/ 4294967296' == '>> 32' + WR_RD(tmp) +}) +DEF(mulhu, FormatR, { // rv32m + precise double op1 = AS_UNSIGNED(xreg(ins.rs1)); + precise double op2 = AS_UNSIGNED(xreg(ins.rs2)); + uint tmp = uint((op1 * op2) / 4294967296.0l); // '/ 4294967296' == '>> 32' + WR_RD(tmp) +}) +DEF(or, FormatR, { // rv32i + WR_RD(xreg(ins.rs1) | xreg(ins.rs2)) +}) +DEF(ori, FormatI, { // rv32i + WR_RD(xreg(ins.rs1) | ins.imm) +}) +DEF(rem, FormatR, { // rv32m + uint dividend = xreg(ins.rs1); + uint divisor = xreg(ins.rs2); + uint result; + if (divisor == 0) { + result = dividend; + } else if (dividend == 0x80000000 && divisor == 0xFFFFFFFF) { + result = 0; + } else { + int tmp = AS_SIGNED(dividend) % AS_SIGNED(divisor); + result = AS_UNSIGNED(tmp); + } + WR_RD(result) +}) +DEF(remu, FormatR, { // rv32m + uint dividend = xreg(ins.rs1); + uint divisor = xreg(ins.rs2); + uint result; + if (divisor == 0) { + result = dividend; + } else { + result = dividend % divisor; + } + WR_RD(result) +}) +DEF(sb, FormatS, { // rv32i + WR_MEM(ins.addr, xreg(ins.rs2), 8) +}) +DEF(sc_w, FormatR, { // rv32a + // I'm pretty sure this is not it chief, but it does the trick for now + uint addr = xreg(ins.rs1); + if (cpu.reservation_en && cpu.reservation_addr == addr) { + WR_MEM(addr, xreg(ins.rs2), 32); + cpu.reservation_en = false; + WR_RD(ZERO) + } else { + WR_RD(ONE) + } +}) +DEF(sfence_vma, FormatEmpty, { // system + /* cpu.stall = STALL_FENCE; */ +}) +DEF(sh, FormatS, { // rv32i + WR_MEM(ins.addr, xreg(ins.rs2), 16) +}) +DEF(sll, FormatR, { // rv32i + WR_RD(xreg(ins.rs1) << xreg(ins.rs2)) +}) +DEF(slli, FormatR, { // rv32i + uint shamt = (ins_word >> 20) & 0x1F; + WR_RD(xreg(ins.rs1) << shamt) +}) +DEF(slt, FormatR, { // rv32i + if (AS_SIGNED(xreg(ins.rs1)) < AS_SIGNED(xreg(ins.rs2))) { + WR_RD(ONE) + } else { + WR_RD(ZERO) + } +}) +DEF(slti, FormatI, { // rv32i + if (AS_SIGNED(xreg(ins.rs1)) < AS_SIGNED(ins.imm)) { + WR_RD(ONE) + } else { + WR_RD(ZERO) + } +}) +DEF(sltiu, FormatI, { // rv32i + if (AS_UNSIGNED(xreg(ins.rs1)) < AS_UNSIGNED(ins.imm)) { + WR_RD(ONE) + } else { + WR_RD(ZERO) + } +}) +DEF(sltu, FormatR, { // rv32i + if (AS_UNSIGNED(xreg(ins.rs1)) < AS_UNSIGNED(xreg(ins.rs2))) { + WR_RD(ONE) + } else { + WR_RD(ZERO) + } +}) +DEF(sra, FormatR, { // rv32i + uint msr = xreg(ins.rs1) & 0x80000000; + WR_RD(msr ? ~(~xreg(ins.rs1) >> xreg(ins.rs2)) : + xreg(ins.rs1) >> xreg(ins.rs2)) +}) +DEF(srai, FormatR, { // rv32i + uint msr = xreg(ins.rs1) & 0x80000000; + uint shamt = (ins_word >> 20) & 0x1F; + WR_RD(msr ? ~(~xreg(ins.rs1) >> shamt) : + xreg(ins.rs1) >> shamt) +}) +DEF(sret, FormatEmpty, { // system + uint newpc = get_csr(CSR_SEPC, ret); + if (!ret.trap.en) { + uint status = read_csr_raw(CSR_SSTATUS); + uint spie = (status >> 5) & 1; + uint spp = (status >> 8) & 1; + uint mprv = spp == PRIV_MACHINE ? ((status >> 17) & 1) : 0; + uint new_status = (status & ~0x20122) | (mprv << 17) | (spie << 1) | (1 << 5); + write_csr_raw(CSR_SSTATUS, new_status); + cpu.csr.privilege = spp; + WR_PC(newpc) + } +}) +DEF(srl, FormatR, { // rv32i + WR_RD(xreg(ins.rs1) >> xreg(ins.rs2)) +}) +DEF(srli, FormatR, { // rv32i + uint shamt = (ins_word >> 20) & 0x1F; + WR_RD(xreg(ins.rs1) >> shamt) +}) +DEF(sub, FormatR, { // rv32i + WR_RD(AS_SIGNED(xreg(ins.rs1)) - AS_SIGNED(xreg(ins.rs2))); +}) +DEF(sw, FormatS, { // rv32i + WR_MEM(ins.addr, xreg(ins.rs2), 32) +}) +DEF(uret, FormatEmpty, { // system + // unnecessary? +}) +DEF(wfi, FormatEmpty, { // system + // no-op is valid here, so skip +}) +DEF(xor, FormatR, { // rv32i + WR_RD(xreg(ins.rs1) ^ xreg(ins.rs2)) +}) +DEF(xori, FormatI, { // rv32i + WR_RD(xreg(ins.rs1) ^ ins.imm) +}) + +/* + * END INSTRUCTIONS + */ + +#define RUN(name, data, insf) case data : { \ + emu_##name(ins_word, ret, insf); \ + return ret; \ +} +ins_ret ins_select(uint ins_word, inout ins_ret ret) { + uint ins_masked; + + FormatEmpty ins_FormatEmpty = parse_FormatEmpty(ins_word); + FormatCSR ins_FormatCSR = parse_FormatCSR(ins_word); + FormatI ins_FormatI = parse_FormatI(ins_word); + FormatU ins_FormatU = parse_FormatU(ins_word); + + /* + NOTE: The switch statements below can't all use [forcecase]. + While this would be best for performance (according to my testing), + it breaks compilation very badly, so only do it for the bigger ones. + */ + + ins_masked = ins_word & 0x0000007f; + [branch] + switch (ins_masked) { + RUN(auipc, 0x00000017, ins_FormatU) + RUN(jal, 0x0000006f, parse_FormatJ(ins_word)) + RUN(lui, 0x00000037, ins_FormatU) + } + + FormatR ins_FormatR = parse_FormatR(ins_word); + + ins_masked = ins_word & 0xfe00707f; + [forcecase] + switch (ins_masked) { + RUN(add, 0x00000033, ins_FormatR) + RUN(and, 0x00007033, ins_FormatR) + RUN(div, 0x02004033, ins_FormatR) + RUN(divu, 0x02005033, ins_FormatR) + RUN(mul, 0x02000033, ins_FormatR) + RUN(mulh, 0x02001033, ins_FormatR) + RUN(mulhsu, 0x02002033, ins_FormatR) + RUN(mulhu, 0x02003033, ins_FormatR) + RUN(or, 0x00006033, ins_FormatR) + RUN(rem, 0x02006033, ins_FormatR) + RUN(remu, 0x02007033, ins_FormatR) + RUN(sll, 0x00001033, ins_FormatR) + RUN(slt, 0x00002033, ins_FormatR) + RUN(sltu, 0x00003033, ins_FormatR) + RUN(sra, 0x40005033, ins_FormatR) + RUN(srl, 0x00005033, ins_FormatR) + RUN(sub, 0x40000033, ins_FormatR) + RUN(xor, 0x00004033, ins_FormatR) + } + + FormatS ins_FormatS = parse_FormatS(ins_word); + FormatB ins_FormatB = parse_FormatB(ins_word); + + // since function calls are all inlined we perform memory accesses + // all together, this way mem_get_word only has to exist once + // (though this might cause some unnecessary accesses too) + uint do_mem_read = 0; + if ((ins_word & 0x0000007f) == 0x00000003) { + // lX memory read + do_mem_read = xreg(ins_FormatI.rs1) + ins_FormatI.imm; + } else if ((ins_word & 0x0000202f) == 0x0000202f) { + // atomic memory read + do_mem_read = xreg(ins_FormatR.rs1); + } + if (do_mem_read) { + /* cpu.debug_arb_3 = do_mem_read; */ + + uint prepared_read_addr = mmu_translate(ret, do_mem_read, MMU_ACCESS_READ); + if (ret.trap.en) { + return ret; + } + // take care of unaligned memory reads using a loop + // so mem_get_word isn't inlined twice + uint w1 = 0, w2 = 0; + [loop] + for (uint ui = 0; ui < ((prepared_read_addr & 0x3) ? 2 : 1); ui++) { + uint tmp = mem_get_word((prepared_read_addr & (~0x3)) + 0x4 * ui); + [flatten] + if (ui) { w2 = tmp; } + else { w1 = tmp; } + } + prepared_mem_val = w1 >> ((do_mem_read & 0x3) * 8); + prepared_mem_val |= w2 << ((4 - (do_mem_read & 0x3)) * 8); + + /* cpu.debug_arb_4 = w1; */ + /* cpu.debug_arb_5 = w2; */ + /* cpu.debug_arb_6 = prepared_read_addr; */ + /* cpu.debug_arb_7 = prepared_mem_val; */ + } + + if ((ins_word & 0x00000073) == 0x00000073) { + // could be CSR instruction + ins_FormatCSR.value = get_csr(ins_FormatCSR.csr, ret); + } + + ins_masked = ins_word & 0x0000707f; + [forcecase] + switch (ins_masked) { + RUN(addi, 0x00000013, ins_FormatI) + RUN(andi, 0x00007013, ins_FormatI) + RUN(beq, 0x00000063, ins_FormatB) + RUN(bge, 0x00005063, ins_FormatB) + RUN(bgeu, 0x00007063, ins_FormatB) + RUN(blt, 0x00004063, ins_FormatB) + RUN(bltu, 0x00006063, ins_FormatB) + RUN(bne, 0x00001063, ins_FormatB) + RUN(csrrc, 0x00003073, ins_FormatCSR) + RUN(csrrci, 0x00007073, ins_FormatCSR) + RUN(csrrs, 0x00002073, ins_FormatCSR) + RUN(csrrsi, 0x00006073, ins_FormatCSR) + RUN(csrrw, 0x00001073, ins_FormatCSR) + RUN(csrrwi, 0x00005073, ins_FormatCSR) + RUN(fence, 0x0000000f, ins_FormatEmpty) + RUN(fence_i, 0x0000100f, ins_FormatEmpty) + RUN(jalr, 0x00000067, ins_FormatI) + RUN(lb, 0x00000003, ins_FormatI) + RUN(lbu, 0x00004003, ins_FormatI) + RUN(lh, 0x00001003, ins_FormatI) + RUN(lhu, 0x00005003, ins_FormatI) + RUN(lw, 0x00002003, ins_FormatI) + RUN(ori, 0x00006013, ins_FormatI) + RUN(sb, 0x00000023, ins_FormatS) + RUN(sh, 0x00001023, ins_FormatS) + RUN(slti, 0x00002013, ins_FormatI) + RUN(sltiu, 0x00003013, ins_FormatI) + RUN(sw, 0x00002023, ins_FormatS) + RUN(xori, 0x00004013, ins_FormatI) + } + + ins_masked = ins_word & 0xf800707f; + [forcecase] + switch (ins_masked) { + RUN(amoswap_w, 0x0800202f, ins_FormatR) + RUN(amoadd_w, 0x0000202f, ins_FormatR) + RUN(amoxor_w, 0x2000202f, ins_FormatR) + RUN(amoand_w, 0x6000202f, ins_FormatR) + RUN(amoor_w, 0x4000202f, ins_FormatR) + RUN(amomin_w, 0x8000202f, ins_FormatR) + RUN(amomax_w, 0xa000202f, ins_FormatR) + RUN(amominu_w, 0xc000202f, ins_FormatR) + RUN(amomaxu_w, 0xe000202f, ins_FormatR) + RUN(sc_w, 0x1800202f, ins_FormatR) + } + ins_masked = ins_word & 0xf9f0707f; + [branch] + switch (ins_masked) { + RUN(lr_w, 0x1000202f, ins_FormatR) + } + ins_masked = ins_word & 0xfc00707f; + [branch] + switch (ins_masked) { + RUN(slli, 0x00001013, ins_FormatR) + RUN(srai, 0x40005013, ins_FormatR) + RUN(srli, 0x00005013, ins_FormatR) + } + ins_masked = ins_word & 0xfe007fff; + [branch] + switch (ins_masked) { + RUN(sfence_vma, 0x12000073, ins_FormatEmpty) + } + ins_masked = ins_word & 0xffffffff; + [forcecase] + switch (ins_masked) { + RUN(ebreak, 0x00100073, ins_FormatEmpty) + RUN(ecall, 0x00000073, ins_FormatEmpty) + RUN(mret, 0x30200073, ins_FormatEmpty) + RUN(sret, 0x10200073, ins_FormatEmpty) + RUN(uret, 0x00200073, ins_FormatEmpty) + RUN(wfi, 0x10500073, ins_FormatEmpty) + } + + ret.trap.en = true; + ret.trap.type = trap_IllegalInstruction; + ret.trap.value = ins_word; + return ret; +} + + +void emulate() { + uint ins_word = 0; + ins_ret ret = ins_ret_noop(); + if ((cpu.pc & 0x3) == 0) { + uint ins_addr = mmu_translate(ret, cpu.pc, MMU_ACCESS_FETCH); + + if (!ret.trap.en) { + ins_word = mem_get_instruction(ins_addr); + cpu.debug_last_ins = ins_word; + + ret = ins_select(ins_word, ret); + + if (ret.csr_write && !ret.trap.en) { + set_csr(ret.csr_write, ret.csr_val, ret); + + if (cpu.stall == STALL_MEMOP_COPY) { + [loop] + for (uint imc = 0; imc < 2; imc++) { + uint phys = mmu_translate(ret, + imc == 0 ? cpu.memop_src_v : cpu.memop_dst_v, + imc == 0 ? MMU_ACCESS_READ : MMU_ACCESS_WRITE); + if (ret.trap.en) break; + if (imc == 0) { + cpu.memop_src_p = phys; + } else { + cpu.memop_dst_p = phys; + } + } + } + } + + if (ret.mem_wr_size && !ret.trap.en) { + uint write_addr = mmu_translate(ret, ret.mem_wr_addr, MMU_ACCESS_WRITE); + if (!ret.trap.en) { + mem_set(write_addr, ret.mem_wr_value, ret.mem_wr_size / 8); + } + } + + if (!ret.trap.en && ret.write_reg) { + #define C(x) case x: cpu.xreg##x = ret.write_val; break; + if (ret.write_reg < 16) { + [flatten] + switch (ret.write_reg) { + C(1) C(2) C(3) + C(4) C(5) C(6) C(7) + C(8) C(9) C(10) C(11) + C(12) C(13) C(14) C(15) + } + } else { + [flatten] + switch (ret.write_reg) { + C(16) C(17) C(18) C(19) + C(20) C(21) C(22) C(23) + C(24) C(25) C(26) C(27) + C(28) C(29) C(30) C(31) + } + } + #undef C + } + } + } else { + ret.trap.en = true; + ret.trap.type = trap_InstructionAddressMisaligned; + ret.trap.value = cpu.pc; + } + + // handle CLINT IRQs + uint mip_override = read_csr_raw(CSR_MIP); + if (cpu.clint.msip) { + mip_override |= MIP_MSIP; + } + + cpu.clint.mtime_lo++; + cpu.clint.mtime_hi += cpu.clint.mtime_lo == 0 ? 1 : 0; + + if ((cpu.clint.mtimecmp_lo != 0 || cpu.clint.mtimecmp_hi != 0) && (cpu.clint.mtime_hi > cpu.clint.mtimecmp_hi || (cpu.clint.mtime_hi == cpu.clint.mtimecmp_hi && cpu.clint.mtime_lo >= cpu.clint.mtimecmp_lo))) { + mip_override |= MIP_MTIP; + } + + uart_tick(); + if (cpu.uart.interrupting) { + mip_override |= MIP_SEIP; + } + + /* if (ret.trap.en && cpu.clock <= 1) { */ + /* cpu.stall = STALL_ILLEGAL_ENTRY_POINT; */ + /* cpu.stall_count = ins_word; */ + /* cpu.trap_count = cpu.pc; */ + /* } */ + + // will write CSR_MIP if necessary + handle_irq_and_trap(ret, mip_override); + + /* if (ret.pc_val & 0x3) { */ + /* cpu.debug_arb_0 = ret.pc_val; */ + /* cpu.debug_arb_1 = ret.trap.en; */ + /* cpu.debug_arb_2 = ret.trap.type; */ + /* cpu.debug_arb_3 = ret.trap.value; */ + /* cpu.debug_do_tick = 0xffffffff; */ + /* _DoTick = cpu.debug_do_tick; */ + /* cpu.stall = STALL_FENCE; */ + /* } */ + + // ret.pc_val should be set to pc+4 by default + cpu.pc = ret.pc_val; +} + +#endif diff --git a/_Nix/rvc/src/emu.h.meta b/_Nix/rvc/src/emu.h.meta new file mode 100755 index 00000000..76ec664a --- /dev/null +++ b/_Nix/rvc/src/emu.h.meta @@ -0,0 +1,27 @@ +fileFormatVersion: 2 +guid: 7d6d4c997ea88674aaece642ba019c9b +PluginImporter: + externalObjects: {} + serializedVersion: 2 + iconMap: {} + executionOrder: {} + defineConstraints: [] + isPreloaded: 0 + isOverridable: 0 + isExplicitlyReferenced: 0 + validateReferences: 1 + platformData: + - first: + Any: + second: + enabled: 1 + settings: {} + - first: + Editor: Editor + second: + enabled: 0 + settings: + DefaultValueInitialized: true + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/header.p b/_Nix/rvc/src/header.p new file mode 100755 index 00000000..61fd726f --- /dev/null +++ b/_Nix/rvc/src/header.p @@ -0,0 +1,9 @@ + + +/* must match set/line count above, shift by two to ignore byte offset */ +#define RAM_L1_TAG(a) ((a >> 2) & 0xf) diff --git a/_Nix/rvc/src/header.p.meta b/_Nix/rvc/src/header.p.meta new file mode 100755 index 00000000..cd9b0953 --- /dev/null +++ b/_Nix/rvc/src/header.p.meta @@ -0,0 +1,7 @@ +fileFormatVersion: 2 +guid: ae7b6df175bef2448bd79480ac863a32 +DefaultImporter: + externalObjects: {} + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/ins.h b/_Nix/rvc/src/ins.h new file mode 100755 index 00000000..eda72ef9 --- /dev/null +++ b/_Nix/rvc/src/ins.h @@ -0,0 +1,119 @@ +#ifndef INS_H +#define INS_H + +typedef struct { + uint rs1; + uint rs2; + uint imm; +} FormatB; + +FormatB parse_FormatB(uint word) { + FormatB ret; + ret.rs1 = (word >> 15) & 0x1f; + ret.rs2 = (word >> 20) & 0x1f; + ret.imm = (word & 0x80000000 ? 0xfffff000 : 0) | + ((word << 4) & 0x00000800) | + ((word >> 20) & 0x000007e0) | + ((word >> 7) & 0x0000001e); + return ret; +} + +typedef struct { + uint csr; + uint rs; + uint rd; + uint value; +} FormatCSR; + +FormatCSR parse_FormatCSR(uint word) { + FormatCSR ret; + ret.csr = (word >> 20) & 0xfff; + ret.rs = (word >> 15) & 0x1f; + ret.rd = (word >> 7) & 0x1f; + return ret; +} + +typedef struct { + uint rd; + uint rs1; + uint imm; +} FormatI; + +FormatI parse_FormatI(uint word) { + FormatI ret; + ret.rd = (word >> 7) & 0x1f; + ret.rs1 = (word >> 15) & 0x1f; + ret.imm = (word & 0x80000000 ? 0xfffff800 : 0) | + ((word >> 20) & 0x000007ff); + return ret; +} + +typedef struct { + uint rd; + uint imm; +} FormatJ; + +FormatJ parse_FormatJ(uint word) { + FormatJ ret; + ret.rd = (word >> 7) & 0x1f; + ret.imm = (word & 0x80000000 ? 0xfff00000 : 0) | + (word & 0x000ff000) | + ((word & 0x00100000) >> 9) | + ((word & 0x7fe00000) >> 20); + return ret; +} + +typedef struct { + uint rd; + uint rs1; + uint rs2; + uint rs3; +} FormatR; + +FormatR parse_FormatR(uint word) { + FormatR ret; + ret.rd = (word >> 7) & 0x1f; + ret.rs1 = (word >> 15) & 0x1f; + ret.rs2 = (word >> 20) & 0x1f; + ret.rs3 = (word >> 27) & 0x1f; + return ret; +} + +typedef struct { + uint rs2; + uint addr; +} FormatS; + +FormatS parse_FormatS(uint word) { + FormatS ret; + uint rs1 = (word >> 15) & 0x1f; + ret.rs2 = (word >> 20) & 0x1f; + uint imm = (word & 0x80000000 ? 0xfffff000 : 0) | + ((word >> 20) & 0xfe0) | + ((word >> 7) & 0x1f); + // special case, FormatS is always treated this way: + ret.addr = xreg(rs1) + imm; + return ret; +} + +typedef struct { + uint rd; + uint imm; +} FormatU; + +FormatU parse_FormatU(uint word) { + FormatU ret; + ret.rd = (word >> 7) & 0x1f; + ret.imm = word & 0xfffff000; + return ret; +} + +typedef struct { +} FormatEmpty; + +FormatEmpty parse_FormatEmpty(uint word) { + FormatEmpty ret; + return ret; +} + +#endif diff --git a/_Nix/rvc/src/ins.h.meta b/_Nix/rvc/src/ins.h.meta new file mode 100755 index 00000000..30b07cf0 --- /dev/null +++ b/_Nix/rvc/src/ins.h.meta @@ -0,0 +1,27 @@ +fileFormatVersion: 2 +guid: d6882778be5bea443a97bfbf2e4a1b0c +PluginImporter: + externalObjects: {} + serializedVersion: 2 + iconMap: {} + executionOrder: {} + defineConstraints: [] + isPreloaded: 0 + isOverridable: 0 + isExplicitlyReferenced: 0 + validateReferences: 1 + platformData: + - first: + Any: + second: + enabled: 1 + settings: {} + - first: + Editor: Editor + second: + enabled: 0 + settings: + DefaultValueInitialized: true + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/main.o.meta b/_Nix/rvc/src/main.o.meta new file mode 100755 index 00000000..091211b9 --- /dev/null +++ b/_Nix/rvc/src/main.o.meta @@ -0,0 +1,7 @@ +fileFormatVersion: 2 +guid: 1ce6e63499e708744a872b825411dea9 +DefaultImporter: + externalObjects: {} + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/mem.h b/_Nix/rvc/src/mem.h new file mode 100755 index 00000000..aa4e0b90 --- /dev/null +++ b/_Nix/rvc/src/mem.h @@ -0,0 +1,280 @@ +#ifndef MEM_H +#define MEM_H + + + +/* must match set/line count above, shift by two to ignore byte offset */ +#define RAM_L1_TAG(a) ((a >> 2) & 0xf) + + +#define WORD_SIZE_NONE 0 +#define WORD_SIZE_BYTE 1 +#define WORD_SIZE_HALF 2 +#define WORD_SIZE_FULL 4 + +uint mem_get_instruction(uint addr) { + addr = addr & 0x7FFFFFFF; + uint idx = (addr >> 2) & 0x3; + addr = addr >> 4; + + uint4 raw = STATE_TEX[RAM_ADDR(addr)]; + return idx_uint4(raw, idx); +} + +// little endian, zero extended, addr must be aligned to word boundary +uint mem_get_word(uint addr) { + addr &= ~(0x3); + if (addr >= 0x1020 && addr <= 0x1fff) { + uint dtb_addr = addr - 0x1020; + uint dtb_idx = (dtb_addr >> 2) & 0x3; + dtb_addr = dtb_addr >> 4; + float4 full; + [branch] + switch (dtb_idx) { + case 0: + full = _Data_DTB_R[uint2(dtb_addr, 0)]; + break; + case 1: + full = _Data_DTB_G[uint2(dtb_addr, 0)]; + break; + case 2: + full = _Data_DTB_B[uint2(dtb_addr, 0)]; + break; + case 3: + full = _Data_DTB_A[uint2(dtb_addr, 0)]; + break; + } + return unpack_raw_float4(full); + } + + [branch] + switch (addr) { + // CLINT + case 0x02000000: return cpu.clint.msip ? 1 : 0; + + case 0x02004000: return cpu.clint.mtimecmp_lo; + case 0x02004004: return cpu.clint.mtimecmp_hi; + case 0x0200bff8: return cpu.clint.mtime_lo; + case 0x0200bffc: return cpu.clint.mtime_hi; + + // UART (first has rbr_thr_ier_iir, second has lcr_mcr_lsr_scr) + case 0x10000000: + uint ret = 0; + if ((UART_GET2(LCR) >> 7) == 0) { + uint rbr = UART_GET1(RBR); + UART_SET1(RBR, 0); + UART_SET2(LSR, (UART_GET2(LSR) & ~LSR_DATA_AVAILABLE)); + uart_update_iir(); + ret = rbr; + } + return ret | ((UART_GET2(LCR) >> 7 == 0 ? UART_GET1(IER) : 0) << 8) | (UART_GET1(IIR) << 16) | (UART_GET2(LCR) << 24); + /* case 0x10000001: return UART_GET2(LCR) >> 7 == 0 ? UART_GET1(IER) : 0; */ + /* case 0x10000002: return UART_GET1(IIR); */ + /* case 0x10000003: return UART_GET2(LCR); */ + case 0x10000004: return UART_GET2(MCR) | (UART_GET2(LSR) << 8) | (UART_GET2(SCR) << 24); + /* case 0x10000005: return UART_GET2(LSR); */ + /* case 0x10000007: return UART_GET2(SCR); */ + } + + if ((addr & 0x80000000) == 0) { + return 0; + } + addr = addr & 0x7FFFFFFF; + + if (addr >= RAM_MAX) { + return 0; + } + + return mem_get_cached_or_tex(addr); +} + +void mem_set_byte(uint addr, uint val) { + [branch] + switch (addr) { + // UART (first has rbr_thr_ier_iir, second has lcr_mcr_lsr_scr) + case 0x10000000: + if ((UART_GET2(LCR) >> 7) == 0) { + UART_SET1(THR, val); + UART_SET2(LSR, (UART_GET2(LSR) & ~LSR_THR_EMPTY)); + uart_update_iir(); + } + return; + case 0x10000001: + if (UART_GET2(LCR) >> 7 == 0) { + if ((UART_GET1(IER) & IER_THREINT_BIT) == 0 && + (val & IER_THREINT_BIT) != 0 && + UART_GET1(THR) == 0) + { + cpu.uart.thre_ip = true; + } + UART_SET1(IER, val); + uart_update_iir(); + } + return; + case 0x10000003: UART_SET2(LCR, val); return; + case 0x10000004: UART_SET2(MCR, val); return; + case 0x10000007: UART_SET2(SCR, val); return; + } + + if ((addr & 0x80000000) == 0) { + return; + } + addr = addr & 0x7FFFFFFF; + + if (addr >= RAM_MAX) { + return; + } + + // caching can cause stalls, so check for same value before storing + uint word_addr = addr & (~0x3); + uint cur_val = mem_get_cached_or_tex(word_addr); + val = (cur_val & ~(0xff << ((addr & 0x3)*8))) | (val << ((addr & 0x3)*8)); + if (val != cur_val) { + // put written value into L1 cache + mem_cache_bloom |= word_addr; + + [branch] + switch (RAM_L1_TAG(word_addr)) { +case 0: + if (cpu.cache.ram_l1_0_addr == 0xffffffff || cpu.cache.ram_l1_0_addr == word_addr) { cpu.cache.ram_l1_0_addr = word_addr; cpu.cache.ram_l1_0_val = val; return; } +else if (cpu.cache.ram_l1_16_addr == 0xffffffff || cpu.cache.ram_l1_16_addr == word_addr) { cpu.cache.ram_l1_16_addr = word_addr; cpu.cache.ram_l1_16_val = val; return; } +else if (cpu.cache.ram_l1_32_addr == 0xffffffff || cpu.cache.ram_l1_32_addr == word_addr) { cpu.cache.ram_l1_32_addr = word_addr; cpu.cache.ram_l1_32_val = val; return; } +else if (cpu.cache.ram_l1_48_addr == 0xffffffff || cpu.cache.ram_l1_48_addr == word_addr) { cpu.cache.ram_l1_48_addr = word_addr; cpu.cache.ram_l1_48_val = val; return; } +else if (cpu.cache.ram_l1_64_addr == 0xffffffff || cpu.cache.ram_l1_64_addr == word_addr) { cpu.cache.ram_l1_64_addr = word_addr; cpu.cache.ram_l1_64_val = val; return; } +break; +case 1: + if (cpu.cache.ram_l1_1_addr == 0xffffffff || cpu.cache.ram_l1_1_addr == word_addr) { cpu.cache.ram_l1_1_addr = word_addr; cpu.cache.ram_l1_1_val = val; return; } +else if (cpu.cache.ram_l1_17_addr == 0xffffffff || cpu.cache.ram_l1_17_addr == word_addr) { cpu.cache.ram_l1_17_addr = word_addr; cpu.cache.ram_l1_17_val = val; return; } +else if (cpu.cache.ram_l1_33_addr == 0xffffffff || cpu.cache.ram_l1_33_addr == word_addr) { cpu.cache.ram_l1_33_addr = word_addr; cpu.cache.ram_l1_33_val = val; return; } +else if (cpu.cache.ram_l1_49_addr == 0xffffffff || cpu.cache.ram_l1_49_addr == word_addr) { cpu.cache.ram_l1_49_addr = word_addr; cpu.cache.ram_l1_49_val = val; return; } +else if (cpu.cache.ram_l1_65_addr == 0xffffffff || cpu.cache.ram_l1_65_addr == word_addr) { cpu.cache.ram_l1_65_addr = word_addr; cpu.cache.ram_l1_65_val = val; return; } +break; +case 2: + if (cpu.cache.ram_l1_2_addr == 0xffffffff || cpu.cache.ram_l1_2_addr == word_addr) { cpu.cache.ram_l1_2_addr = word_addr; cpu.cache.ram_l1_2_val = val; return; } +else if (cpu.cache.ram_l1_18_addr == 0xffffffff || cpu.cache.ram_l1_18_addr == word_addr) { cpu.cache.ram_l1_18_addr = word_addr; cpu.cache.ram_l1_18_val = val; return; } +else if (cpu.cache.ram_l1_34_addr == 0xffffffff || cpu.cache.ram_l1_34_addr == word_addr) { cpu.cache.ram_l1_34_addr = word_addr; cpu.cache.ram_l1_34_val = val; return; } +else if (cpu.cache.ram_l1_50_addr == 0xffffffff || cpu.cache.ram_l1_50_addr == word_addr) { cpu.cache.ram_l1_50_addr = word_addr; cpu.cache.ram_l1_50_val = val; return; } +else if (cpu.cache.ram_l1_66_addr == 0xffffffff || cpu.cache.ram_l1_66_addr == word_addr) { cpu.cache.ram_l1_66_addr = word_addr; cpu.cache.ram_l1_66_val = val; return; } +break; +case 3: + if (cpu.cache.ram_l1_3_addr == 0xffffffff || cpu.cache.ram_l1_3_addr == word_addr) { cpu.cache.ram_l1_3_addr = word_addr; cpu.cache.ram_l1_3_val = val; return; } +else if (cpu.cache.ram_l1_19_addr == 0xffffffff || cpu.cache.ram_l1_19_addr == word_addr) { cpu.cache.ram_l1_19_addr = word_addr; cpu.cache.ram_l1_19_val = val; return; } +else if (cpu.cache.ram_l1_35_addr == 0xffffffff || cpu.cache.ram_l1_35_addr == word_addr) { cpu.cache.ram_l1_35_addr = word_addr; cpu.cache.ram_l1_35_val = val; return; } +else if (cpu.cache.ram_l1_51_addr == 0xffffffff || cpu.cache.ram_l1_51_addr == word_addr) { cpu.cache.ram_l1_51_addr = word_addr; cpu.cache.ram_l1_51_val = val; return; } +else if (cpu.cache.ram_l1_67_addr == 0xffffffff || cpu.cache.ram_l1_67_addr == word_addr) { cpu.cache.ram_l1_67_addr = word_addr; cpu.cache.ram_l1_67_val = val; return; } +break; +case 4: + if (cpu.cache.ram_l1_4_addr == 0xffffffff || cpu.cache.ram_l1_4_addr == word_addr) { cpu.cache.ram_l1_4_addr = word_addr; cpu.cache.ram_l1_4_val = val; return; } +else if (cpu.cache.ram_l1_20_addr == 0xffffffff || cpu.cache.ram_l1_20_addr == word_addr) { cpu.cache.ram_l1_20_addr = word_addr; cpu.cache.ram_l1_20_val = val; return; } +else if (cpu.cache.ram_l1_36_addr == 0xffffffff || cpu.cache.ram_l1_36_addr == word_addr) { cpu.cache.ram_l1_36_addr = word_addr; cpu.cache.ram_l1_36_val = val; return; } +else if (cpu.cache.ram_l1_52_addr == 0xffffffff || cpu.cache.ram_l1_52_addr == word_addr) { cpu.cache.ram_l1_52_addr = word_addr; cpu.cache.ram_l1_52_val = val; return; } +else if (cpu.cache.ram_l1_68_addr == 0xffffffff || cpu.cache.ram_l1_68_addr == word_addr) { cpu.cache.ram_l1_68_addr = word_addr; cpu.cache.ram_l1_68_val = val; return; } +break; +case 5: + if (cpu.cache.ram_l1_5_addr == 0xffffffff || cpu.cache.ram_l1_5_addr == word_addr) { cpu.cache.ram_l1_5_addr = word_addr; cpu.cache.ram_l1_5_val = val; return; } +else if (cpu.cache.ram_l1_21_addr == 0xffffffff || cpu.cache.ram_l1_21_addr == word_addr) { cpu.cache.ram_l1_21_addr = word_addr; cpu.cache.ram_l1_21_val = val; return; } +else if (cpu.cache.ram_l1_37_addr == 0xffffffff || cpu.cache.ram_l1_37_addr == word_addr) { cpu.cache.ram_l1_37_addr = word_addr; cpu.cache.ram_l1_37_val = val; return; } +else if (cpu.cache.ram_l1_53_addr == 0xffffffff || cpu.cache.ram_l1_53_addr == word_addr) { cpu.cache.ram_l1_53_addr = word_addr; cpu.cache.ram_l1_53_val = val; return; } +else if (cpu.cache.ram_l1_69_addr == 0xffffffff || cpu.cache.ram_l1_69_addr == word_addr) { cpu.cache.ram_l1_69_addr = word_addr; cpu.cache.ram_l1_69_val = val; return; } +break; +case 6: + if (cpu.cache.ram_l1_6_addr == 0xffffffff || cpu.cache.ram_l1_6_addr == word_addr) { cpu.cache.ram_l1_6_addr = word_addr; cpu.cache.ram_l1_6_val = val; return; } +else if (cpu.cache.ram_l1_22_addr == 0xffffffff || cpu.cache.ram_l1_22_addr == word_addr) { cpu.cache.ram_l1_22_addr = word_addr; cpu.cache.ram_l1_22_val = val; return; } +else if (cpu.cache.ram_l1_38_addr == 0xffffffff || cpu.cache.ram_l1_38_addr == word_addr) { cpu.cache.ram_l1_38_addr = word_addr; cpu.cache.ram_l1_38_val = val; return; } +else if (cpu.cache.ram_l1_54_addr == 0xffffffff || cpu.cache.ram_l1_54_addr == word_addr) { cpu.cache.ram_l1_54_addr = word_addr; cpu.cache.ram_l1_54_val = val; return; } +else if (cpu.cache.ram_l1_70_addr == 0xffffffff || cpu.cache.ram_l1_70_addr == word_addr) { cpu.cache.ram_l1_70_addr = word_addr; cpu.cache.ram_l1_70_val = val; return; } +break; +case 7: + if (cpu.cache.ram_l1_7_addr == 0xffffffff || cpu.cache.ram_l1_7_addr == word_addr) { cpu.cache.ram_l1_7_addr = word_addr; cpu.cache.ram_l1_7_val = val; return; } +else if (cpu.cache.ram_l1_23_addr == 0xffffffff || cpu.cache.ram_l1_23_addr == word_addr) { cpu.cache.ram_l1_23_addr = word_addr; cpu.cache.ram_l1_23_val = val; return; } +else if (cpu.cache.ram_l1_39_addr == 0xffffffff || cpu.cache.ram_l1_39_addr == word_addr) { cpu.cache.ram_l1_39_addr = word_addr; cpu.cache.ram_l1_39_val = val; return; } +else if (cpu.cache.ram_l1_55_addr == 0xffffffff || cpu.cache.ram_l1_55_addr == word_addr) { cpu.cache.ram_l1_55_addr = word_addr; cpu.cache.ram_l1_55_val = val; return; } +else if (cpu.cache.ram_l1_71_addr == 0xffffffff || cpu.cache.ram_l1_71_addr == word_addr) { cpu.cache.ram_l1_71_addr = word_addr; cpu.cache.ram_l1_71_val = val; return; } +break; +case 8: + if (cpu.cache.ram_l1_8_addr == 0xffffffff || cpu.cache.ram_l1_8_addr == word_addr) { cpu.cache.ram_l1_8_addr = word_addr; cpu.cache.ram_l1_8_val = val; return; } +else if (cpu.cache.ram_l1_24_addr == 0xffffffff || cpu.cache.ram_l1_24_addr == word_addr) { cpu.cache.ram_l1_24_addr = word_addr; cpu.cache.ram_l1_24_val = val; return; } +else if (cpu.cache.ram_l1_40_addr == 0xffffffff || cpu.cache.ram_l1_40_addr == word_addr) { cpu.cache.ram_l1_40_addr = word_addr; cpu.cache.ram_l1_40_val = val; return; } +else if (cpu.cache.ram_l1_56_addr == 0xffffffff || cpu.cache.ram_l1_56_addr == word_addr) { cpu.cache.ram_l1_56_addr = word_addr; cpu.cache.ram_l1_56_val = val; return; } +else if (cpu.cache.ram_l1_72_addr == 0xffffffff || cpu.cache.ram_l1_72_addr == word_addr) { cpu.cache.ram_l1_72_addr = word_addr; cpu.cache.ram_l1_72_val = val; return; } +break; +case 9: + if (cpu.cache.ram_l1_9_addr == 0xffffffff || cpu.cache.ram_l1_9_addr == word_addr) { cpu.cache.ram_l1_9_addr = word_addr; cpu.cache.ram_l1_9_val = val; return; } +else if (cpu.cache.ram_l1_25_addr == 0xffffffff || cpu.cache.ram_l1_25_addr == word_addr) { cpu.cache.ram_l1_25_addr = word_addr; cpu.cache.ram_l1_25_val = val; return; } +else if (cpu.cache.ram_l1_41_addr == 0xffffffff || cpu.cache.ram_l1_41_addr == word_addr) { cpu.cache.ram_l1_41_addr = word_addr; cpu.cache.ram_l1_41_val = val; return; } +else if (cpu.cache.ram_l1_57_addr == 0xffffffff || cpu.cache.ram_l1_57_addr == word_addr) { cpu.cache.ram_l1_57_addr = word_addr; cpu.cache.ram_l1_57_val = val; return; } +else if (cpu.cache.ram_l1_73_addr == 0xffffffff || cpu.cache.ram_l1_73_addr == word_addr) { cpu.cache.ram_l1_73_addr = word_addr; cpu.cache.ram_l1_73_val = val; return; } +break; +case 10: + if (cpu.cache.ram_l1_10_addr == 0xffffffff || cpu.cache.ram_l1_10_addr == word_addr) { cpu.cache.ram_l1_10_addr = word_addr; cpu.cache.ram_l1_10_val = val; return; } +else if (cpu.cache.ram_l1_26_addr == 0xffffffff || cpu.cache.ram_l1_26_addr == word_addr) { cpu.cache.ram_l1_26_addr = word_addr; cpu.cache.ram_l1_26_val = val; return; } +else if (cpu.cache.ram_l1_42_addr == 0xffffffff || cpu.cache.ram_l1_42_addr == word_addr) { cpu.cache.ram_l1_42_addr = word_addr; cpu.cache.ram_l1_42_val = val; return; } +else if (cpu.cache.ram_l1_58_addr == 0xffffffff || cpu.cache.ram_l1_58_addr == word_addr) { cpu.cache.ram_l1_58_addr = word_addr; cpu.cache.ram_l1_58_val = val; return; } +else if (cpu.cache.ram_l1_74_addr == 0xffffffff || cpu.cache.ram_l1_74_addr == word_addr) { cpu.cache.ram_l1_74_addr = word_addr; cpu.cache.ram_l1_74_val = val; return; } +break; +case 11: + if (cpu.cache.ram_l1_11_addr == 0xffffffff || cpu.cache.ram_l1_11_addr == word_addr) { cpu.cache.ram_l1_11_addr = word_addr; cpu.cache.ram_l1_11_val = val; return; } +else if (cpu.cache.ram_l1_27_addr == 0xffffffff || cpu.cache.ram_l1_27_addr == word_addr) { cpu.cache.ram_l1_27_addr = word_addr; cpu.cache.ram_l1_27_val = val; return; } +else if (cpu.cache.ram_l1_43_addr == 0xffffffff || cpu.cache.ram_l1_43_addr == word_addr) { cpu.cache.ram_l1_43_addr = word_addr; cpu.cache.ram_l1_43_val = val; return; } +else if (cpu.cache.ram_l1_59_addr == 0xffffffff || cpu.cache.ram_l1_59_addr == word_addr) { cpu.cache.ram_l1_59_addr = word_addr; cpu.cache.ram_l1_59_val = val; return; } +else if (cpu.cache.ram_l1_75_addr == 0xffffffff || cpu.cache.ram_l1_75_addr == word_addr) { cpu.cache.ram_l1_75_addr = word_addr; cpu.cache.ram_l1_75_val = val; return; } +break; +case 12: + if (cpu.cache.ram_l1_12_addr == 0xffffffff || cpu.cache.ram_l1_12_addr == word_addr) { cpu.cache.ram_l1_12_addr = word_addr; cpu.cache.ram_l1_12_val = val; return; } +else if (cpu.cache.ram_l1_28_addr == 0xffffffff || cpu.cache.ram_l1_28_addr == word_addr) { cpu.cache.ram_l1_28_addr = word_addr; cpu.cache.ram_l1_28_val = val; return; } +else if (cpu.cache.ram_l1_44_addr == 0xffffffff || cpu.cache.ram_l1_44_addr == word_addr) { cpu.cache.ram_l1_44_addr = word_addr; cpu.cache.ram_l1_44_val = val; return; } +else if (cpu.cache.ram_l1_60_addr == 0xffffffff || cpu.cache.ram_l1_60_addr == word_addr) { cpu.cache.ram_l1_60_addr = word_addr; cpu.cache.ram_l1_60_val = val; return; } +else if (cpu.cache.ram_l1_76_addr == 0xffffffff || cpu.cache.ram_l1_76_addr == word_addr) { cpu.cache.ram_l1_76_addr = word_addr; cpu.cache.ram_l1_76_val = val; return; } +break; +case 13: + if (cpu.cache.ram_l1_13_addr == 0xffffffff || cpu.cache.ram_l1_13_addr == word_addr) { cpu.cache.ram_l1_13_addr = word_addr; cpu.cache.ram_l1_13_val = val; return; } +else if (cpu.cache.ram_l1_29_addr == 0xffffffff || cpu.cache.ram_l1_29_addr == word_addr) { cpu.cache.ram_l1_29_addr = word_addr; cpu.cache.ram_l1_29_val = val; return; } +else if (cpu.cache.ram_l1_45_addr == 0xffffffff || cpu.cache.ram_l1_45_addr == word_addr) { cpu.cache.ram_l1_45_addr = word_addr; cpu.cache.ram_l1_45_val = val; return; } +else if (cpu.cache.ram_l1_61_addr == 0xffffffff || cpu.cache.ram_l1_61_addr == word_addr) { cpu.cache.ram_l1_61_addr = word_addr; cpu.cache.ram_l1_61_val = val; return; } +else if (cpu.cache.ram_l1_77_addr == 0xffffffff || cpu.cache.ram_l1_77_addr == word_addr) { cpu.cache.ram_l1_77_addr = word_addr; cpu.cache.ram_l1_77_val = val; return; } +break; +case 14: + if (cpu.cache.ram_l1_14_addr == 0xffffffff || cpu.cache.ram_l1_14_addr == word_addr) { cpu.cache.ram_l1_14_addr = word_addr; cpu.cache.ram_l1_14_val = val; return; } +else if (cpu.cache.ram_l1_30_addr == 0xffffffff || cpu.cache.ram_l1_30_addr == word_addr) { cpu.cache.ram_l1_30_addr = word_addr; cpu.cache.ram_l1_30_val = val; return; } +else if (cpu.cache.ram_l1_46_addr == 0xffffffff || cpu.cache.ram_l1_46_addr == word_addr) { cpu.cache.ram_l1_46_addr = word_addr; cpu.cache.ram_l1_46_val = val; return; } +else if (cpu.cache.ram_l1_62_addr == 0xffffffff || cpu.cache.ram_l1_62_addr == word_addr) { cpu.cache.ram_l1_62_addr = word_addr; cpu.cache.ram_l1_62_val = val; return; } +else if (cpu.cache.ram_l1_78_addr == 0xffffffff || cpu.cache.ram_l1_78_addr == word_addr) { cpu.cache.ram_l1_78_addr = word_addr; cpu.cache.ram_l1_78_val = val; return; } +break; +case 15: + if (cpu.cache.ram_l1_15_addr == 0xffffffff || cpu.cache.ram_l1_15_addr == word_addr) { cpu.cache.ram_l1_15_addr = word_addr; cpu.cache.ram_l1_15_val = val; return; } +else if (cpu.cache.ram_l1_31_addr == 0xffffffff || cpu.cache.ram_l1_31_addr == word_addr) { cpu.cache.ram_l1_31_addr = word_addr; cpu.cache.ram_l1_31_val = val; return; } +else if (cpu.cache.ram_l1_47_addr == 0xffffffff || cpu.cache.ram_l1_47_addr == word_addr) { cpu.cache.ram_l1_47_addr = word_addr; cpu.cache.ram_l1_47_val = val; return; } +else if (cpu.cache.ram_l1_63_addr == 0xffffffff || cpu.cache.ram_l1_63_addr == word_addr) { cpu.cache.ram_l1_63_addr = word_addr; cpu.cache.ram_l1_63_val = val; return; } +else if (cpu.cache.ram_l1_79_addr == 0xffffffff || cpu.cache.ram_l1_79_addr == word_addr) { cpu.cache.ram_l1_79_addr = word_addr; cpu.cache.ram_l1_79_val = val; return; } +break; + + } + + // L1 overflow, stall to avoid fillup until L2 flush (TODO) or next frame + cpu.cache.ram_l1_last_addr = word_addr; + cpu.cache.ram_l1_last_val = val; + cpu.stall = STALL_MEM_CACHE_L1; + } +} + +void mem_set(uint addr, uint val, uint word_size) { + + if (word_size == WORD_SIZE_FULL) { + [branch] + switch (addr & (~0x3)) { + // CLINT/timer - only supports full word write as optimization + case 0x02000000: cpu.clint.msip = (val & 1) != 0; return; + case 0x02004000: cpu.clint.mtimecmp_lo = val; return; + case 0x02004004: cpu.clint.mtimecmp_hi = val; return; + case 0x0200bff8: cpu.clint.mtime_lo = val; return; + case 0x0200bffc: cpu.clint.mtime_hi = val; return; + } + } + + [loop] + for (uint i = 0; i < word_size; i++) { + mem_set_byte(addr + i, (val >> (8 * i)) & 0xff); + } +} + +#endif diff --git a/_Nix/rvc/src/mem.h.meta b/_Nix/rvc/src/mem.h.meta new file mode 100755 index 00000000..3de36d94 --- /dev/null +++ b/_Nix/rvc/src/mem.h.meta @@ -0,0 +1,27 @@ +fileFormatVersion: 2 +guid: 0bef11a1bf62d8d4fb1cbb55d82036f5 +PluginImporter: + externalObjects: {} + serializedVersion: 2 + iconMap: {} + executionOrder: {} + defineConstraints: [] + isPreloaded: 0 + isOverridable: 0 + isExplicitlyReferenced: 0 + validateReferences: 1 + platformData: + - first: + Any: + second: + enabled: 1 + settings: {} + - first: + Editor: Editor + second: + enabled: 0 + settings: + DefaultValueInitialized: true + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/mem.h.pp b/_Nix/rvc/src/mem.h.pp new file mode 100755 index 00000000..cb3b235e --- /dev/null +++ b/_Nix/rvc/src/mem.h.pp @@ -0,0 +1,174 @@ +#ifndef MEM_H +#define MEM_H + + + +#define WORD_SIZE_NONE 0 +#define WORD_SIZE_BYTE 1 +#define WORD_SIZE_HALF 2 +#define WORD_SIZE_FULL 4 + +uint mem_get_instruction(uint addr) { + addr = addr & 0x7FFFFFFF; + uint idx = (addr >> 2) & 0x3; + addr = addr >> 4; + + uint4 raw = STATE_TEX[RAM_ADDR(addr)]; + return idx_uint4(raw, idx); +} + +// little endian, zero extended, addr must be aligned to word boundary +uint mem_get_word(uint addr) { + addr &= ~(0x3); + if (addr >= 0x1020 && addr <= 0x1fff) { + uint dtb_addr = addr - 0x1020; + uint dtb_idx = (dtb_addr >> 2) & 0x3; + dtb_addr = dtb_addr >> 4; + float4 full; + [branch] + switch (dtb_idx) { + case 0: + full = _Data_DTB_R[uint2(dtb_addr, 0)]; + break; + case 1: + full = _Data_DTB_G[uint2(dtb_addr, 0)]; + break; + case 2: + full = _Data_DTB_B[uint2(dtb_addr, 0)]; + break; + case 3: + full = _Data_DTB_A[uint2(dtb_addr, 0)]; + break; + } + return unpack_raw_float4(full); + } + + [branch] + switch (addr) { + // CLINT + case 0x02000000: return cpu.clint.msip ? 1 : 0; + + case 0x02004000: return cpu.clint.mtimecmp_lo; + case 0x02004004: return cpu.clint.mtimecmp_hi; + case 0x0200bff8: return cpu.clint.mtime_lo; + case 0x0200bffc: return cpu.clint.mtime_hi; + + // UART (first has rbr_thr_ier_iir, second has lcr_mcr_lsr_scr) + case 0x10000000: + uint ret = 0; + if ((UART_GET2(LCR) >> 7) == 0) { + uint rbr = UART_GET1(RBR); + UART_SET1(RBR, 0); + UART_SET2(LSR, (UART_GET2(LSR) & ~LSR_DATA_AVAILABLE)); + uart_update_iir(); + ret = rbr; + } + return ret | ((UART_GET2(LCR) >> 7 == 0 ? UART_GET1(IER) : 0) << 8) | (UART_GET1(IIR) << 16) | (UART_GET2(LCR) << 24); + /* case 0x10000001: return UART_GET2(LCR) >> 7 == 0 ? UART_GET1(IER) : 0; */ + /* case 0x10000002: return UART_GET1(IIR); */ + /* case 0x10000003: return UART_GET2(LCR); */ + case 0x10000004: return UART_GET2(MCR) | (UART_GET2(LSR) << 8) | (UART_GET2(SCR) << 24); + /* case 0x10000005: return UART_GET2(LSR); */ + /* case 0x10000007: return UART_GET2(SCR); */ + } + + if ((addr & 0x80000000) == 0) { + return 0; + } + addr = addr & 0x7FFFFFFF; + + if (addr >= RAM_MAX) { + return 0; + } + + return mem_get_cached_or_tex(addr); +} + +void mem_set_byte(uint addr, uint val) { + [branch] + switch (addr) { + // UART (first has rbr_thr_ier_iir, second has lcr_mcr_lsr_scr) + case 0x10000000: + if ((UART_GET2(LCR) >> 7) == 0) { + UART_SET1(THR, val); + UART_SET2(LSR, (UART_GET2(LSR) & ~LSR_THR_EMPTY)); + uart_update_iir(); + } + return; + case 0x10000001: + if (UART_GET2(LCR) >> 7 == 0) { + if ((UART_GET1(IER) & IER_THREINT_BIT) == 0 && + (val & IER_THREINT_BIT) != 0 && + UART_GET1(THR) == 0) + { + cpu.uart.thre_ip = true; + } + UART_SET1(IER, val); + uart_update_iir(); + } + return; + case 0x10000003: UART_SET2(LCR, val); return; + case 0x10000004: UART_SET2(MCR, val); return; + case 0x10000007: UART_SET2(SCR, val); return; + } + + if ((addr & 0x80000000) == 0) { + return; + } + addr = addr & 0x7FFFFFFF; + + if (addr >= RAM_MAX) { + return; + } + + // caching can cause stalls, so check for same value before storing + uint word_addr = addr & (~0x3); + uint cur_val = mem_get_cached_or_tex(word_addr); + val = (cur_val & ~(0xff << ((addr & 0x3)*8))) | (val << ((addr & 0x3)*8)); + if (val != cur_val) { + // put written value into L1 cache + mem_cache_bloom |= word_addr; + + [branch] + switch (RAM_L1_TAG(word_addr)) { + + } + + // L1 overflow, stall to avoid fillup until L2 flush (TODO) or next frame + cpu.cache.ram_l1_last_addr = word_addr; + cpu.cache.ram_l1_last_val = val; + cpu.stall = STALL_MEM_CACHE_L1; + } +} + +void mem_set(uint addr, uint val, uint word_size) { + + if (word_size == WORD_SIZE_FULL) { + [branch] + switch (addr & (~0x3)) { + // CLINT/timer - only supports full word write as optimization + case 0x02000000: cpu.clint.msip = (val & 1) != 0; return; + case 0x02004000: cpu.clint.mtimecmp_lo = val; return; + case 0x02004004: cpu.clint.mtimecmp_hi = val; return; + case 0x0200bff8: cpu.clint.mtime_lo = val; return; + case 0x0200bffc: cpu.clint.mtime_hi = val; return; + } + } + + [loop] + for (uint i = 0; i < word_size; i++) { + mem_set_byte(addr + i, (val >> (8 * i)) & 0xff); + } +} + +#endif diff --git a/_Nix/rvc/src/mem.h.pp.meta b/_Nix/rvc/src/mem.h.pp.meta new file mode 100755 index 00000000..57a3d6d3 --- /dev/null +++ b/_Nix/rvc/src/mem.h.pp.meta @@ -0,0 +1,7 @@ +fileFormatVersion: 2 +guid: acbbe536ff8198442bc21259d2d4de83 +DefaultImporter: + externalObjects: {} + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/mmu.h b/_Nix/rvc/src/mmu.h new file mode 100755 index 00000000..64b6d2c9 --- /dev/null +++ b/_Nix/rvc/src/mmu.h @@ -0,0 +1,154 @@ +#ifndef MMU_H +#define MMU_H + +#include "types.h" + +void mmu_update(uint satp) { + cpu.mmu.mode = satp >> 31; + cpu.mmu.ppn = satp & 0x7fffffff; +} + +#include "mem.h" +#include "trap.h" + +#define MMU_MODE_OFF 0 +#define MMU_MODE_SV32 1 + +#define MMU_ACCESS_FETCH 0 +#define MMU_ACCESS_READ 1 +#define MMU_ACCESS_WRITE 2 + +#define PAGESIZE 4096 +#define PTESIZE 4 + +#define ADDR_PART_OFFSET(x) ((x >> 0) & 0xfff) +#define ADDR_PART_PN0(x) ((x >> 12) & 0x3ff) +#define ADDR_PART_PN1(x) ((x >> 22) & 0xfff) + +typedef struct { + bool v, r, w, x, u, g, a, d; + uint rsw; + uint ppn0; + uint ppn1; +} mmu_page; + +uint get_trap_type(uint mode) { + return mode == MMU_ACCESS_FETCH ? trap_InstructionPageFault : + (mode == MMU_ACCESS_READ ? trap_LoadPageFault : trap_StorePageFault); +} + +uint get_effective_privilege(out uint sum, out uint mxr) { + uint mstatus = read_csr_raw(CSR_MSTATUS); + sum = (mstatus >> 18) & 0x1; + mxr = (mstatus >> 19) & 0x1; + if ((mstatus >> 17) & 0x1) { + // TODO: Check if this shouldn't be 9 + return (mstatus >> 11) & 0x3; + } + return cpu.csr.privilege; +} + +mmu_page load_page(uint addr) { + uint data = mem_get_cached_or_tex(addr & 0x7ffffffc); + mmu_page ret; + #define BOOL(name, bit) ret.name = (data >> bit) & 0x1; + BOOL(v, 0) + BOOL(r, 1) + BOOL(w, 2) + BOOL(x, 3) + BOOL(u, 4) + BOOL(g, 5) + BOOL(a, 6) + BOOL(d, 7) + #undef BOOL + ret.rsw = (data >> 8) & 0x3; + ret.ppn0 = (data >> 10) & 0x3ff; + ret.ppn1 = (data >> 20) & 0xfff; + return ret; +} + +uint mmu_translate(inout ins_ret ins, uint addr, uint mode) { + if (cpu.mmu.mode == MMU_MODE_OFF) { + return addr; + } + + #define FAULT \ + ins.trap.en = true; \ + ins.trap.type = get_trap_type(mode); \ + ins.trap.value = addr; \ + return 0; + + uint sum, mxr; + uint priv = get_effective_privilege(sum, mxr); + + // machine mode fetch will always use physical addresses, otherwise 'mxr' + // defines if paging will be used + if (priv == PRIV_MACHINE || (cpu.csr.privilege == PRIV_MACHINE && mode == MMU_ACCESS_FETCH)) { + return addr; + } + + bool super; + mmu_page page; + + // perform two-layer page walk, exit early in case of super page + [loop] + for (uint im = 0; im < 2; im++) { + uint page_addr = im == 0 ? + (cpu.mmu.ppn * PAGESIZE + ADDR_PART_PN1(addr) * PTESIZE) : + ((page.ppn0 | (page.ppn1 << 10)) * PAGESIZE + ADDR_PART_PN0(addr) * PTESIZE); + page = load_page(page_addr); + super = im == 0; + + if (!page.v || (!page.r && page.w)) { + FAULT + } + + if (page.r || page.x) { + break; + } else if (im == 1) { + // non-leaf page at bottom level + FAULT + } + } + + // PTE has been found, permission check + bool perm = + priv == PRIV_MACHINE || // machine can read everything + (priv == PRIV_USER && page.u) || // this is a user page + (priv == PRIV_SUPERVISOR && (!page.u || sum)); // supervisor page or SUM + bool access = + (mode == MMU_ACCESS_FETCH && page.x) || + (mode == MMU_ACCESS_READ && (page.r || (page.x && mxr))) || + (mode == MMU_ACCESS_WRITE && page.w); + bool allowed = perm && access; + + if (!allowed) { + /* access permission fault */ + FAULT + } + + if (super && page.ppn0 != 0) { + /* misaligned super page fault */ + FAULT + } + + if (!page.a || (mode == MMU_ACCESS_WRITE && !page.d)) { + /* access/dirty bit fault */ + FAULT + } + + // translation success + uint pa = ADDR_PART_OFFSET(addr); + pa |= super ? ADDR_PART_PN0(addr) << 12 : page.ppn0 << 12; + pa |= page.ppn1 << 22; + + /* cpu.debug_arb_1 = pa; */ + + /* if (!(pa & 0x80000000) || (pa & 0x7fffffff) >= RAM_MAX) { */ + /* FAULT */ + /* } */ + + return pa; +} + +#endif diff --git a/_Nix/rvc/src/mmu.h.meta b/_Nix/rvc/src/mmu.h.meta new file mode 100755 index 00000000..4c6ea840 --- /dev/null +++ b/_Nix/rvc/src/mmu.h.meta @@ -0,0 +1,27 @@ +fileFormatVersion: 2 +guid: 218f78fedbddea54e933dbc3c74bdddc +PluginImporter: + externalObjects: {} + serializedVersion: 2 + iconMap: {} + executionOrder: {} + defineConstraints: [] + isPreloaded: 0 + isOverridable: 0 + isExplicitlyReferenced: 0 + validateReferences: 1 + platformData: + - first: + Any: + second: + enabled: 1 + settings: {} + - first: + Editor: Editor + second: + enabled: 0 + settings: + DefaultValueInitialized: true + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/trap.h b/_Nix/rvc/src/trap.h new file mode 100755 index 00000000..3371cd4f --- /dev/null +++ b/_Nix/rvc/src/trap.h @@ -0,0 +1,179 @@ +#ifndef TRAP_H +#define TRAP_H + +#define PRIV_USER 0 +#define PRIV_SUPERVISOR 1 +#define PRIV_MACHINE 3 + +#define interrupt_offset 0x80000000 +#define trap_InstructionAddressMisaligned 0 +#define trap_InstructionAccessFault 1 +#define trap_IllegalInstruction 2 +#define trap_Breakpoint 3 +#define trap_LoadAddressMisaligned 4 +#define trap_LoadAccessFault 5 +#define trap_StoreAddressMisaligned 6 +#define trap_StoreAccessFault 7 +#define trap_EnvironmentCallFromUMode 8 +#define trap_EnvironmentCallFromSMode 9 +#define trap_EnvironmentCallFromMMode 11 +#define trap_InstructionPageFault 12 +#define trap_LoadPageFault 13 +#define trap_StorePageFault 15 +#define trap_UserSoftwareInterrupt interrupt_offset + 0 +#define trap_SupervisorSoftwareInterrupt interrupt_offset + 1 +#define trap_MachineSoftwareInterrupt interrupt_offset + 3 +#define trap_UserTimerInterrupt interrupt_offset + 4 +#define trap_SupervisorTimerInterrupt interrupt_offset + 5 +#define trap_MachineTimerInterrupt interrupt_offset + 7 +#define trap_UserExternalInterrupt interrupt_offset + 8 +#define trap_SupervisorExternalInterrupt interrupt_offset + 9 +#define trap_MachineExternalInterrupt interrupt_offset + 11 + +#define MIP_MEIP 0x800 +#define MIP_MTIP 0x080 +#define MIP_MSIP 0x008 +#define MIP_SEIP 0x200 +#define MIP_STIP 0x020 +#define MIP_SSIP 0x002 +#define MIP_ALL 0xAAA // MIP_MEIP | MIP_MTIP | MIP_MSIP | MIP_SEIP | MIP_STIP | MIP_SSIP + +// include after trap_ definitions +#include "csr.h" + +// returns true if IRQ was handled or !is_interrupt +bool handle_trap(inout ins_ret ret, bool is_interrupt, uint c_mie) { + trap t = ret.trap; + uint current_privilege = cpu.csr.privilege; + + uint mdeleg = read_csr_raw(is_interrupt ? CSR_MIDELEG : CSR_MEDELEG); + uint sdeleg = read_csr_raw(is_interrupt ? CSR_SIDELEG : CSR_SEDELEG); + uint pos = t.type & 0xFFFF; + + uint new_privilege = ((mdeleg >> pos) & 1) == 0 ? + PRIV_MACHINE : (((sdeleg >> pos) & 1) == 0 ? + PRIV_SUPERVISOR : PRIV_USER); + + uint mstatus = read_csr_raw(CSR_MSTATUS); + uint sstatus = read_csr_raw(CSR_SSTATUS); + uint current_status = current_privilege == PRIV_MACHINE ? + mstatus : (current_privilege == PRIV_SUPERVISOR ? + sstatus : read_csr_raw(CSR_USTATUS)); + + // check if IRQ should be ignored + if (is_interrupt) { + uint ie = new_privilege == PRIV_MACHINE ? + c_mie : (new_privilege == PRIV_SUPERVISOR ? + read_csr_raw(CSR_SIE) : read_csr_raw(CSR_UIE)); + + uint current_mie = (current_status >> 3) & 1; + uint current_sie = (current_status >> 1) & 1; + uint current_uie = current_status & 1; + + uint msie = (ie >> 3) & 1; + uint ssie = (ie >> 1) & 1; + uint usie = ie & 1; + + uint mtie = (ie >> 7) & 1; + uint stie = (ie >> 5) & 1; + uint utie = (ie >> 4) & 1; + + uint meie = (ie >> 11) & 1; + uint seie = (ie >> 9) & 1; + uint ueie = (ie >> 8) & 1; + + if (new_privilege < current_privilege) { + return false; + } else if (new_privilege == current_privilege) { + if (current_privilege == PRIV_MACHINE && current_mie == 0) { + return false; + } else if (current_privilege == PRIV_SUPERVISOR && current_sie == 0) { + return false; + } else if (current_privilege == PRIV_USER && current_uie == 0) { + return false; + } + } + +#define MASK(trap, val) case trap: if (val == 0) { return false; } else { break; } + switch (t.type) { + MASK(trap_UserSoftwareInterrupt, usie) + MASK(trap_SupervisorSoftwareInterrupt, ssie) + MASK(trap_MachineSoftwareInterrupt, msie) + MASK(trap_UserTimerInterrupt, utie) + MASK(trap_SupervisorTimerInterrupt, stie) + MASK(trap_MachineTimerInterrupt, mtie) + MASK(trap_UserExternalInterrupt, ueie) + MASK(trap_SupervisorExternalInterrupt, seie) + MASK(trap_MachineExternalInterrupt, meie) + } +#undef MASK + } + + // should be handled, do that now + cpu.csr.privilege = new_privilege; + + uint csr_epc_addr = new_privilege == PRIV_MACHINE ? CSR_MEPC : (new_privilege == PRIV_SUPERVISOR ? CSR_SEPC : CSR_UEPC); + uint csr_cause_addr = new_privilege == PRIV_MACHINE ? CSR_MCAUSE : (new_privilege == PRIV_SUPERVISOR ? CSR_SCAUSE : CSR_UCAUSE); + uint csr_tval_addr = new_privilege == PRIV_MACHINE ? CSR_MTVAL : (new_privilege == PRIV_SUPERVISOR ? CSR_STVAL : CSR_UTVAL); + uint csr_tvec_addr = new_privilege == PRIV_MACHINE ? CSR_MTVEC : (new_privilege == PRIV_SUPERVISOR ? CSR_STVEC : CSR_UTVEC); + + write_csr_raw(csr_epc_addr, is_interrupt ? ret.pc_val : cpu.pc); + write_csr_raw(csr_cause_addr, t.type); + write_csr_raw(csr_tval_addr, t.value); + ret.pc_val = read_csr_raw(csr_tvec_addr); + + if ((ret.pc_val & 0x3) != 0) { + // vectored handler + ret.pc_val = (ret.pc_val & ~0x3) + 4*pos; + } + + // NOTE: No user mode interrupt/exception handling! + if (new_privilege == PRIV_MACHINE) { + uint mie = (mstatus >> 3) & 1; + uint new_status = (mstatus & ~0x1888) | (mie << 7) | (current_privilege << 11); + write_csr_raw(CSR_MSTATUS, new_status); + } else { // PRIV_SUPERVISOR + uint sie = (sstatus >> 1) & 1; + uint new_status = (sstatus & ~0x122) | (sie << 5) | ((current_privilege & 1) << 8); + write_csr_raw(CSR_SSTATUS, new_status); + } + + return true; +} + +void handle_irq_and_trap(inout ins_ret ret, uint mip_override) { + bool trap = ret.trap.en; + uint mip_reset = MIP_ALL; + uint mie = read_csr_raw(CSR_MIE); + + if (!trap) { + uint mirq = mip_override & mie; +#define HANDLE(mip, ttype) case mip: mip_reset = mip; ret.trap.en = true; ret.trap.type = ttype; break; + switch (mirq & MIP_ALL) { + HANDLE(MIP_MEIP, trap_MachineExternalInterrupt) + HANDLE(MIP_MSIP, trap_MachineSoftwareInterrupt) + HANDLE(MIP_MTIP, trap_MachineTimerInterrupt) + HANDLE(MIP_SEIP, trap_SupervisorExternalInterrupt) + HANDLE(MIP_SSIP, trap_SupervisorSoftwareInterrupt) + HANDLE(MIP_STIP, trap_SupervisorTimerInterrupt) + } +#undef HANDLE + } + + bool irq = mip_reset != MIP_ALL; + if (trap || irq) { + uint new_mip = mip_override; + bool handled = handle_trap(ret, irq, mie); + if (handled) { + cpu.trap_count++; + } + if (handled && irq) { + // reset MIP value since IRQ was handled + // this implies that mip_reset is not MIP_ALL + new_mip = mip_override & (~mip_reset); + } + write_csr_raw(CSR_MIP, new_mip); + } +} + +#endif diff --git a/_Nix/rvc/src/trap.h.meta b/_Nix/rvc/src/trap.h.meta new file mode 100755 index 00000000..866befb9 --- /dev/null +++ b/_Nix/rvc/src/trap.h.meta @@ -0,0 +1,27 @@ +fileFormatVersion: 2 +guid: 806b90a2bfec8914a99cefc09f4bc755 +PluginImporter: + externalObjects: {} + serializedVersion: 2 + iconMap: {} + executionOrder: {} + defineConstraints: [] + isPreloaded: 0 + isOverridable: 0 + isExplicitlyReferenced: 0 + validateReferences: 1 + platformData: + - first: + Any: + second: + enabled: 1 + settings: {} + - first: + Editor: Editor + second: + enabled: 0 + settings: + DefaultValueInitialized: true + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/types.h b/_Nix/rvc/src/types.h new file mode 100755 index 00000000..48bb041e --- /dev/null +++ b/_Nix/rvc/src/types.h @@ -0,0 +1,2305 @@ +#ifndef TYPES_H +#define TYPES_H + + + +/* must match set/line count above, shift by two to ignore byte offset */ +#define RAM_L1_TAG(a) ((a >> 2) & 0xf) + + +#define STALL_EXIT_CALL 1 +#define STALL_CSR_CACHE 2 +#define STALL_MEM_CACHE_L1 3 +#define STALL_MEM_CACHE_L2 4 +#define STALL_ILLEGAL_ENTRY_POINT 5 +#define STALL_UART 6 +#define STALL_FENCE 7 +#define STALL_MEMOP_COPY 8 + + + +// STRUCT TYPES +typedef struct { + uint csr_cache_0_addr; uint csr_cache_0_val; + uint csr_cache_1_addr; uint csr_cache_1_val; + uint csr_cache_2_addr; uint csr_cache_2_val; + uint csr_cache_3_addr; uint csr_cache_3_val; + uint csr_cache_4_addr; uint csr_cache_4_val; + uint csr_cache_5_addr; uint csr_cache_5_val; + uint csr_cache_6_addr; uint csr_cache_6_val; + uint csr_cache_7_addr; uint csr_cache_7_val; + uint csr_cache_8_addr; uint csr_cache_8_val; + uint csr_cache_9_addr; uint csr_cache_9_val; + uint csr_cache_10_addr; uint csr_cache_10_val; + uint csr_cache_11_addr; uint csr_cache_11_val; + uint csr_cache_12_addr; uint csr_cache_12_val; + uint csr_cache_13_addr; uint csr_cache_13_val; + uint csr_cache_14_addr; uint csr_cache_14_val; + uint csr_cache_15_addr; uint csr_cache_15_val; + uint ram_l1_0_addr; uint ram_l1_0_val; + uint ram_l1_16_addr; uint ram_l1_16_val; + uint ram_l1_32_addr; uint ram_l1_32_val; + uint ram_l1_48_addr; uint ram_l1_48_val; + uint ram_l1_64_addr; uint ram_l1_64_val; + uint ram_l1_1_addr; uint ram_l1_1_val; + uint ram_l1_17_addr; uint ram_l1_17_val; + uint ram_l1_33_addr; uint ram_l1_33_val; + uint ram_l1_49_addr; uint ram_l1_49_val; + uint ram_l1_65_addr; uint ram_l1_65_val; + uint ram_l1_2_addr; uint ram_l1_2_val; + uint ram_l1_18_addr; uint ram_l1_18_val; + uint ram_l1_34_addr; uint ram_l1_34_val; + uint ram_l1_50_addr; uint ram_l1_50_val; + uint ram_l1_66_addr; uint ram_l1_66_val; + uint ram_l1_3_addr; uint ram_l1_3_val; + uint ram_l1_19_addr; uint ram_l1_19_val; + uint ram_l1_35_addr; uint ram_l1_35_val; + uint ram_l1_51_addr; uint ram_l1_51_val; + uint ram_l1_67_addr; uint ram_l1_67_val; + uint ram_l1_4_addr; uint ram_l1_4_val; + uint ram_l1_20_addr; uint ram_l1_20_val; + uint ram_l1_36_addr; uint ram_l1_36_val; + uint ram_l1_52_addr; uint ram_l1_52_val; + uint ram_l1_68_addr; uint ram_l1_68_val; + uint ram_l1_5_addr; uint ram_l1_5_val; + uint ram_l1_21_addr; uint ram_l1_21_val; + uint ram_l1_37_addr; uint ram_l1_37_val; + uint ram_l1_53_addr; uint ram_l1_53_val; + uint ram_l1_69_addr; uint ram_l1_69_val; + uint ram_l1_6_addr; uint ram_l1_6_val; + uint ram_l1_22_addr; uint ram_l1_22_val; + uint ram_l1_38_addr; uint ram_l1_38_val; + uint ram_l1_54_addr; uint ram_l1_54_val; + uint ram_l1_70_addr; uint ram_l1_70_val; + uint ram_l1_7_addr; uint ram_l1_7_val; + uint ram_l1_23_addr; uint ram_l1_23_val; + uint ram_l1_39_addr; uint ram_l1_39_val; + uint ram_l1_55_addr; uint ram_l1_55_val; + uint ram_l1_71_addr; uint ram_l1_71_val; + uint ram_l1_8_addr; uint ram_l1_8_val; + uint ram_l1_24_addr; uint ram_l1_24_val; + uint ram_l1_40_addr; uint ram_l1_40_val; + uint ram_l1_56_addr; uint ram_l1_56_val; + uint ram_l1_72_addr; uint ram_l1_72_val; + uint ram_l1_9_addr; uint ram_l1_9_val; + uint ram_l1_25_addr; uint ram_l1_25_val; + uint ram_l1_41_addr; uint ram_l1_41_val; + uint ram_l1_57_addr; uint ram_l1_57_val; + uint ram_l1_73_addr; uint ram_l1_73_val; + uint ram_l1_10_addr; uint ram_l1_10_val; + uint ram_l1_26_addr; uint ram_l1_26_val; + uint ram_l1_42_addr; uint ram_l1_42_val; + uint ram_l1_58_addr; uint ram_l1_58_val; + uint ram_l1_74_addr; uint ram_l1_74_val; + uint ram_l1_11_addr; uint ram_l1_11_val; + uint ram_l1_27_addr; uint ram_l1_27_val; + uint ram_l1_43_addr; uint ram_l1_43_val; + uint ram_l1_59_addr; uint ram_l1_59_val; + uint ram_l1_75_addr; uint ram_l1_75_val; + uint ram_l1_12_addr; uint ram_l1_12_val; + uint ram_l1_28_addr; uint ram_l1_28_val; + uint ram_l1_44_addr; uint ram_l1_44_val; + uint ram_l1_60_addr; uint ram_l1_60_val; + uint ram_l1_76_addr; uint ram_l1_76_val; + uint ram_l1_13_addr; uint ram_l1_13_val; + uint ram_l1_29_addr; uint ram_l1_29_val; + uint ram_l1_45_addr; uint ram_l1_45_val; + uint ram_l1_61_addr; uint ram_l1_61_val; + uint ram_l1_77_addr; uint ram_l1_77_val; + uint ram_l1_14_addr; uint ram_l1_14_val; + uint ram_l1_30_addr; uint ram_l1_30_val; + uint ram_l1_46_addr; uint ram_l1_46_val; + uint ram_l1_62_addr; uint ram_l1_62_val; + uint ram_l1_78_addr; uint ram_l1_78_val; + uint ram_l1_15_addr; uint ram_l1_15_val; + uint ram_l1_31_addr; uint ram_l1_31_val; + uint ram_l1_47_addr; uint ram_l1_47_val; + uint ram_l1_63_addr; uint ram_l1_63_val; + uint ram_l1_79_addr; uint ram_l1_79_val; + uint ram_l1_last_addr;uint ram_l1_last_val; +} cache_t; + +typedef struct { + uint privilege; +} csr_state; + +typedef struct { + uint rbr_thr_ier_iir; + uint lcr_mcr_lsr_scr; + bool thre_ip; + bool interrupting; + uint input_tag; +} uart_state; + +typedef struct { + bool msip; + uint mtimecmp_lo; + uint mtimecmp_hi; + uint mtime_lo; + uint mtime_hi; +} clint_state; + +typedef struct { + uint ptr; + uint buf0; + uint buf1; + uint buf2; + uint buf3; + uint buf4; + uint buf5; + uint buf6; + uint buf7; + uint buf8; + uint buf9; + uint buf10; + uint buf11; + uint buf12; + uint buf13; + uint buf14; + uint buf15; + uint buf16; + uint buf17; + uint buf18; + uint buf19; + uint buf20; + uint buf21; + uint buf22; + uint buf23; + uint buf24; + uint buf25; + uint buf26; + uint buf27; + uint buf28; + uint buf29; + uint buf30; + uint buf31; + uint buf32; + uint buf33; + uint buf34; + uint buf35; + uint buf36; + uint buf37; + uint buf38; + uint buf39; + uint buf40; + uint buf41; + uint buf42; + uint buf43; + uint buf44; + uint buf45; + uint buf46; + uint buf47; + uint buf48; + uint buf49; + uint buf50; + uint buf51; + uint buf52; + uint buf53; + uint buf54; + uint buf55; + uint buf56; + uint buf57; + uint buf58; + uint buf59; + uint buf60; + uint buf61; + uint buf62; + uint buf63; + +} uart_buffer; + +typedef struct { + uint mode; + uint ppn; +} mmu_state; + +typedef struct { + uint stall; + uint clock; + uint commits; + uint xreg0; + uint xreg1; + uint xreg2; + uint xreg3; + uint xreg4; + uint xreg5; + uint xreg6; + uint xreg7; + uint xreg8; + uint xreg9; + uint xreg10; + uint xreg11; + uint xreg12; + uint xreg13; + uint xreg14; + uint xreg15; + uint xreg16; + uint xreg17; + uint xreg18; + uint xreg19; + uint xreg20; + uint xreg21; + uint xreg22; + uint xreg23; + uint xreg24; + uint xreg25; + uint xreg26; + uint xreg27; + uint xreg28; + uint xreg29; + uint xreg30; + uint xreg31; + + uint pc; + csr_state csr; + clint_state clint; + uart_state uart; + uart_buffer uart_buffer; + mmu_state mmu; + + bool reservation_en; + uint reservation_addr; + + uint memop_src_v; + uint memop_dst_v; + uint memop_src_p; + uint memop_dst_p; + uint memop_n; + + uint stall_count; + uint trap_count; + + uint debug_do_tick; + uint debug_last_ins; + uint debug_last_stall; + + + + uint debug_arb_0; + + + + + + + + + cache_t cache; +} cpu_t; + +typedef struct { + bool en; + bool irq; + uint type; + uint value; +} trap; + +typedef struct { + uint write_reg; + uint write_val; + uint pc_val; + uint csr_write; + uint csr_val; + uint mem_wr_addr; + uint mem_wr_value; + uint mem_wr_size; + trap trap; +} ins_ret; + +// GLOBAL STATICS +static cpu_t cpu; + +// TYPE HELPERS +ins_ret ins_ret_noop() { + ins_ret ret = (ins_ret)0; + ret.pc_val = cpu.pc + 4; + return ret; +} + +uint sign_extend(uint x, uint b) { + uint m = ((uint)1) << (b - 1); + return (x ^ m) - m; +} + +uint xreg(uint i) { + #define C(x) case x: return cpu.xreg##x; + if (i < 16) { + [flatten] + switch (i) { + C(0) C(1) C(2) C(3) + C(4) C(5) C(6) C(7) + C(8) C(9) C(10) C(11) + C(12) C(13) C(14) C(15) + } + } else { + [flatten] + switch (i) { + C(16) C(17) C(18) C(19) + C(20) C(21) C(22) C(23) + C(24) C(25) C(26) C(27) + C(28) C(29) C(30) C(31) + } + } + return 0xdeadc0de; + #undef C +} + +// ENCODE/DECODE LOGIC (state serialization into self texture) + + + +void decode(uint udonUartPtr) { + cpu = (cpu_t)0; + + cpu.cache.csr_cache_0_addr = uint(4294967295); + cpu.cache.csr_cache_0_val = uint(3735930846); + cpu.cache.csr_cache_1_addr = uint(4294967295); + cpu.cache.csr_cache_1_val = uint(3735930846); + cpu.cache.csr_cache_2_addr = uint(4294967295); + cpu.cache.csr_cache_2_val = uint(3735930846); + cpu.cache.csr_cache_3_addr = uint(4294967295); + cpu.cache.csr_cache_3_val = uint(3735930846); + cpu.cache.csr_cache_4_addr = uint(4294967295); + cpu.cache.csr_cache_4_val = uint(3735930846); + cpu.cache.csr_cache_5_addr = uint(4294967295); + cpu.cache.csr_cache_5_val = uint(3735930846); + cpu.cache.csr_cache_6_addr = uint(4294967295); + cpu.cache.csr_cache_6_val = uint(3735930846); + cpu.cache.csr_cache_7_addr = uint(4294967295); + cpu.cache.csr_cache_7_val = uint(3735930846); + cpu.cache.csr_cache_8_addr = uint(4294967295); + cpu.cache.csr_cache_8_val = uint(3735930846); + cpu.cache.csr_cache_9_addr = uint(4294967295); + cpu.cache.csr_cache_9_val = uint(3735930846); + cpu.cache.csr_cache_10_addr = uint(4294967295); + cpu.cache.csr_cache_10_val = uint(3735930846); + cpu.cache.csr_cache_11_addr = uint(4294967295); + cpu.cache.csr_cache_11_val = uint(3735930846); + cpu.cache.csr_cache_12_addr = uint(4294967295); + cpu.cache.csr_cache_12_val = uint(3735930846); + cpu.cache.csr_cache_13_addr = uint(4294967295); + cpu.cache.csr_cache_13_val = uint(3735930846); + cpu.cache.csr_cache_14_addr = uint(4294967295); + cpu.cache.csr_cache_14_val = uint(3735930846); + cpu.cache.csr_cache_15_addr = uint(4294967295); + cpu.cache.csr_cache_15_val = uint(3735930846); + cpu.cache.ram_l1_0_addr = uint(4294967295); + cpu.cache.ram_l1_0_val = uint(3735931102); + cpu.cache.ram_l1_16_addr = uint(4294967295); + cpu.cache.ram_l1_16_val = uint(3735931102); + cpu.cache.ram_l1_32_addr = uint(4294967295); + cpu.cache.ram_l1_32_val = uint(3735931102); + cpu.cache.ram_l1_48_addr = uint(4294967295); + cpu.cache.ram_l1_48_val = uint(3735931102); + cpu.cache.ram_l1_64_addr = uint(4294967295); + cpu.cache.ram_l1_64_val = uint(3735931102); + cpu.cache.ram_l1_1_addr = uint(4294967295); + cpu.cache.ram_l1_1_val = uint(3735931102); + cpu.cache.ram_l1_17_addr = uint(4294967295); + cpu.cache.ram_l1_17_val = uint(3735931102); + cpu.cache.ram_l1_33_addr = uint(4294967295); + cpu.cache.ram_l1_33_val = uint(3735931102); + cpu.cache.ram_l1_49_addr = uint(4294967295); + cpu.cache.ram_l1_49_val = uint(3735931102); + cpu.cache.ram_l1_65_addr = uint(4294967295); + cpu.cache.ram_l1_65_val = uint(3735931102); + cpu.cache.ram_l1_2_addr = uint(4294967295); + cpu.cache.ram_l1_2_val = uint(3735931102); + cpu.cache.ram_l1_18_addr = uint(4294967295); + cpu.cache.ram_l1_18_val = uint(3735931102); + cpu.cache.ram_l1_34_addr = uint(4294967295); + cpu.cache.ram_l1_34_val = uint(3735931102); + cpu.cache.ram_l1_50_addr = uint(4294967295); + cpu.cache.ram_l1_50_val = uint(3735931102); + cpu.cache.ram_l1_66_addr = uint(4294967295); + cpu.cache.ram_l1_66_val = uint(3735931102); + cpu.cache.ram_l1_3_addr = uint(4294967295); + cpu.cache.ram_l1_3_val = uint(3735931102); + cpu.cache.ram_l1_19_addr = uint(4294967295); + cpu.cache.ram_l1_19_val = uint(3735931102); + cpu.cache.ram_l1_35_addr = uint(4294967295); + cpu.cache.ram_l1_35_val = uint(3735931102); + cpu.cache.ram_l1_51_addr = uint(4294967295); + cpu.cache.ram_l1_51_val = uint(3735931102); + cpu.cache.ram_l1_67_addr = uint(4294967295); + cpu.cache.ram_l1_67_val = uint(3735931102); + cpu.cache.ram_l1_4_addr = uint(4294967295); + cpu.cache.ram_l1_4_val = uint(3735931102); + cpu.cache.ram_l1_20_addr = uint(4294967295); + cpu.cache.ram_l1_20_val = uint(3735931102); + cpu.cache.ram_l1_36_addr = uint(4294967295); + cpu.cache.ram_l1_36_val = uint(3735931102); + cpu.cache.ram_l1_52_addr = uint(4294967295); + cpu.cache.ram_l1_52_val = uint(3735931102); + cpu.cache.ram_l1_68_addr = uint(4294967295); + cpu.cache.ram_l1_68_val = uint(3735931102); + cpu.cache.ram_l1_5_addr = uint(4294967295); + cpu.cache.ram_l1_5_val = uint(3735931102); + cpu.cache.ram_l1_21_addr = uint(4294967295); + cpu.cache.ram_l1_21_val = uint(3735931102); + cpu.cache.ram_l1_37_addr = uint(4294967295); + cpu.cache.ram_l1_37_val = uint(3735931102); + cpu.cache.ram_l1_53_addr = uint(4294967295); + cpu.cache.ram_l1_53_val = uint(3735931102); + cpu.cache.ram_l1_69_addr = uint(4294967295); + cpu.cache.ram_l1_69_val = uint(3735931102); + cpu.cache.ram_l1_6_addr = uint(4294967295); + cpu.cache.ram_l1_6_val = uint(3735931102); + cpu.cache.ram_l1_22_addr = uint(4294967295); + cpu.cache.ram_l1_22_val = uint(3735931102); + cpu.cache.ram_l1_38_addr = uint(4294967295); + cpu.cache.ram_l1_38_val = uint(3735931102); + cpu.cache.ram_l1_54_addr = uint(4294967295); + cpu.cache.ram_l1_54_val = uint(3735931102); + cpu.cache.ram_l1_70_addr = uint(4294967295); + cpu.cache.ram_l1_70_val = uint(3735931102); + cpu.cache.ram_l1_7_addr = uint(4294967295); + cpu.cache.ram_l1_7_val = uint(3735931102); + cpu.cache.ram_l1_23_addr = uint(4294967295); + cpu.cache.ram_l1_23_val = uint(3735931102); + cpu.cache.ram_l1_39_addr = uint(4294967295); + cpu.cache.ram_l1_39_val = uint(3735931102); + cpu.cache.ram_l1_55_addr = uint(4294967295); + cpu.cache.ram_l1_55_val = uint(3735931102); + cpu.cache.ram_l1_71_addr = uint(4294967295); + cpu.cache.ram_l1_71_val = uint(3735931102); + cpu.cache.ram_l1_8_addr = uint(4294967295); + cpu.cache.ram_l1_8_val = uint(3735931102); + cpu.cache.ram_l1_24_addr = uint(4294967295); + cpu.cache.ram_l1_24_val = uint(3735931102); + cpu.cache.ram_l1_40_addr = uint(4294967295); + cpu.cache.ram_l1_40_val = uint(3735931102); + cpu.cache.ram_l1_56_addr = uint(4294967295); + cpu.cache.ram_l1_56_val = uint(3735931102); + cpu.cache.ram_l1_72_addr = uint(4294967295); + cpu.cache.ram_l1_72_val = uint(3735931102); + cpu.cache.ram_l1_9_addr = uint(4294967295); + cpu.cache.ram_l1_9_val = uint(3735931102); + cpu.cache.ram_l1_25_addr = uint(4294967295); + cpu.cache.ram_l1_25_val = uint(3735931102); + cpu.cache.ram_l1_41_addr = uint(4294967295); + cpu.cache.ram_l1_41_val = uint(3735931102); + cpu.cache.ram_l1_57_addr = uint(4294967295); + cpu.cache.ram_l1_57_val = uint(3735931102); + cpu.cache.ram_l1_73_addr = uint(4294967295); + cpu.cache.ram_l1_73_val = uint(3735931102); + cpu.cache.ram_l1_10_addr = uint(4294967295); + cpu.cache.ram_l1_10_val = uint(3735931102); + cpu.cache.ram_l1_26_addr = uint(4294967295); + cpu.cache.ram_l1_26_val = uint(3735931102); + cpu.cache.ram_l1_42_addr = uint(4294967295); + cpu.cache.ram_l1_42_val = uint(3735931102); + cpu.cache.ram_l1_58_addr = uint(4294967295); + cpu.cache.ram_l1_58_val = uint(3735931102); + cpu.cache.ram_l1_74_addr = uint(4294967295); + cpu.cache.ram_l1_74_val = uint(3735931102); + cpu.cache.ram_l1_11_addr = uint(4294967295); + cpu.cache.ram_l1_11_val = uint(3735931102); + cpu.cache.ram_l1_27_addr = uint(4294967295); + cpu.cache.ram_l1_27_val = uint(3735931102); + cpu.cache.ram_l1_43_addr = uint(4294967295); + cpu.cache.ram_l1_43_val = uint(3735931102); + cpu.cache.ram_l1_59_addr = uint(4294967295); + cpu.cache.ram_l1_59_val = uint(3735931102); + cpu.cache.ram_l1_75_addr = uint(4294967295); + cpu.cache.ram_l1_75_val = uint(3735931102); + cpu.cache.ram_l1_12_addr = uint(4294967295); + cpu.cache.ram_l1_12_val = uint(3735931102); + cpu.cache.ram_l1_28_addr = uint(4294967295); + cpu.cache.ram_l1_28_val = uint(3735931102); + cpu.cache.ram_l1_44_addr = uint(4294967295); + cpu.cache.ram_l1_44_val = uint(3735931102); + cpu.cache.ram_l1_60_addr = uint(4294967295); + cpu.cache.ram_l1_60_val = uint(3735931102); + cpu.cache.ram_l1_76_addr = uint(4294967295); + cpu.cache.ram_l1_76_val = uint(3735931102); + cpu.cache.ram_l1_13_addr = uint(4294967295); + cpu.cache.ram_l1_13_val = uint(3735931102); + cpu.cache.ram_l1_29_addr = uint(4294967295); + cpu.cache.ram_l1_29_val = uint(3735931102); + cpu.cache.ram_l1_45_addr = uint(4294967295); + cpu.cache.ram_l1_45_val = uint(3735931102); + cpu.cache.ram_l1_61_addr = uint(4294967295); + cpu.cache.ram_l1_61_val = uint(3735931102); + cpu.cache.ram_l1_77_addr = uint(4294967295); + cpu.cache.ram_l1_77_val = uint(3735931102); + cpu.cache.ram_l1_14_addr = uint(4294967295); + cpu.cache.ram_l1_14_val = uint(3735931102); + cpu.cache.ram_l1_30_addr = uint(4294967295); + cpu.cache.ram_l1_30_val = uint(3735931102); + cpu.cache.ram_l1_46_addr = uint(4294967295); + cpu.cache.ram_l1_46_val = uint(3735931102); + cpu.cache.ram_l1_62_addr = uint(4294967295); + cpu.cache.ram_l1_62_val = uint(3735931102); + cpu.cache.ram_l1_78_addr = uint(4294967295); + cpu.cache.ram_l1_78_val = uint(3735931102); + cpu.cache.ram_l1_15_addr = uint(4294967295); + cpu.cache.ram_l1_15_val = uint(3735931102); + cpu.cache.ram_l1_31_addr = uint(4294967295); + cpu.cache.ram_l1_31_val = uint(3735931102); + cpu.cache.ram_l1_47_addr = uint(4294967295); + cpu.cache.ram_l1_47_val = uint(3735931102); + cpu.cache.ram_l1_63_addr = uint(4294967295); + cpu.cache.ram_l1_63_val = uint(3735931102); + cpu.cache.ram_l1_79_addr = uint(4294967295); + cpu.cache.ram_l1_79_val = uint(3735931102); + cpu.cache.ram_l1_last_addr = uint(4294967295); + cpu.cache.ram_l1_last_val = uint(3735931358); + cpu.csr.privilege = uint(idx_uint4(STATE_TEX[uint2(48, 0)], 2)); + cpu.uart.rbr_thr_ier_iir = uint(idx_uint4(STATE_TEX[uint2(48, 0)], 3)); + cpu.uart.lcr_mcr_lsr_scr = uint(idx_uint4(STATE_TEX[uint2(49, 0)], 0)); + cpu.uart.thre_ip = bool(idx_uint4(STATE_TEX[uint2(49, 0)], 1)); + cpu.uart.interrupting = bool(idx_uint4(STATE_TEX[uint2(49, 0)], 2)); + cpu.uart.input_tag = uint(idx_uint4(STATE_TEX[uint2(49, 0)], 3)); + cpu.clint.msip = bool(idx_uint4(STATE_TEX[uint2(50, 0)], 0)); + cpu.clint.mtimecmp_lo = uint(idx_uint4(STATE_TEX[uint2(50, 0)], 1)); + cpu.clint.mtimecmp_hi = uint(idx_uint4(STATE_TEX[uint2(50, 0)], 2)); + cpu.clint.mtime_lo = uint(idx_uint4(STATE_TEX[uint2(50, 0)], 3)); + cpu.clint.mtime_hi = uint(idx_uint4(STATE_TEX[uint2(51, 0)], 0)); + cpu.uart_buffer.ptr = uint(idx_uint4(STATE_TEX[uint2(51, 0)], 1)); + cpu.uart_buffer.buf0 = uint(idx_uint4(STATE_TEX[uint2(51, 0)], 2)); + cpu.uart_buffer.buf1 = uint(idx_uint4(STATE_TEX[uint2(51, 0)], 3)); + cpu.uart_buffer.buf2 = uint(idx_uint4(STATE_TEX[uint2(52, 0)], 0)); + cpu.uart_buffer.buf3 = uint(idx_uint4(STATE_TEX[uint2(52, 0)], 1)); + cpu.uart_buffer.buf4 = uint(idx_uint4(STATE_TEX[uint2(52, 0)], 2)); + cpu.uart_buffer.buf5 = uint(idx_uint4(STATE_TEX[uint2(52, 0)], 3)); + cpu.uart_buffer.buf6 = uint(idx_uint4(STATE_TEX[uint2(53, 0)], 0)); + cpu.uart_buffer.buf7 = uint(idx_uint4(STATE_TEX[uint2(53, 0)], 1)); + cpu.uart_buffer.buf8 = uint(idx_uint4(STATE_TEX[uint2(53, 0)], 2)); + cpu.uart_buffer.buf9 = uint(idx_uint4(STATE_TEX[uint2(53, 0)], 3)); + cpu.uart_buffer.buf10 = uint(idx_uint4(STATE_TEX[uint2(54, 0)], 0)); + cpu.uart_buffer.buf11 = uint(idx_uint4(STATE_TEX[uint2(54, 0)], 1)); + cpu.uart_buffer.buf12 = uint(idx_uint4(STATE_TEX[uint2(54, 0)], 2)); + cpu.uart_buffer.buf13 = uint(idx_uint4(STATE_TEX[uint2(54, 0)], 3)); + cpu.uart_buffer.buf14 = uint(idx_uint4(STATE_TEX[uint2(55, 0)], 0)); + cpu.uart_buffer.buf15 = uint(idx_uint4(STATE_TEX[uint2(55, 0)], 1)); + cpu.uart_buffer.buf16 = uint(idx_uint4(STATE_TEX[uint2(55, 0)], 2)); + cpu.uart_buffer.buf17 = uint(idx_uint4(STATE_TEX[uint2(55, 0)], 3)); + cpu.uart_buffer.buf18 = uint(idx_uint4(STATE_TEX[uint2(56, 0)], 0)); + cpu.uart_buffer.buf19 = uint(idx_uint4(STATE_TEX[uint2(56, 0)], 1)); + cpu.uart_buffer.buf20 = uint(idx_uint4(STATE_TEX[uint2(56, 0)], 2)); + cpu.uart_buffer.buf21 = uint(idx_uint4(STATE_TEX[uint2(56, 0)], 3)); + cpu.uart_buffer.buf22 = uint(idx_uint4(STATE_TEX[uint2(57, 0)], 0)); + cpu.uart_buffer.buf23 = uint(idx_uint4(STATE_TEX[uint2(57, 0)], 1)); + cpu.uart_buffer.buf24 = uint(idx_uint4(STATE_TEX[uint2(57, 0)], 2)); + cpu.uart_buffer.buf25 = uint(idx_uint4(STATE_TEX[uint2(57, 0)], 3)); + cpu.uart_buffer.buf26 = uint(idx_uint4(STATE_TEX[uint2(58, 0)], 0)); + cpu.uart_buffer.buf27 = uint(idx_uint4(STATE_TEX[uint2(58, 0)], 1)); + cpu.uart_buffer.buf28 = uint(idx_uint4(STATE_TEX[uint2(58, 0)], 2)); + cpu.uart_buffer.buf29 = uint(idx_uint4(STATE_TEX[uint2(58, 0)], 3)); + cpu.uart_buffer.buf30 = uint(idx_uint4(STATE_TEX[uint2(59, 0)], 0)); + cpu.uart_buffer.buf31 = uint(idx_uint4(STATE_TEX[uint2(59, 0)], 1)); + cpu.uart_buffer.buf32 = uint(idx_uint4(STATE_TEX[uint2(59, 0)], 2)); + cpu.uart_buffer.buf33 = uint(idx_uint4(STATE_TEX[uint2(59, 0)], 3)); + cpu.uart_buffer.buf34 = uint(idx_uint4(STATE_TEX[uint2(60, 0)], 0)); + cpu.uart_buffer.buf35 = uint(idx_uint4(STATE_TEX[uint2(60, 0)], 1)); + cpu.uart_buffer.buf36 = uint(idx_uint4(STATE_TEX[uint2(60, 0)], 2)); + cpu.uart_buffer.buf37 = uint(idx_uint4(STATE_TEX[uint2(60, 0)], 3)); + cpu.uart_buffer.buf38 = uint(idx_uint4(STATE_TEX[uint2(61, 0)], 0)); + cpu.uart_buffer.buf39 = uint(idx_uint4(STATE_TEX[uint2(61, 0)], 1)); + cpu.uart_buffer.buf40 = uint(idx_uint4(STATE_TEX[uint2(61, 0)], 2)); + cpu.uart_buffer.buf41 = uint(idx_uint4(STATE_TEX[uint2(61, 0)], 3)); + cpu.uart_buffer.buf42 = uint(idx_uint4(STATE_TEX[uint2(62, 0)], 0)); + cpu.uart_buffer.buf43 = uint(idx_uint4(STATE_TEX[uint2(62, 0)], 1)); + cpu.uart_buffer.buf44 = uint(idx_uint4(STATE_TEX[uint2(62, 0)], 2)); + cpu.uart_buffer.buf45 = uint(idx_uint4(STATE_TEX[uint2(62, 0)], 3)); + cpu.uart_buffer.buf46 = uint(idx_uint4(STATE_TEX[uint2(63, 0)], 0)); + cpu.uart_buffer.buf47 = uint(idx_uint4(STATE_TEX[uint2(63, 0)], 1)); + cpu.uart_buffer.buf48 = uint(idx_uint4(STATE_TEX[uint2(63, 0)], 2)); + cpu.uart_buffer.buf49 = uint(idx_uint4(STATE_TEX[uint2(63, 0)], 3)); + cpu.uart_buffer.buf50 = uint(idx_uint4(STATE_TEX[uint2(64, 0)], 0)); + cpu.uart_buffer.buf51 = uint(idx_uint4(STATE_TEX[uint2(64, 0)], 1)); + cpu.uart_buffer.buf52 = uint(idx_uint4(STATE_TEX[uint2(64, 0)], 2)); + cpu.uart_buffer.buf53 = uint(idx_uint4(STATE_TEX[uint2(64, 0)], 3)); + cpu.uart_buffer.buf54 = uint(idx_uint4(STATE_TEX[uint2(65, 0)], 0)); + cpu.uart_buffer.buf55 = uint(idx_uint4(STATE_TEX[uint2(65, 0)], 1)); + cpu.uart_buffer.buf56 = uint(idx_uint4(STATE_TEX[uint2(65, 0)], 2)); + cpu.uart_buffer.buf57 = uint(idx_uint4(STATE_TEX[uint2(65, 0)], 3)); + cpu.uart_buffer.buf58 = uint(idx_uint4(STATE_TEX[uint2(66, 0)], 0)); + cpu.uart_buffer.buf59 = uint(idx_uint4(STATE_TEX[uint2(66, 0)], 1)); + cpu.uart_buffer.buf60 = uint(idx_uint4(STATE_TEX[uint2(66, 0)], 2)); + cpu.uart_buffer.buf61 = uint(idx_uint4(STATE_TEX[uint2(66, 0)], 3)); + cpu.uart_buffer.buf62 = uint(idx_uint4(STATE_TEX[uint2(67, 0)], 0)); + cpu.uart_buffer.buf63 = uint(idx_uint4(STATE_TEX[uint2(67, 0)], 1)); + cpu.mmu.mode = uint(idx_uint4(STATE_TEX[uint2(67, 0)], 2)); + cpu.mmu.ppn = uint(idx_uint4(STATE_TEX[uint2(67, 0)], 3)); + cpu.stall = uint(idx_uint4(STATE_TEX[uint2(68, 0)], 0)); + cpu.clock = uint(idx_uint4(STATE_TEX[uint2(68, 0)], 1)); + cpu.commits = uint(idx_uint4(STATE_TEX[uint2(68, 0)], 2)); + cpu.xreg0 = uint(idx_uint4(STATE_TEX[uint2(68, 0)], 3)); + cpu.xreg1 = uint(idx_uint4(STATE_TEX[uint2(69, 0)], 0)); + cpu.xreg2 = uint(idx_uint4(STATE_TEX[uint2(69, 0)], 1)); + cpu.xreg3 = uint(idx_uint4(STATE_TEX[uint2(69, 0)], 2)); + cpu.xreg4 = uint(idx_uint4(STATE_TEX[uint2(69, 0)], 3)); + cpu.xreg5 = uint(idx_uint4(STATE_TEX[uint2(70, 0)], 0)); + cpu.xreg6 = uint(idx_uint4(STATE_TEX[uint2(70, 0)], 1)); + cpu.xreg7 = uint(idx_uint4(STATE_TEX[uint2(70, 0)], 2)); + cpu.xreg8 = uint(idx_uint4(STATE_TEX[uint2(70, 0)], 3)); + cpu.xreg9 = uint(idx_uint4(STATE_TEX[uint2(71, 0)], 0)); + cpu.xreg10 = uint(idx_uint4(STATE_TEX[uint2(71, 0)], 1)); + cpu.xreg11 = uint(idx_uint4(STATE_TEX[uint2(71, 0)], 2)); + cpu.xreg12 = uint(idx_uint4(STATE_TEX[uint2(71, 0)], 3)); + cpu.xreg13 = uint(idx_uint4(STATE_TEX[uint2(72, 0)], 0)); + cpu.xreg14 = uint(idx_uint4(STATE_TEX[uint2(72, 0)], 1)); + cpu.xreg15 = uint(idx_uint4(STATE_TEX[uint2(72, 0)], 2)); + cpu.xreg16 = uint(idx_uint4(STATE_TEX[uint2(72, 0)], 3)); + cpu.xreg17 = uint(idx_uint4(STATE_TEX[uint2(73, 0)], 0)); + cpu.xreg18 = uint(idx_uint4(STATE_TEX[uint2(73, 0)], 1)); + cpu.xreg19 = uint(idx_uint4(STATE_TEX[uint2(73, 0)], 2)); + cpu.xreg20 = uint(idx_uint4(STATE_TEX[uint2(73, 0)], 3)); + cpu.xreg21 = uint(idx_uint4(STATE_TEX[uint2(74, 0)], 0)); + cpu.xreg22 = uint(idx_uint4(STATE_TEX[uint2(74, 0)], 1)); + cpu.xreg23 = uint(idx_uint4(STATE_TEX[uint2(74, 0)], 2)); + cpu.xreg24 = uint(idx_uint4(STATE_TEX[uint2(74, 0)], 3)); + cpu.xreg25 = uint(idx_uint4(STATE_TEX[uint2(75, 0)], 0)); + cpu.xreg26 = uint(idx_uint4(STATE_TEX[uint2(75, 0)], 1)); + cpu.xreg27 = uint(idx_uint4(STATE_TEX[uint2(75, 0)], 2)); + cpu.xreg28 = uint(idx_uint4(STATE_TEX[uint2(75, 0)], 3)); + cpu.xreg29 = uint(idx_uint4(STATE_TEX[uint2(76, 0)], 0)); + cpu.xreg30 = uint(idx_uint4(STATE_TEX[uint2(76, 0)], 1)); + cpu.xreg31 = uint(idx_uint4(STATE_TEX[uint2(76, 0)], 2)); + cpu.pc = uint(idx_uint4(STATE_TEX[uint2(76, 0)], 3)); + cpu.reservation_en = bool(idx_uint4(STATE_TEX[uint2(77, 0)], 0)); + cpu.reservation_addr = uint(idx_uint4(STATE_TEX[uint2(77, 0)], 1)); + cpu.memop_src_v = uint(idx_uint4(STATE_TEX[uint2(77, 0)], 2)); + cpu.memop_dst_v = uint(idx_uint4(STATE_TEX[uint2(77, 0)], 3)); + cpu.memop_src_p = uint(idx_uint4(STATE_TEX[uint2(78, 0)], 0)); + cpu.memop_dst_p = uint(idx_uint4(STATE_TEX[uint2(78, 0)], 1)); + cpu.memop_n = uint(idx_uint4(STATE_TEX[uint2(78, 0)], 2)); + cpu.stall_count = uint(idx_uint4(STATE_TEX[uint2(78, 0)], 3)); + cpu.trap_count = uint(idx_uint4(STATE_TEX[uint2(79, 0)], 0)); + cpu.debug_do_tick = uint(idx_uint4(STATE_TEX[uint2(79, 0)], 1)); + cpu.debug_last_ins = uint(idx_uint4(STATE_TEX[uint2(79, 0)], 2)); + cpu.debug_last_stall = uint(idx_uint4(STATE_TEX[uint2(79, 0)], 3)); + cpu.debug_arb_0 = uint(idx_uint4(STATE_TEX[uint2(80, 0)], 0)); + + + if (cpu.stall == STALL_UART && udonUartPtr == cpu.uart_buffer.ptr) { + cpu.stall = 0; + } +} + +#ifdef PASS_COMMIT +void decode_for_commit() { + cpu = (cpu_t)0; + + cpu.cache.csr_cache_0_addr = uint(idx_uint4(STATE_TEX[uint2(0, 0)], 0)); + cpu.cache.csr_cache_0_val = uint(idx_uint4(STATE_TEX[uint2(0, 0)], 1)); + cpu.cache.csr_cache_1_addr = uint(idx_uint4(STATE_TEX[uint2(0, 0)], 2)); + cpu.cache.csr_cache_1_val = uint(idx_uint4(STATE_TEX[uint2(0, 0)], 3)); + cpu.cache.csr_cache_2_addr = uint(idx_uint4(STATE_TEX[uint2(1, 0)], 0)); + cpu.cache.csr_cache_2_val = uint(idx_uint4(STATE_TEX[uint2(1, 0)], 1)); + cpu.cache.csr_cache_3_addr = uint(idx_uint4(STATE_TEX[uint2(1, 0)], 2)); + cpu.cache.csr_cache_3_val = uint(idx_uint4(STATE_TEX[uint2(1, 0)], 3)); + cpu.cache.csr_cache_4_addr = uint(idx_uint4(STATE_TEX[uint2(2, 0)], 0)); + cpu.cache.csr_cache_4_val = uint(idx_uint4(STATE_TEX[uint2(2, 0)], 1)); + cpu.cache.csr_cache_5_addr = uint(idx_uint4(STATE_TEX[uint2(2, 0)], 2)); + cpu.cache.csr_cache_5_val = uint(idx_uint4(STATE_TEX[uint2(2, 0)], 3)); + cpu.cache.csr_cache_6_addr = uint(idx_uint4(STATE_TEX[uint2(3, 0)], 0)); + cpu.cache.csr_cache_6_val = uint(idx_uint4(STATE_TEX[uint2(3, 0)], 1)); + cpu.cache.csr_cache_7_addr = uint(idx_uint4(STATE_TEX[uint2(3, 0)], 2)); + cpu.cache.csr_cache_7_val = uint(idx_uint4(STATE_TEX[uint2(3, 0)], 3)); + cpu.cache.csr_cache_8_addr = uint(idx_uint4(STATE_TEX[uint2(4, 0)], 0)); + cpu.cache.csr_cache_8_val = uint(idx_uint4(STATE_TEX[uint2(4, 0)], 1)); + cpu.cache.csr_cache_9_addr = uint(idx_uint4(STATE_TEX[uint2(4, 0)], 2)); + cpu.cache.csr_cache_9_val = uint(idx_uint4(STATE_TEX[uint2(4, 0)], 3)); + cpu.cache.csr_cache_10_addr = uint(idx_uint4(STATE_TEX[uint2(5, 0)], 0)); + cpu.cache.csr_cache_10_val = uint(idx_uint4(STATE_TEX[uint2(5, 0)], 1)); + cpu.cache.csr_cache_11_addr = uint(idx_uint4(STATE_TEX[uint2(5, 0)], 2)); + cpu.cache.csr_cache_11_val = uint(idx_uint4(STATE_TEX[uint2(5, 0)], 3)); + cpu.cache.csr_cache_12_addr = uint(idx_uint4(STATE_TEX[uint2(6, 0)], 0)); + cpu.cache.csr_cache_12_val = uint(idx_uint4(STATE_TEX[uint2(6, 0)], 1)); + cpu.cache.csr_cache_13_addr = uint(idx_uint4(STATE_TEX[uint2(6, 0)], 2)); + cpu.cache.csr_cache_13_val = uint(idx_uint4(STATE_TEX[uint2(6, 0)], 3)); + cpu.cache.csr_cache_14_addr = uint(idx_uint4(STATE_TEX[uint2(7, 0)], 0)); + cpu.cache.csr_cache_14_val = uint(idx_uint4(STATE_TEX[uint2(7, 0)], 1)); + cpu.cache.csr_cache_15_addr = uint(idx_uint4(STATE_TEX[uint2(7, 0)], 2)); + cpu.cache.csr_cache_15_val = uint(idx_uint4(STATE_TEX[uint2(7, 0)], 3)); + cpu.cache.ram_l1_0_addr = uint(idx_uint4(STATE_TEX[uint2(8, 0)], 0)); + cpu.cache.ram_l1_0_val = uint(idx_uint4(STATE_TEX[uint2(8, 0)], 1)); + cpu.cache.ram_l1_16_addr = uint(idx_uint4(STATE_TEX[uint2(8, 0)], 2)); + cpu.cache.ram_l1_16_val = uint(idx_uint4(STATE_TEX[uint2(8, 0)], 3)); + cpu.cache.ram_l1_32_addr = uint(idx_uint4(STATE_TEX[uint2(9, 0)], 0)); + cpu.cache.ram_l1_32_val = uint(idx_uint4(STATE_TEX[uint2(9, 0)], 1)); + cpu.cache.ram_l1_48_addr = uint(idx_uint4(STATE_TEX[uint2(9, 0)], 2)); + cpu.cache.ram_l1_48_val = uint(idx_uint4(STATE_TEX[uint2(9, 0)], 3)); + cpu.cache.ram_l1_64_addr = uint(idx_uint4(STATE_TEX[uint2(10, 0)], 0)); + cpu.cache.ram_l1_64_val = uint(idx_uint4(STATE_TEX[uint2(10, 0)], 1)); + cpu.cache.ram_l1_1_addr = uint(idx_uint4(STATE_TEX[uint2(10, 0)], 2)); + cpu.cache.ram_l1_1_val = uint(idx_uint4(STATE_TEX[uint2(10, 0)], 3)); + cpu.cache.ram_l1_17_addr = uint(idx_uint4(STATE_TEX[uint2(11, 0)], 0)); + cpu.cache.ram_l1_17_val = uint(idx_uint4(STATE_TEX[uint2(11, 0)], 1)); + cpu.cache.ram_l1_33_addr = uint(idx_uint4(STATE_TEX[uint2(11, 0)], 2)); + cpu.cache.ram_l1_33_val = uint(idx_uint4(STATE_TEX[uint2(11, 0)], 3)); + cpu.cache.ram_l1_49_addr = uint(idx_uint4(STATE_TEX[uint2(12, 0)], 0)); + cpu.cache.ram_l1_49_val = uint(idx_uint4(STATE_TEX[uint2(12, 0)], 1)); + cpu.cache.ram_l1_65_addr = uint(idx_uint4(STATE_TEX[uint2(12, 0)], 2)); + cpu.cache.ram_l1_65_val = uint(idx_uint4(STATE_TEX[uint2(12, 0)], 3)); + cpu.cache.ram_l1_2_addr = uint(idx_uint4(STATE_TEX[uint2(13, 0)], 0)); + cpu.cache.ram_l1_2_val = uint(idx_uint4(STATE_TEX[uint2(13, 0)], 1)); + cpu.cache.ram_l1_18_addr = uint(idx_uint4(STATE_TEX[uint2(13, 0)], 2)); + cpu.cache.ram_l1_18_val = uint(idx_uint4(STATE_TEX[uint2(13, 0)], 3)); + cpu.cache.ram_l1_34_addr = uint(idx_uint4(STATE_TEX[uint2(14, 0)], 0)); + cpu.cache.ram_l1_34_val = uint(idx_uint4(STATE_TEX[uint2(14, 0)], 1)); + cpu.cache.ram_l1_50_addr = uint(idx_uint4(STATE_TEX[uint2(14, 0)], 2)); + cpu.cache.ram_l1_50_val = uint(idx_uint4(STATE_TEX[uint2(14, 0)], 3)); + cpu.cache.ram_l1_66_addr = uint(idx_uint4(STATE_TEX[uint2(15, 0)], 0)); + cpu.cache.ram_l1_66_val = uint(idx_uint4(STATE_TEX[uint2(15, 0)], 1)); + cpu.cache.ram_l1_3_addr = uint(idx_uint4(STATE_TEX[uint2(15, 0)], 2)); + cpu.cache.ram_l1_3_val = uint(idx_uint4(STATE_TEX[uint2(15, 0)], 3)); + cpu.cache.ram_l1_19_addr = uint(idx_uint4(STATE_TEX[uint2(16, 0)], 0)); + cpu.cache.ram_l1_19_val = uint(idx_uint4(STATE_TEX[uint2(16, 0)], 1)); + cpu.cache.ram_l1_35_addr = uint(idx_uint4(STATE_TEX[uint2(16, 0)], 2)); + cpu.cache.ram_l1_35_val = uint(idx_uint4(STATE_TEX[uint2(16, 0)], 3)); + cpu.cache.ram_l1_51_addr = uint(idx_uint4(STATE_TEX[uint2(17, 0)], 0)); + cpu.cache.ram_l1_51_val = uint(idx_uint4(STATE_TEX[uint2(17, 0)], 1)); + cpu.cache.ram_l1_67_addr = uint(idx_uint4(STATE_TEX[uint2(17, 0)], 2)); + cpu.cache.ram_l1_67_val = uint(idx_uint4(STATE_TEX[uint2(17, 0)], 3)); + cpu.cache.ram_l1_4_addr = uint(idx_uint4(STATE_TEX[uint2(18, 0)], 0)); + cpu.cache.ram_l1_4_val = uint(idx_uint4(STATE_TEX[uint2(18, 0)], 1)); + cpu.cache.ram_l1_20_addr = uint(idx_uint4(STATE_TEX[uint2(18, 0)], 2)); + cpu.cache.ram_l1_20_val = uint(idx_uint4(STATE_TEX[uint2(18, 0)], 3)); + cpu.cache.ram_l1_36_addr = uint(idx_uint4(STATE_TEX[uint2(19, 0)], 0)); + cpu.cache.ram_l1_36_val = uint(idx_uint4(STATE_TEX[uint2(19, 0)], 1)); + cpu.cache.ram_l1_52_addr = uint(idx_uint4(STATE_TEX[uint2(19, 0)], 2)); + cpu.cache.ram_l1_52_val = uint(idx_uint4(STATE_TEX[uint2(19, 0)], 3)); + cpu.cache.ram_l1_68_addr = uint(idx_uint4(STATE_TEX[uint2(20, 0)], 0)); + cpu.cache.ram_l1_68_val = uint(idx_uint4(STATE_TEX[uint2(20, 0)], 1)); + cpu.cache.ram_l1_5_addr = uint(idx_uint4(STATE_TEX[uint2(20, 0)], 2)); + cpu.cache.ram_l1_5_val = uint(idx_uint4(STATE_TEX[uint2(20, 0)], 3)); + cpu.cache.ram_l1_21_addr = uint(idx_uint4(STATE_TEX[uint2(21, 0)], 0)); + cpu.cache.ram_l1_21_val = uint(idx_uint4(STATE_TEX[uint2(21, 0)], 1)); + cpu.cache.ram_l1_37_addr = uint(idx_uint4(STATE_TEX[uint2(21, 0)], 2)); + cpu.cache.ram_l1_37_val = uint(idx_uint4(STATE_TEX[uint2(21, 0)], 3)); + cpu.cache.ram_l1_53_addr = uint(idx_uint4(STATE_TEX[uint2(22, 0)], 0)); + cpu.cache.ram_l1_53_val = uint(idx_uint4(STATE_TEX[uint2(22, 0)], 1)); + cpu.cache.ram_l1_69_addr = uint(idx_uint4(STATE_TEX[uint2(22, 0)], 2)); + cpu.cache.ram_l1_69_val = uint(idx_uint4(STATE_TEX[uint2(22, 0)], 3)); + cpu.cache.ram_l1_6_addr = uint(idx_uint4(STATE_TEX[uint2(23, 0)], 0)); + cpu.cache.ram_l1_6_val = uint(idx_uint4(STATE_TEX[uint2(23, 0)], 1)); + cpu.cache.ram_l1_22_addr = uint(idx_uint4(STATE_TEX[uint2(23, 0)], 2)); + cpu.cache.ram_l1_22_val = uint(idx_uint4(STATE_TEX[uint2(23, 0)], 3)); + cpu.cache.ram_l1_38_addr = uint(idx_uint4(STATE_TEX[uint2(24, 0)], 0)); + cpu.cache.ram_l1_38_val = uint(idx_uint4(STATE_TEX[uint2(24, 0)], 1)); + cpu.cache.ram_l1_54_addr = uint(idx_uint4(STATE_TEX[uint2(24, 0)], 2)); + cpu.cache.ram_l1_54_val = uint(idx_uint4(STATE_TEX[uint2(24, 0)], 3)); + cpu.cache.ram_l1_70_addr = uint(idx_uint4(STATE_TEX[uint2(25, 0)], 0)); + cpu.cache.ram_l1_70_val = uint(idx_uint4(STATE_TEX[uint2(25, 0)], 1)); + cpu.cache.ram_l1_7_addr = uint(idx_uint4(STATE_TEX[uint2(25, 0)], 2)); + cpu.cache.ram_l1_7_val = uint(idx_uint4(STATE_TEX[uint2(25, 0)], 3)); + cpu.cache.ram_l1_23_addr = uint(idx_uint4(STATE_TEX[uint2(26, 0)], 0)); + cpu.cache.ram_l1_23_val = uint(idx_uint4(STATE_TEX[uint2(26, 0)], 1)); + cpu.cache.ram_l1_39_addr = uint(idx_uint4(STATE_TEX[uint2(26, 0)], 2)); + cpu.cache.ram_l1_39_val = uint(idx_uint4(STATE_TEX[uint2(26, 0)], 3)); + cpu.cache.ram_l1_55_addr = uint(idx_uint4(STATE_TEX[uint2(27, 0)], 0)); + cpu.cache.ram_l1_55_val = uint(idx_uint4(STATE_TEX[uint2(27, 0)], 1)); + cpu.cache.ram_l1_71_addr = uint(idx_uint4(STATE_TEX[uint2(27, 0)], 2)); + cpu.cache.ram_l1_71_val = uint(idx_uint4(STATE_TEX[uint2(27, 0)], 3)); + cpu.cache.ram_l1_8_addr = uint(idx_uint4(STATE_TEX[uint2(28, 0)], 0)); + cpu.cache.ram_l1_8_val = uint(idx_uint4(STATE_TEX[uint2(28, 0)], 1)); + cpu.cache.ram_l1_24_addr = uint(idx_uint4(STATE_TEX[uint2(28, 0)], 2)); + cpu.cache.ram_l1_24_val = uint(idx_uint4(STATE_TEX[uint2(28, 0)], 3)); + cpu.cache.ram_l1_40_addr = uint(idx_uint4(STATE_TEX[uint2(29, 0)], 0)); + cpu.cache.ram_l1_40_val = uint(idx_uint4(STATE_TEX[uint2(29, 0)], 1)); + cpu.cache.ram_l1_56_addr = uint(idx_uint4(STATE_TEX[uint2(29, 0)], 2)); + cpu.cache.ram_l1_56_val = uint(idx_uint4(STATE_TEX[uint2(29, 0)], 3)); + cpu.cache.ram_l1_72_addr = uint(idx_uint4(STATE_TEX[uint2(30, 0)], 0)); + cpu.cache.ram_l1_72_val = uint(idx_uint4(STATE_TEX[uint2(30, 0)], 1)); + cpu.cache.ram_l1_9_addr = uint(idx_uint4(STATE_TEX[uint2(30, 0)], 2)); + cpu.cache.ram_l1_9_val = uint(idx_uint4(STATE_TEX[uint2(30, 0)], 3)); + cpu.cache.ram_l1_25_addr = uint(idx_uint4(STATE_TEX[uint2(31, 0)], 0)); + cpu.cache.ram_l1_25_val = uint(idx_uint4(STATE_TEX[uint2(31, 0)], 1)); + cpu.cache.ram_l1_41_addr = uint(idx_uint4(STATE_TEX[uint2(31, 0)], 2)); + cpu.cache.ram_l1_41_val = uint(idx_uint4(STATE_TEX[uint2(31, 0)], 3)); + cpu.cache.ram_l1_57_addr = uint(idx_uint4(STATE_TEX[uint2(32, 0)], 0)); + cpu.cache.ram_l1_57_val = uint(idx_uint4(STATE_TEX[uint2(32, 0)], 1)); + cpu.cache.ram_l1_73_addr = uint(idx_uint4(STATE_TEX[uint2(32, 0)], 2)); + cpu.cache.ram_l1_73_val = uint(idx_uint4(STATE_TEX[uint2(32, 0)], 3)); + cpu.cache.ram_l1_10_addr = uint(idx_uint4(STATE_TEX[uint2(33, 0)], 0)); + cpu.cache.ram_l1_10_val = uint(idx_uint4(STATE_TEX[uint2(33, 0)], 1)); + cpu.cache.ram_l1_26_addr = uint(idx_uint4(STATE_TEX[uint2(33, 0)], 2)); + cpu.cache.ram_l1_26_val = uint(idx_uint4(STATE_TEX[uint2(33, 0)], 3)); + cpu.cache.ram_l1_42_addr = uint(idx_uint4(STATE_TEX[uint2(34, 0)], 0)); + cpu.cache.ram_l1_42_val = uint(idx_uint4(STATE_TEX[uint2(34, 0)], 1)); + cpu.cache.ram_l1_58_addr = uint(idx_uint4(STATE_TEX[uint2(34, 0)], 2)); + cpu.cache.ram_l1_58_val = uint(idx_uint4(STATE_TEX[uint2(34, 0)], 3)); + cpu.cache.ram_l1_74_addr = uint(idx_uint4(STATE_TEX[uint2(35, 0)], 0)); + cpu.cache.ram_l1_74_val = uint(idx_uint4(STATE_TEX[uint2(35, 0)], 1)); + cpu.cache.ram_l1_11_addr = uint(idx_uint4(STATE_TEX[uint2(35, 0)], 2)); + cpu.cache.ram_l1_11_val = uint(idx_uint4(STATE_TEX[uint2(35, 0)], 3)); + cpu.cache.ram_l1_27_addr = uint(idx_uint4(STATE_TEX[uint2(36, 0)], 0)); + cpu.cache.ram_l1_27_val = uint(idx_uint4(STATE_TEX[uint2(36, 0)], 1)); + cpu.cache.ram_l1_43_addr = uint(idx_uint4(STATE_TEX[uint2(36, 0)], 2)); + cpu.cache.ram_l1_43_val = uint(idx_uint4(STATE_TEX[uint2(36, 0)], 3)); + cpu.cache.ram_l1_59_addr = uint(idx_uint4(STATE_TEX[uint2(37, 0)], 0)); + cpu.cache.ram_l1_59_val = uint(idx_uint4(STATE_TEX[uint2(37, 0)], 1)); + cpu.cache.ram_l1_75_addr = uint(idx_uint4(STATE_TEX[uint2(37, 0)], 2)); + cpu.cache.ram_l1_75_val = uint(idx_uint4(STATE_TEX[uint2(37, 0)], 3)); + cpu.cache.ram_l1_12_addr = uint(idx_uint4(STATE_TEX[uint2(38, 0)], 0)); + cpu.cache.ram_l1_12_val = uint(idx_uint4(STATE_TEX[uint2(38, 0)], 1)); + cpu.cache.ram_l1_28_addr = uint(idx_uint4(STATE_TEX[uint2(38, 0)], 2)); + cpu.cache.ram_l1_28_val = uint(idx_uint4(STATE_TEX[uint2(38, 0)], 3)); + cpu.cache.ram_l1_44_addr = uint(idx_uint4(STATE_TEX[uint2(39, 0)], 0)); + cpu.cache.ram_l1_44_val = uint(idx_uint4(STATE_TEX[uint2(39, 0)], 1)); + cpu.cache.ram_l1_60_addr = uint(idx_uint4(STATE_TEX[uint2(39, 0)], 2)); + cpu.cache.ram_l1_60_val = uint(idx_uint4(STATE_TEX[uint2(39, 0)], 3)); + cpu.cache.ram_l1_76_addr = uint(idx_uint4(STATE_TEX[uint2(40, 0)], 0)); + cpu.cache.ram_l1_76_val = uint(idx_uint4(STATE_TEX[uint2(40, 0)], 1)); + cpu.cache.ram_l1_13_addr = uint(idx_uint4(STATE_TEX[uint2(40, 0)], 2)); + cpu.cache.ram_l1_13_val = uint(idx_uint4(STATE_TEX[uint2(40, 0)], 3)); + cpu.cache.ram_l1_29_addr = uint(idx_uint4(STATE_TEX[uint2(41, 0)], 0)); + cpu.cache.ram_l1_29_val = uint(idx_uint4(STATE_TEX[uint2(41, 0)], 1)); + cpu.cache.ram_l1_45_addr = uint(idx_uint4(STATE_TEX[uint2(41, 0)], 2)); + cpu.cache.ram_l1_45_val = uint(idx_uint4(STATE_TEX[uint2(41, 0)], 3)); + cpu.cache.ram_l1_61_addr = uint(idx_uint4(STATE_TEX[uint2(42, 0)], 0)); + cpu.cache.ram_l1_61_val = uint(idx_uint4(STATE_TEX[uint2(42, 0)], 1)); + cpu.cache.ram_l1_77_addr = uint(idx_uint4(STATE_TEX[uint2(42, 0)], 2)); + cpu.cache.ram_l1_77_val = uint(idx_uint4(STATE_TEX[uint2(42, 0)], 3)); + cpu.cache.ram_l1_14_addr = uint(idx_uint4(STATE_TEX[uint2(43, 0)], 0)); + cpu.cache.ram_l1_14_val = uint(idx_uint4(STATE_TEX[uint2(43, 0)], 1)); + cpu.cache.ram_l1_30_addr = uint(idx_uint4(STATE_TEX[uint2(43, 0)], 2)); + cpu.cache.ram_l1_30_val = uint(idx_uint4(STATE_TEX[uint2(43, 0)], 3)); + cpu.cache.ram_l1_46_addr = uint(idx_uint4(STATE_TEX[uint2(44, 0)], 0)); + cpu.cache.ram_l1_46_val = uint(idx_uint4(STATE_TEX[uint2(44, 0)], 1)); + cpu.cache.ram_l1_62_addr = uint(idx_uint4(STATE_TEX[uint2(44, 0)], 2)); + cpu.cache.ram_l1_62_val = uint(idx_uint4(STATE_TEX[uint2(44, 0)], 3)); + cpu.cache.ram_l1_78_addr = uint(idx_uint4(STATE_TEX[uint2(45, 0)], 0)); + cpu.cache.ram_l1_78_val = uint(idx_uint4(STATE_TEX[uint2(45, 0)], 1)); + cpu.cache.ram_l1_15_addr = uint(idx_uint4(STATE_TEX[uint2(45, 0)], 2)); + cpu.cache.ram_l1_15_val = uint(idx_uint4(STATE_TEX[uint2(45, 0)], 3)); + cpu.cache.ram_l1_31_addr = uint(idx_uint4(STATE_TEX[uint2(46, 0)], 0)); + cpu.cache.ram_l1_31_val = uint(idx_uint4(STATE_TEX[uint2(46, 0)], 1)); + cpu.cache.ram_l1_47_addr = uint(idx_uint4(STATE_TEX[uint2(46, 0)], 2)); + cpu.cache.ram_l1_47_val = uint(idx_uint4(STATE_TEX[uint2(46, 0)], 3)); + cpu.cache.ram_l1_63_addr = uint(idx_uint4(STATE_TEX[uint2(47, 0)], 0)); + cpu.cache.ram_l1_63_val = uint(idx_uint4(STATE_TEX[uint2(47, 0)], 1)); + cpu.cache.ram_l1_79_addr = uint(idx_uint4(STATE_TEX[uint2(47, 0)], 2)); + cpu.cache.ram_l1_79_val = uint(idx_uint4(STATE_TEX[uint2(47, 0)], 3)); + cpu.cache.ram_l1_last_addr = uint(idx_uint4(STATE_TEX[uint2(48, 0)], 0)); + cpu.cache.ram_l1_last_val = uint(idx_uint4(STATE_TEX[uint2(48, 0)], 1)); + cpu.csr.privilege = uint(idx_uint4(STATE_TEX[uint2(48, 0)], 2)); + cpu.uart.rbr_thr_ier_iir = uint(idx_uint4(STATE_TEX[uint2(48, 0)], 3)); + cpu.uart.lcr_mcr_lsr_scr = uint(idx_uint4(STATE_TEX[uint2(49, 0)], 0)); + cpu.uart.thre_ip = bool(idx_uint4(STATE_TEX[uint2(49, 0)], 1)); + cpu.uart.interrupting = bool(idx_uint4(STATE_TEX[uint2(49, 0)], 2)); + cpu.uart.input_tag = uint(idx_uint4(STATE_TEX[uint2(49, 0)], 3)); + cpu.clint.msip = bool(idx_uint4(STATE_TEX[uint2(50, 0)], 0)); + cpu.clint.mtimecmp_lo = uint(idx_uint4(STATE_TEX[uint2(50, 0)], 1)); + cpu.clint.mtimecmp_hi = uint(idx_uint4(STATE_TEX[uint2(50, 0)], 2)); + cpu.clint.mtime_lo = uint(idx_uint4(STATE_TEX[uint2(50, 0)], 3)); + cpu.clint.mtime_hi = uint(idx_uint4(STATE_TEX[uint2(51, 0)], 0)); + cpu.uart_buffer.ptr = uint(idx_uint4(STATE_TEX[uint2(51, 0)], 1)); + cpu.uart_buffer.buf0 = uint(idx_uint4(STATE_TEX[uint2(51, 0)], 2)); + cpu.uart_buffer.buf1 = uint(idx_uint4(STATE_TEX[uint2(51, 0)], 3)); + cpu.uart_buffer.buf2 = uint(idx_uint4(STATE_TEX[uint2(52, 0)], 0)); + cpu.uart_buffer.buf3 = uint(idx_uint4(STATE_TEX[uint2(52, 0)], 1)); + cpu.uart_buffer.buf4 = uint(idx_uint4(STATE_TEX[uint2(52, 0)], 2)); + cpu.uart_buffer.buf5 = uint(idx_uint4(STATE_TEX[uint2(52, 0)], 3)); + cpu.uart_buffer.buf6 = uint(idx_uint4(STATE_TEX[uint2(53, 0)], 0)); + cpu.uart_buffer.buf7 = uint(idx_uint4(STATE_TEX[uint2(53, 0)], 1)); + cpu.uart_buffer.buf8 = uint(idx_uint4(STATE_TEX[uint2(53, 0)], 2)); + cpu.uart_buffer.buf9 = uint(idx_uint4(STATE_TEX[uint2(53, 0)], 3)); + cpu.uart_buffer.buf10 = uint(idx_uint4(STATE_TEX[uint2(54, 0)], 0)); + cpu.uart_buffer.buf11 = uint(idx_uint4(STATE_TEX[uint2(54, 0)], 1)); + cpu.uart_buffer.buf12 = uint(idx_uint4(STATE_TEX[uint2(54, 0)], 2)); + cpu.uart_buffer.buf13 = uint(idx_uint4(STATE_TEX[uint2(54, 0)], 3)); + cpu.uart_buffer.buf14 = uint(idx_uint4(STATE_TEX[uint2(55, 0)], 0)); + cpu.uart_buffer.buf15 = uint(idx_uint4(STATE_TEX[uint2(55, 0)], 1)); + cpu.uart_buffer.buf16 = uint(idx_uint4(STATE_TEX[uint2(55, 0)], 2)); + cpu.uart_buffer.buf17 = uint(idx_uint4(STATE_TEX[uint2(55, 0)], 3)); + cpu.uart_buffer.buf18 = uint(idx_uint4(STATE_TEX[uint2(56, 0)], 0)); + cpu.uart_buffer.buf19 = uint(idx_uint4(STATE_TEX[uint2(56, 0)], 1)); + cpu.uart_buffer.buf20 = uint(idx_uint4(STATE_TEX[uint2(56, 0)], 2)); + cpu.uart_buffer.buf21 = uint(idx_uint4(STATE_TEX[uint2(56, 0)], 3)); + cpu.uart_buffer.buf22 = uint(idx_uint4(STATE_TEX[uint2(57, 0)], 0)); + cpu.uart_buffer.buf23 = uint(idx_uint4(STATE_TEX[uint2(57, 0)], 1)); + cpu.uart_buffer.buf24 = uint(idx_uint4(STATE_TEX[uint2(57, 0)], 2)); + cpu.uart_buffer.buf25 = uint(idx_uint4(STATE_TEX[uint2(57, 0)], 3)); + cpu.uart_buffer.buf26 = uint(idx_uint4(STATE_TEX[uint2(58, 0)], 0)); + cpu.uart_buffer.buf27 = uint(idx_uint4(STATE_TEX[uint2(58, 0)], 1)); + cpu.uart_buffer.buf28 = uint(idx_uint4(STATE_TEX[uint2(58, 0)], 2)); + cpu.uart_buffer.buf29 = uint(idx_uint4(STATE_TEX[uint2(58, 0)], 3)); + cpu.uart_buffer.buf30 = uint(idx_uint4(STATE_TEX[uint2(59, 0)], 0)); + cpu.uart_buffer.buf31 = uint(idx_uint4(STATE_TEX[uint2(59, 0)], 1)); + cpu.uart_buffer.buf32 = uint(idx_uint4(STATE_TEX[uint2(59, 0)], 2)); + cpu.uart_buffer.buf33 = uint(idx_uint4(STATE_TEX[uint2(59, 0)], 3)); + cpu.uart_buffer.buf34 = uint(idx_uint4(STATE_TEX[uint2(60, 0)], 0)); + cpu.uart_buffer.buf35 = uint(idx_uint4(STATE_TEX[uint2(60, 0)], 1)); + cpu.uart_buffer.buf36 = uint(idx_uint4(STATE_TEX[uint2(60, 0)], 2)); + cpu.uart_buffer.buf37 = uint(idx_uint4(STATE_TEX[uint2(60, 0)], 3)); + cpu.uart_buffer.buf38 = uint(idx_uint4(STATE_TEX[uint2(61, 0)], 0)); + cpu.uart_buffer.buf39 = uint(idx_uint4(STATE_TEX[uint2(61, 0)], 1)); + cpu.uart_buffer.buf40 = uint(idx_uint4(STATE_TEX[uint2(61, 0)], 2)); + cpu.uart_buffer.buf41 = uint(idx_uint4(STATE_TEX[uint2(61, 0)], 3)); + cpu.uart_buffer.buf42 = uint(idx_uint4(STATE_TEX[uint2(62, 0)], 0)); + cpu.uart_buffer.buf43 = uint(idx_uint4(STATE_TEX[uint2(62, 0)], 1)); + cpu.uart_buffer.buf44 = uint(idx_uint4(STATE_TEX[uint2(62, 0)], 2)); + cpu.uart_buffer.buf45 = uint(idx_uint4(STATE_TEX[uint2(62, 0)], 3)); + cpu.uart_buffer.buf46 = uint(idx_uint4(STATE_TEX[uint2(63, 0)], 0)); + cpu.uart_buffer.buf47 = uint(idx_uint4(STATE_TEX[uint2(63, 0)], 1)); + cpu.uart_buffer.buf48 = uint(idx_uint4(STATE_TEX[uint2(63, 0)], 2)); + cpu.uart_buffer.buf49 = uint(idx_uint4(STATE_TEX[uint2(63, 0)], 3)); + cpu.uart_buffer.buf50 = uint(idx_uint4(STATE_TEX[uint2(64, 0)], 0)); + cpu.uart_buffer.buf51 = uint(idx_uint4(STATE_TEX[uint2(64, 0)], 1)); + cpu.uart_buffer.buf52 = uint(idx_uint4(STATE_TEX[uint2(64, 0)], 2)); + cpu.uart_buffer.buf53 = uint(idx_uint4(STATE_TEX[uint2(64, 0)], 3)); + cpu.uart_buffer.buf54 = uint(idx_uint4(STATE_TEX[uint2(65, 0)], 0)); + cpu.uart_buffer.buf55 = uint(idx_uint4(STATE_TEX[uint2(65, 0)], 1)); + cpu.uart_buffer.buf56 = uint(idx_uint4(STATE_TEX[uint2(65, 0)], 2)); + cpu.uart_buffer.buf57 = uint(idx_uint4(STATE_TEX[uint2(65, 0)], 3)); + cpu.uart_buffer.buf58 = uint(idx_uint4(STATE_TEX[uint2(66, 0)], 0)); + cpu.uart_buffer.buf59 = uint(idx_uint4(STATE_TEX[uint2(66, 0)], 1)); + cpu.uart_buffer.buf60 = uint(idx_uint4(STATE_TEX[uint2(66, 0)], 2)); + cpu.uart_buffer.buf61 = uint(idx_uint4(STATE_TEX[uint2(66, 0)], 3)); + cpu.uart_buffer.buf62 = uint(idx_uint4(STATE_TEX[uint2(67, 0)], 0)); + cpu.uart_buffer.buf63 = uint(idx_uint4(STATE_TEX[uint2(67, 0)], 1)); + cpu.mmu.mode = uint(idx_uint4(STATE_TEX[uint2(67, 0)], 2)); + cpu.mmu.ppn = uint(idx_uint4(STATE_TEX[uint2(67, 0)], 3)); + cpu.stall = uint(idx_uint4(STATE_TEX[uint2(68, 0)], 0)); + cpu.clock = uint(idx_uint4(STATE_TEX[uint2(68, 0)], 1)); + cpu.commits = uint(idx_uint4(STATE_TEX[uint2(68, 0)], 2)); + cpu.xreg0 = uint(idx_uint4(STATE_TEX[uint2(68, 0)], 3)); + cpu.xreg1 = uint(idx_uint4(STATE_TEX[uint2(69, 0)], 0)); + cpu.xreg2 = uint(idx_uint4(STATE_TEX[uint2(69, 0)], 1)); + cpu.xreg3 = uint(idx_uint4(STATE_TEX[uint2(69, 0)], 2)); + cpu.xreg4 = uint(idx_uint4(STATE_TEX[uint2(69, 0)], 3)); + cpu.xreg5 = uint(idx_uint4(STATE_TEX[uint2(70, 0)], 0)); + cpu.xreg6 = uint(idx_uint4(STATE_TEX[uint2(70, 0)], 1)); + cpu.xreg7 = uint(idx_uint4(STATE_TEX[uint2(70, 0)], 2)); + cpu.xreg8 = uint(idx_uint4(STATE_TEX[uint2(70, 0)], 3)); + cpu.xreg9 = uint(idx_uint4(STATE_TEX[uint2(71, 0)], 0)); + cpu.xreg10 = uint(idx_uint4(STATE_TEX[uint2(71, 0)], 1)); + cpu.xreg11 = uint(idx_uint4(STATE_TEX[uint2(71, 0)], 2)); + cpu.xreg12 = uint(idx_uint4(STATE_TEX[uint2(71, 0)], 3)); + cpu.xreg13 = uint(idx_uint4(STATE_TEX[uint2(72, 0)], 0)); + cpu.xreg14 = uint(idx_uint4(STATE_TEX[uint2(72, 0)], 1)); + cpu.xreg15 = uint(idx_uint4(STATE_TEX[uint2(72, 0)], 2)); + cpu.xreg16 = uint(idx_uint4(STATE_TEX[uint2(72, 0)], 3)); + cpu.xreg17 = uint(idx_uint4(STATE_TEX[uint2(73, 0)], 0)); + cpu.xreg18 = uint(idx_uint4(STATE_TEX[uint2(73, 0)], 1)); + cpu.xreg19 = uint(idx_uint4(STATE_TEX[uint2(73, 0)], 2)); + cpu.xreg20 = uint(idx_uint4(STATE_TEX[uint2(73, 0)], 3)); + cpu.xreg21 = uint(idx_uint4(STATE_TEX[uint2(74, 0)], 0)); + cpu.xreg22 = uint(idx_uint4(STATE_TEX[uint2(74, 0)], 1)); + cpu.xreg23 = uint(idx_uint4(STATE_TEX[uint2(74, 0)], 2)); + cpu.xreg24 = uint(idx_uint4(STATE_TEX[uint2(74, 0)], 3)); + cpu.xreg25 = uint(idx_uint4(STATE_TEX[uint2(75, 0)], 0)); + cpu.xreg26 = uint(idx_uint4(STATE_TEX[uint2(75, 0)], 1)); + cpu.xreg27 = uint(idx_uint4(STATE_TEX[uint2(75, 0)], 2)); + cpu.xreg28 = uint(idx_uint4(STATE_TEX[uint2(75, 0)], 3)); + cpu.xreg29 = uint(idx_uint4(STATE_TEX[uint2(76, 0)], 0)); + cpu.xreg30 = uint(idx_uint4(STATE_TEX[uint2(76, 0)], 1)); + cpu.xreg31 = uint(idx_uint4(STATE_TEX[uint2(76, 0)], 2)); + cpu.pc = uint(idx_uint4(STATE_TEX[uint2(76, 0)], 3)); + cpu.reservation_en = bool(idx_uint4(STATE_TEX[uint2(77, 0)], 0)); + cpu.reservation_addr = uint(idx_uint4(STATE_TEX[uint2(77, 0)], 1)); + cpu.memop_src_v = uint(idx_uint4(STATE_TEX[uint2(77, 0)], 2)); + cpu.memop_dst_v = uint(idx_uint4(STATE_TEX[uint2(77, 0)], 3)); + cpu.memop_src_p = uint(idx_uint4(STATE_TEX[uint2(78, 0)], 0)); + cpu.memop_dst_p = uint(idx_uint4(STATE_TEX[uint2(78, 0)], 1)); + cpu.memop_n = uint(idx_uint4(STATE_TEX[uint2(78, 0)], 2)); + cpu.stall_count = uint(idx_uint4(STATE_TEX[uint2(78, 0)], 3)); + cpu.trap_count = uint(idx_uint4(STATE_TEX[uint2(79, 0)], 0)); + cpu.debug_do_tick = uint(idx_uint4(STATE_TEX[uint2(79, 0)], 1)); + cpu.debug_last_ins = uint(idx_uint4(STATE_TEX[uint2(79, 0)], 2)); + cpu.debug_last_stall = uint(idx_uint4(STATE_TEX[uint2(79, 0)], 3)); + cpu.debug_arb_0 = uint(idx_uint4(STATE_TEX[uint2(80, 0)], 0)); + +} +#endif + +bool pixel_has_state(uint2 pos) { + + return pos.y < 0 || (pos.y == 0 && pos.x <= 80); +} + + + +/* void set_debug_arb() { */ +/* */ +/* cpu.debug_arb_0 = cpu.xreg0 ^ */ +/* cpu.xreg1 ^ */ +/* cpu.xreg2 ^ */ +/* cpu.xreg3; */ +/* */ +/* cpu.debug_arb_1 = cpu.xreg4 ^ */ +/* cpu.xreg5 ^ */ +/* cpu.xreg6 ^ */ +/* cpu.xreg7; */ +/* */ +/* cpu.debug_arb_2 = cpu.xreg8 ^ */ +/* cpu.xreg9 ^ */ +/* cpu.xreg10 ^ */ +/* cpu.xreg11; */ +/* */ +/* cpu.debug_arb_3 = cpu.xreg12 ^ */ +/* cpu.xreg13 ^ */ +/* cpu.xreg14 ^ */ +/* cpu.xreg15; */ +/* */ +/* cpu.debug_arb_4 = cpu.xreg16 ^ */ +/* cpu.xreg17 ^ */ +/* cpu.xreg18 ^ */ +/* cpu.xreg19; */ +/* */ +/* cpu.debug_arb_5 = cpu.xreg20 ^ */ +/* cpu.xreg21 ^ */ +/* cpu.xreg22 ^ */ +/* cpu.xreg23; */ +/* */ +/* cpu.debug_arb_6 = cpu.xreg24 ^ */ +/* cpu.xreg25 ^ */ +/* cpu.xreg26 ^ */ +/* cpu.xreg27; */ +/* */ +/* cpu.debug_arb_7 = cpu.xreg28 ^ */ +/* cpu.xreg29 ^ */ +/* cpu.xreg30 ^ */ +/* cpu.xreg31; */ +/* */ +/* } */ + +uint4 encode(uint2 pos) { + // fallback is passthrough + uint4 ret = STATE_TEX[pos]; + + uint pos_id = pos.x | (pos.y << 16); + + switch (pos_id) { + case 0: + ret.r = uint(cpu.cache.csr_cache_0_addr); + ret.g = uint(cpu.cache.csr_cache_0_val); + ret.b = uint(cpu.cache.csr_cache_1_addr); + ret.a = uint(cpu.cache.csr_cache_1_val); + return ret; + case 1: + ret.r = uint(cpu.cache.csr_cache_2_addr); + ret.g = uint(cpu.cache.csr_cache_2_val); + ret.b = uint(cpu.cache.csr_cache_3_addr); + ret.a = uint(cpu.cache.csr_cache_3_val); + return ret; + case 10: + ret.b = uint(cpu.cache.ram_l1_1_addr); + ret.a = uint(cpu.cache.ram_l1_1_val); + ret.r = uint(cpu.cache.ram_l1_64_addr); + ret.g = uint(cpu.cache.ram_l1_64_val); + return ret; + case 11: + ret.r = uint(cpu.cache.ram_l1_17_addr); + ret.g = uint(cpu.cache.ram_l1_17_val); + ret.b = uint(cpu.cache.ram_l1_33_addr); + ret.a = uint(cpu.cache.ram_l1_33_val); + return ret; + case 12: + ret.r = uint(cpu.cache.ram_l1_49_addr); + ret.g = uint(cpu.cache.ram_l1_49_val); + ret.b = uint(cpu.cache.ram_l1_65_addr); + ret.a = uint(cpu.cache.ram_l1_65_val); + return ret; + case 13: + ret.b = uint(cpu.cache.ram_l1_18_addr); + ret.a = uint(cpu.cache.ram_l1_18_val); + ret.r = uint(cpu.cache.ram_l1_2_addr); + ret.g = uint(cpu.cache.ram_l1_2_val); + return ret; + case 14: + ret.r = uint(cpu.cache.ram_l1_34_addr); + ret.g = uint(cpu.cache.ram_l1_34_val); + ret.b = uint(cpu.cache.ram_l1_50_addr); + ret.a = uint(cpu.cache.ram_l1_50_val); + return ret; + case 15: + ret.b = uint(cpu.cache.ram_l1_3_addr); + ret.a = uint(cpu.cache.ram_l1_3_val); + ret.r = uint(cpu.cache.ram_l1_66_addr); + ret.g = uint(cpu.cache.ram_l1_66_val); + return ret; + case 16: + ret.r = uint(cpu.cache.ram_l1_19_addr); + ret.g = uint(cpu.cache.ram_l1_19_val); + ret.b = uint(cpu.cache.ram_l1_35_addr); + ret.a = uint(cpu.cache.ram_l1_35_val); + return ret; + case 17: + ret.r = uint(cpu.cache.ram_l1_51_addr); + ret.g = uint(cpu.cache.ram_l1_51_val); + ret.b = uint(cpu.cache.ram_l1_67_addr); + ret.a = uint(cpu.cache.ram_l1_67_val); + return ret; + case 18: + ret.b = uint(cpu.cache.ram_l1_20_addr); + ret.a = uint(cpu.cache.ram_l1_20_val); + ret.r = uint(cpu.cache.ram_l1_4_addr); + ret.g = uint(cpu.cache.ram_l1_4_val); + return ret; + case 19: + ret.r = uint(cpu.cache.ram_l1_36_addr); + ret.g = uint(cpu.cache.ram_l1_36_val); + ret.b = uint(cpu.cache.ram_l1_52_addr); + ret.a = uint(cpu.cache.ram_l1_52_val); + return ret; + case 2: + ret.r = uint(cpu.cache.csr_cache_4_addr); + ret.g = uint(cpu.cache.csr_cache_4_val); + ret.b = uint(cpu.cache.csr_cache_5_addr); + ret.a = uint(cpu.cache.csr_cache_5_val); + return ret; + case 20: + ret.b = uint(cpu.cache.ram_l1_5_addr); + ret.a = uint(cpu.cache.ram_l1_5_val); + ret.r = uint(cpu.cache.ram_l1_68_addr); + ret.g = uint(cpu.cache.ram_l1_68_val); + return ret; + case 21: + ret.r = uint(cpu.cache.ram_l1_21_addr); + ret.g = uint(cpu.cache.ram_l1_21_val); + ret.b = uint(cpu.cache.ram_l1_37_addr); + ret.a = uint(cpu.cache.ram_l1_37_val); + return ret; + case 22: + ret.r = uint(cpu.cache.ram_l1_53_addr); + ret.g = uint(cpu.cache.ram_l1_53_val); + ret.b = uint(cpu.cache.ram_l1_69_addr); + ret.a = uint(cpu.cache.ram_l1_69_val); + return ret; + case 23: + ret.b = uint(cpu.cache.ram_l1_22_addr); + ret.a = uint(cpu.cache.ram_l1_22_val); + ret.r = uint(cpu.cache.ram_l1_6_addr); + ret.g = uint(cpu.cache.ram_l1_6_val); + return ret; + case 24: + ret.r = uint(cpu.cache.ram_l1_38_addr); + ret.g = uint(cpu.cache.ram_l1_38_val); + ret.b = uint(cpu.cache.ram_l1_54_addr); + ret.a = uint(cpu.cache.ram_l1_54_val); + return ret; + case 25: + ret.r = uint(cpu.cache.ram_l1_70_addr); + ret.g = uint(cpu.cache.ram_l1_70_val); + ret.b = uint(cpu.cache.ram_l1_7_addr); + ret.a = uint(cpu.cache.ram_l1_7_val); + return ret; + case 26: + ret.r = uint(cpu.cache.ram_l1_23_addr); + ret.g = uint(cpu.cache.ram_l1_23_val); + ret.b = uint(cpu.cache.ram_l1_39_addr); + ret.a = uint(cpu.cache.ram_l1_39_val); + return ret; + case 27: + ret.r = uint(cpu.cache.ram_l1_55_addr); + ret.g = uint(cpu.cache.ram_l1_55_val); + ret.b = uint(cpu.cache.ram_l1_71_addr); + ret.a = uint(cpu.cache.ram_l1_71_val); + return ret; + case 28: + ret.b = uint(cpu.cache.ram_l1_24_addr); + ret.a = uint(cpu.cache.ram_l1_24_val); + ret.r = uint(cpu.cache.ram_l1_8_addr); + ret.g = uint(cpu.cache.ram_l1_8_val); + return ret; + case 29: + ret.r = uint(cpu.cache.ram_l1_40_addr); + ret.g = uint(cpu.cache.ram_l1_40_val); + ret.b = uint(cpu.cache.ram_l1_56_addr); + ret.a = uint(cpu.cache.ram_l1_56_val); + return ret; + case 3: + ret.r = uint(cpu.cache.csr_cache_6_addr); + ret.g = uint(cpu.cache.csr_cache_6_val); + ret.b = uint(cpu.cache.csr_cache_7_addr); + ret.a = uint(cpu.cache.csr_cache_7_val); + return ret; + case 30: + ret.r = uint(cpu.cache.ram_l1_72_addr); + ret.g = uint(cpu.cache.ram_l1_72_val); + ret.b = uint(cpu.cache.ram_l1_9_addr); + ret.a = uint(cpu.cache.ram_l1_9_val); + return ret; + case 31: + ret.r = uint(cpu.cache.ram_l1_25_addr); + ret.g = uint(cpu.cache.ram_l1_25_val); + ret.b = uint(cpu.cache.ram_l1_41_addr); + ret.a = uint(cpu.cache.ram_l1_41_val); + return ret; + case 32: + ret.r = uint(cpu.cache.ram_l1_57_addr); + ret.g = uint(cpu.cache.ram_l1_57_val); + ret.b = uint(cpu.cache.ram_l1_73_addr); + ret.a = uint(cpu.cache.ram_l1_73_val); + return ret; + case 33: + ret.r = uint(cpu.cache.ram_l1_10_addr); + ret.g = uint(cpu.cache.ram_l1_10_val); + ret.b = uint(cpu.cache.ram_l1_26_addr); + ret.a = uint(cpu.cache.ram_l1_26_val); + return ret; + case 34: + ret.r = uint(cpu.cache.ram_l1_42_addr); + ret.g = uint(cpu.cache.ram_l1_42_val); + ret.b = uint(cpu.cache.ram_l1_58_addr); + ret.a = uint(cpu.cache.ram_l1_58_val); + return ret; + case 35: + ret.b = uint(cpu.cache.ram_l1_11_addr); + ret.a = uint(cpu.cache.ram_l1_11_val); + ret.r = uint(cpu.cache.ram_l1_74_addr); + ret.g = uint(cpu.cache.ram_l1_74_val); + return ret; + case 36: + ret.r = uint(cpu.cache.ram_l1_27_addr); + ret.g = uint(cpu.cache.ram_l1_27_val); + ret.b = uint(cpu.cache.ram_l1_43_addr); + ret.a = uint(cpu.cache.ram_l1_43_val); + return ret; + case 37: + ret.r = uint(cpu.cache.ram_l1_59_addr); + ret.g = uint(cpu.cache.ram_l1_59_val); + ret.b = uint(cpu.cache.ram_l1_75_addr); + ret.a = uint(cpu.cache.ram_l1_75_val); + return ret; + case 38: + ret.r = uint(cpu.cache.ram_l1_12_addr); + ret.g = uint(cpu.cache.ram_l1_12_val); + ret.b = uint(cpu.cache.ram_l1_28_addr); + ret.a = uint(cpu.cache.ram_l1_28_val); + return ret; + case 39: + ret.r = uint(cpu.cache.ram_l1_44_addr); + ret.g = uint(cpu.cache.ram_l1_44_val); + ret.b = uint(cpu.cache.ram_l1_60_addr); + ret.a = uint(cpu.cache.ram_l1_60_val); + return ret; + case 4: + ret.r = uint(cpu.cache.csr_cache_8_addr); + ret.g = uint(cpu.cache.csr_cache_8_val); + ret.b = uint(cpu.cache.csr_cache_9_addr); + ret.a = uint(cpu.cache.csr_cache_9_val); + return ret; + case 40: + ret.b = uint(cpu.cache.ram_l1_13_addr); + ret.a = uint(cpu.cache.ram_l1_13_val); + ret.r = uint(cpu.cache.ram_l1_76_addr); + ret.g = uint(cpu.cache.ram_l1_76_val); + return ret; + case 41: + ret.r = uint(cpu.cache.ram_l1_29_addr); + ret.g = uint(cpu.cache.ram_l1_29_val); + ret.b = uint(cpu.cache.ram_l1_45_addr); + ret.a = uint(cpu.cache.ram_l1_45_val); + return ret; + case 42: + ret.r = uint(cpu.cache.ram_l1_61_addr); + ret.g = uint(cpu.cache.ram_l1_61_val); + ret.b = uint(cpu.cache.ram_l1_77_addr); + ret.a = uint(cpu.cache.ram_l1_77_val); + return ret; + case 43: + ret.r = uint(cpu.cache.ram_l1_14_addr); + ret.g = uint(cpu.cache.ram_l1_14_val); + ret.b = uint(cpu.cache.ram_l1_30_addr); + ret.a = uint(cpu.cache.ram_l1_30_val); + return ret; + case 44: + ret.r = uint(cpu.cache.ram_l1_46_addr); + ret.g = uint(cpu.cache.ram_l1_46_val); + ret.b = uint(cpu.cache.ram_l1_62_addr); + ret.a = uint(cpu.cache.ram_l1_62_val); + return ret; + case 45: + ret.b = uint(cpu.cache.ram_l1_15_addr); + ret.a = uint(cpu.cache.ram_l1_15_val); + ret.r = uint(cpu.cache.ram_l1_78_addr); + ret.g = uint(cpu.cache.ram_l1_78_val); + return ret; + case 46: + ret.r = uint(cpu.cache.ram_l1_31_addr); + ret.g = uint(cpu.cache.ram_l1_31_val); + ret.b = uint(cpu.cache.ram_l1_47_addr); + ret.a = uint(cpu.cache.ram_l1_47_val); + return ret; + case 47: + ret.r = uint(cpu.cache.ram_l1_63_addr); + ret.g = uint(cpu.cache.ram_l1_63_val); + ret.b = uint(cpu.cache.ram_l1_79_addr); + ret.a = uint(cpu.cache.ram_l1_79_val); + return ret; + case 48: + ret.r = uint(cpu.cache.ram_l1_last_addr); + ret.g = uint(cpu.cache.ram_l1_last_val); + ret.b = uint(cpu.csr.privilege); + ret.a = uint(cpu.uart.rbr_thr_ier_iir); + return ret; + case 49: + ret.a = uint(cpu.uart.input_tag); + ret.b = uint(cpu.uart.interrupting); + ret.r = uint(cpu.uart.lcr_mcr_lsr_scr); + ret.g = uint(cpu.uart.thre_ip); + return ret; + case 5: + ret.r = uint(cpu.cache.csr_cache_10_addr); + ret.g = uint(cpu.cache.csr_cache_10_val); + ret.b = uint(cpu.cache.csr_cache_11_addr); + ret.a = uint(cpu.cache.csr_cache_11_val); + return ret; + case 50: + ret.r = uint(cpu.clint.msip); + ret.a = uint(cpu.clint.mtime_lo); + ret.b = uint(cpu.clint.mtimecmp_hi); + ret.g = uint(cpu.clint.mtimecmp_lo); + return ret; + case 51: + ret.r = uint(cpu.clint.mtime_hi); + ret.b = uint(cpu.uart_buffer.buf0); + ret.a = uint(cpu.uart_buffer.buf1); + ret.g = uint(cpu.uart_buffer.ptr); + return ret; + case 52: + ret.r = uint(cpu.uart_buffer.buf2); + ret.g = uint(cpu.uart_buffer.buf3); + ret.b = uint(cpu.uart_buffer.buf4); + ret.a = uint(cpu.uart_buffer.buf5); + return ret; + case 53: + ret.r = uint(cpu.uart_buffer.buf6); + ret.g = uint(cpu.uart_buffer.buf7); + ret.b = uint(cpu.uart_buffer.buf8); + ret.a = uint(cpu.uart_buffer.buf9); + return ret; + case 54: + ret.r = uint(cpu.uart_buffer.buf10); + ret.g = uint(cpu.uart_buffer.buf11); + ret.b = uint(cpu.uart_buffer.buf12); + ret.a = uint(cpu.uart_buffer.buf13); + return ret; + case 55: + ret.r = uint(cpu.uart_buffer.buf14); + ret.g = uint(cpu.uart_buffer.buf15); + ret.b = uint(cpu.uart_buffer.buf16); + ret.a = uint(cpu.uart_buffer.buf17); + return ret; + case 56: + ret.r = uint(cpu.uart_buffer.buf18); + ret.g = uint(cpu.uart_buffer.buf19); + ret.b = uint(cpu.uart_buffer.buf20); + ret.a = uint(cpu.uart_buffer.buf21); + return ret; + case 57: + ret.r = uint(cpu.uart_buffer.buf22); + ret.g = uint(cpu.uart_buffer.buf23); + ret.b = uint(cpu.uart_buffer.buf24); + ret.a = uint(cpu.uart_buffer.buf25); + return ret; + case 58: + ret.r = uint(cpu.uart_buffer.buf26); + ret.g = uint(cpu.uart_buffer.buf27); + ret.b = uint(cpu.uart_buffer.buf28); + ret.a = uint(cpu.uart_buffer.buf29); + return ret; + case 59: + ret.r = uint(cpu.uart_buffer.buf30); + ret.g = uint(cpu.uart_buffer.buf31); + ret.b = uint(cpu.uart_buffer.buf32); + ret.a = uint(cpu.uart_buffer.buf33); + return ret; + case 6: + ret.r = uint(cpu.cache.csr_cache_12_addr); + ret.g = uint(cpu.cache.csr_cache_12_val); + ret.b = uint(cpu.cache.csr_cache_13_addr); + ret.a = uint(cpu.cache.csr_cache_13_val); + return ret; + case 60: + ret.r = uint(cpu.uart_buffer.buf34); + ret.g = uint(cpu.uart_buffer.buf35); + ret.b = uint(cpu.uart_buffer.buf36); + ret.a = uint(cpu.uart_buffer.buf37); + return ret; + case 61: + ret.r = uint(cpu.uart_buffer.buf38); + ret.g = uint(cpu.uart_buffer.buf39); + ret.b = uint(cpu.uart_buffer.buf40); + ret.a = uint(cpu.uart_buffer.buf41); + return ret; + case 62: + ret.r = uint(cpu.uart_buffer.buf42); + ret.g = uint(cpu.uart_buffer.buf43); + ret.b = uint(cpu.uart_buffer.buf44); + ret.a = uint(cpu.uart_buffer.buf45); + return ret; + case 63: + ret.r = uint(cpu.uart_buffer.buf46); + ret.g = uint(cpu.uart_buffer.buf47); + ret.b = uint(cpu.uart_buffer.buf48); + ret.a = uint(cpu.uart_buffer.buf49); + return ret; + case 64: + ret.r = uint(cpu.uart_buffer.buf50); + ret.g = uint(cpu.uart_buffer.buf51); + ret.b = uint(cpu.uart_buffer.buf52); + ret.a = uint(cpu.uart_buffer.buf53); + return ret; + case 65: + ret.r = uint(cpu.uart_buffer.buf54); + ret.g = uint(cpu.uart_buffer.buf55); + ret.b = uint(cpu.uart_buffer.buf56); + ret.a = uint(cpu.uart_buffer.buf57); + return ret; + case 66: + ret.r = uint(cpu.uart_buffer.buf58); + ret.g = uint(cpu.uart_buffer.buf59); + ret.b = uint(cpu.uart_buffer.buf60); + ret.a = uint(cpu.uart_buffer.buf61); + return ret; + case 67: + ret.b = uint(cpu.mmu.mode); + ret.a = uint(cpu.mmu.ppn); + ret.r = uint(cpu.uart_buffer.buf62); + ret.g = uint(cpu.uart_buffer.buf63); + return ret; + case 68: + ret.g = uint(cpu.clock); + ret.b = uint(cpu.commits); + ret.r = uint(cpu.stall == STALL_CSR_CACHE ? 0 : (cpu.stall == STALL_MEM_CACHE_L1 ? 0 : cpu.stall)); + ret.a = uint(cpu.xreg0); + return ret; + case 69: + ret.r = uint(cpu.xreg1); + ret.g = uint(cpu.xreg2); + ret.b = uint(cpu.xreg3); + ret.a = uint(cpu.xreg4); + return ret; + case 7: + ret.r = uint(cpu.cache.csr_cache_14_addr); + ret.g = uint(cpu.cache.csr_cache_14_val); + ret.b = uint(cpu.cache.csr_cache_15_addr); + ret.a = uint(cpu.cache.csr_cache_15_val); + return ret; + case 70: + ret.r = uint(cpu.xreg5); + ret.g = uint(cpu.xreg6); + ret.b = uint(cpu.xreg7); + ret.a = uint(cpu.xreg8); + return ret; + case 71: + ret.g = uint(cpu.xreg10); + ret.b = uint(cpu.xreg11); + ret.a = uint(cpu.xreg12); + ret.r = uint(cpu.xreg9); + return ret; + case 72: + ret.r = uint(cpu.xreg13); + ret.g = uint(cpu.xreg14); + ret.b = uint(cpu.xreg15); + ret.a = uint(cpu.xreg16); + return ret; + case 73: + ret.r = uint(cpu.xreg17); + ret.g = uint(cpu.xreg18); + ret.b = uint(cpu.xreg19); + ret.a = uint(cpu.xreg20); + return ret; + case 74: + ret.r = uint(cpu.xreg21); + ret.g = uint(cpu.xreg22); + ret.b = uint(cpu.xreg23); + ret.a = uint(cpu.xreg24); + return ret; + case 75: + ret.r = uint(cpu.xreg25); + ret.g = uint(cpu.xreg26); + ret.b = uint(cpu.xreg27); + ret.a = uint(cpu.xreg28); + return ret; + case 76: + ret.a = uint(cpu.pc); + ret.r = uint(cpu.xreg29); + ret.g = uint(cpu.xreg30); + ret.b = uint(cpu.xreg31); + return ret; + case 77: + ret.a = uint(cpu.memop_dst_v); + ret.b = uint(cpu.memop_src_v); + ret.g = uint(cpu.reservation_addr); + ret.r = uint(cpu.reservation_en); + return ret; + case 78: + ret.g = uint(cpu.memop_dst_p); + ret.b = uint(cpu.memop_n); + ret.r = uint(cpu.memop_src_p); + ret.a = uint(cpu.stall_count); + return ret; + case 79: + ret.g = uint(cpu.debug_do_tick); + ret.b = uint(cpu.debug_last_ins); + ret.a = uint(cpu.stall); + ret.r = uint(cpu.trap_count); + return ret; + case 8: + ret.r = uint(cpu.cache.ram_l1_0_addr); + ret.g = uint(cpu.cache.ram_l1_0_val); + ret.b = uint(cpu.cache.ram_l1_16_addr); + ret.a = uint(cpu.cache.ram_l1_16_val); + return ret; + case 80: + ret.r = uint(cpu.debug_arb_0); + return ret; + case 9: + ret.r = uint(cpu.cache.ram_l1_32_addr); + ret.g = uint(cpu.cache.ram_l1_32_val); + ret.b = uint(cpu.cache.ram_l1_48_addr); + ret.a = uint(cpu.cache.ram_l1_48_val); + return ret; + + } + + return ret; +} + +uint tex_get_csr(uint addr) { + uint lin = (addr >> 2) + 324; + uint idx = addr & 0x3; + return idx_uint4(STATE_TEX[uint2(lin % 128, lin / 128)], idx); +} + +#define RAM_ADDR(lin) uint2(lin % 2048, 128 + (lin / 2048)) +#define RAM_MAX (2048 * (2048 - 128) * 4 * 4) + + +// Memory operations (should be in mem.h but cyclic dependencies...) + +// Basic bloom filter to slightly optimize memory caching +#ifdef PASS_TICK +static uint mem_cache_bloom = 0; +#else +static uint mem_cache_bloom = 0xffffffff; +#endif + +[noinline] // I'm pretty sure this does nothing, but see it as a prayer to the compiler gods +uint mem_get_cached_or_tex(uint addr) { + // query L1 cache + if ((addr & mem_cache_bloom) != addr) { /* not cached */ } + else { + [forcecase] + switch (RAM_L1_TAG(addr)) { +case 0: + if (cpu.cache.ram_l1_0_addr == addr) { return cpu.cache.ram_l1_0_val; } +else if (cpu.cache.ram_l1_16_addr == addr) { return cpu.cache.ram_l1_16_val; } +else if (cpu.cache.ram_l1_32_addr == addr) { return cpu.cache.ram_l1_32_val; } +else if (cpu.cache.ram_l1_48_addr == addr) { return cpu.cache.ram_l1_48_val; } +else if (cpu.cache.ram_l1_64_addr == addr) { return cpu.cache.ram_l1_64_val; } +break; +case 1: + if (cpu.cache.ram_l1_1_addr == addr) { return cpu.cache.ram_l1_1_val; } +else if (cpu.cache.ram_l1_17_addr == addr) { return cpu.cache.ram_l1_17_val; } +else if (cpu.cache.ram_l1_33_addr == addr) { return cpu.cache.ram_l1_33_val; } +else if (cpu.cache.ram_l1_49_addr == addr) { return cpu.cache.ram_l1_49_val; } +else if (cpu.cache.ram_l1_65_addr == addr) { return cpu.cache.ram_l1_65_val; } +break; +case 2: + if (cpu.cache.ram_l1_2_addr == addr) { return cpu.cache.ram_l1_2_val; } +else if (cpu.cache.ram_l1_18_addr == addr) { return cpu.cache.ram_l1_18_val; } +else if (cpu.cache.ram_l1_34_addr == addr) { return cpu.cache.ram_l1_34_val; } +else if (cpu.cache.ram_l1_50_addr == addr) { return cpu.cache.ram_l1_50_val; } +else if (cpu.cache.ram_l1_66_addr == addr) { return cpu.cache.ram_l1_66_val; } +break; +case 3: + if (cpu.cache.ram_l1_3_addr == addr) { return cpu.cache.ram_l1_3_val; } +else if (cpu.cache.ram_l1_19_addr == addr) { return cpu.cache.ram_l1_19_val; } +else if (cpu.cache.ram_l1_35_addr == addr) { return cpu.cache.ram_l1_35_val; } +else if (cpu.cache.ram_l1_51_addr == addr) { return cpu.cache.ram_l1_51_val; } +else if (cpu.cache.ram_l1_67_addr == addr) { return cpu.cache.ram_l1_67_val; } +break; +case 4: + if (cpu.cache.ram_l1_4_addr == addr) { return cpu.cache.ram_l1_4_val; } +else if (cpu.cache.ram_l1_20_addr == addr) { return cpu.cache.ram_l1_20_val; } +else if (cpu.cache.ram_l1_36_addr == addr) { return cpu.cache.ram_l1_36_val; } +else if (cpu.cache.ram_l1_52_addr == addr) { return cpu.cache.ram_l1_52_val; } +else if (cpu.cache.ram_l1_68_addr == addr) { return cpu.cache.ram_l1_68_val; } +break; +case 5: + if (cpu.cache.ram_l1_5_addr == addr) { return cpu.cache.ram_l1_5_val; } +else if (cpu.cache.ram_l1_21_addr == addr) { return cpu.cache.ram_l1_21_val; } +else if (cpu.cache.ram_l1_37_addr == addr) { return cpu.cache.ram_l1_37_val; } +else if (cpu.cache.ram_l1_53_addr == addr) { return cpu.cache.ram_l1_53_val; } +else if (cpu.cache.ram_l1_69_addr == addr) { return cpu.cache.ram_l1_69_val; } +break; +case 6: + if (cpu.cache.ram_l1_6_addr == addr) { return cpu.cache.ram_l1_6_val; } +else if (cpu.cache.ram_l1_22_addr == addr) { return cpu.cache.ram_l1_22_val; } +else if (cpu.cache.ram_l1_38_addr == addr) { return cpu.cache.ram_l1_38_val; } +else if (cpu.cache.ram_l1_54_addr == addr) { return cpu.cache.ram_l1_54_val; } +else if (cpu.cache.ram_l1_70_addr == addr) { return cpu.cache.ram_l1_70_val; } +break; +case 7: + if (cpu.cache.ram_l1_7_addr == addr) { return cpu.cache.ram_l1_7_val; } +else if (cpu.cache.ram_l1_23_addr == addr) { return cpu.cache.ram_l1_23_val; } +else if (cpu.cache.ram_l1_39_addr == addr) { return cpu.cache.ram_l1_39_val; } +else if (cpu.cache.ram_l1_55_addr == addr) { return cpu.cache.ram_l1_55_val; } +else if (cpu.cache.ram_l1_71_addr == addr) { return cpu.cache.ram_l1_71_val; } +break; +case 8: + if (cpu.cache.ram_l1_8_addr == addr) { return cpu.cache.ram_l1_8_val; } +else if (cpu.cache.ram_l1_24_addr == addr) { return cpu.cache.ram_l1_24_val; } +else if (cpu.cache.ram_l1_40_addr == addr) { return cpu.cache.ram_l1_40_val; } +else if (cpu.cache.ram_l1_56_addr == addr) { return cpu.cache.ram_l1_56_val; } +else if (cpu.cache.ram_l1_72_addr == addr) { return cpu.cache.ram_l1_72_val; } +break; +case 9: + if (cpu.cache.ram_l1_9_addr == addr) { return cpu.cache.ram_l1_9_val; } +else if (cpu.cache.ram_l1_25_addr == addr) { return cpu.cache.ram_l1_25_val; } +else if (cpu.cache.ram_l1_41_addr == addr) { return cpu.cache.ram_l1_41_val; } +else if (cpu.cache.ram_l1_57_addr == addr) { return cpu.cache.ram_l1_57_val; } +else if (cpu.cache.ram_l1_73_addr == addr) { return cpu.cache.ram_l1_73_val; } +break; +case 10: + if (cpu.cache.ram_l1_10_addr == addr) { return cpu.cache.ram_l1_10_val; } +else if (cpu.cache.ram_l1_26_addr == addr) { return cpu.cache.ram_l1_26_val; } +else if (cpu.cache.ram_l1_42_addr == addr) { return cpu.cache.ram_l1_42_val; } +else if (cpu.cache.ram_l1_58_addr == addr) { return cpu.cache.ram_l1_58_val; } +else if (cpu.cache.ram_l1_74_addr == addr) { return cpu.cache.ram_l1_74_val; } +break; +case 11: + if (cpu.cache.ram_l1_11_addr == addr) { return cpu.cache.ram_l1_11_val; } +else if (cpu.cache.ram_l1_27_addr == addr) { return cpu.cache.ram_l1_27_val; } +else if (cpu.cache.ram_l1_43_addr == addr) { return cpu.cache.ram_l1_43_val; } +else if (cpu.cache.ram_l1_59_addr == addr) { return cpu.cache.ram_l1_59_val; } +else if (cpu.cache.ram_l1_75_addr == addr) { return cpu.cache.ram_l1_75_val; } +break; +case 12: + if (cpu.cache.ram_l1_12_addr == addr) { return cpu.cache.ram_l1_12_val; } +else if (cpu.cache.ram_l1_28_addr == addr) { return cpu.cache.ram_l1_28_val; } +else if (cpu.cache.ram_l1_44_addr == addr) { return cpu.cache.ram_l1_44_val; } +else if (cpu.cache.ram_l1_60_addr == addr) { return cpu.cache.ram_l1_60_val; } +else if (cpu.cache.ram_l1_76_addr == addr) { return cpu.cache.ram_l1_76_val; } +break; +case 13: + if (cpu.cache.ram_l1_13_addr == addr) { return cpu.cache.ram_l1_13_val; } +else if (cpu.cache.ram_l1_29_addr == addr) { return cpu.cache.ram_l1_29_val; } +else if (cpu.cache.ram_l1_45_addr == addr) { return cpu.cache.ram_l1_45_val; } +else if (cpu.cache.ram_l1_61_addr == addr) { return cpu.cache.ram_l1_61_val; } +else if (cpu.cache.ram_l1_77_addr == addr) { return cpu.cache.ram_l1_77_val; } +break; +case 14: + if (cpu.cache.ram_l1_14_addr == addr) { return cpu.cache.ram_l1_14_val; } +else if (cpu.cache.ram_l1_30_addr == addr) { return cpu.cache.ram_l1_30_val; } +else if (cpu.cache.ram_l1_46_addr == addr) { return cpu.cache.ram_l1_46_val; } +else if (cpu.cache.ram_l1_62_addr == addr) { return cpu.cache.ram_l1_62_val; } +else if (cpu.cache.ram_l1_78_addr == addr) { return cpu.cache.ram_l1_78_val; } +break; +case 15: + if (cpu.cache.ram_l1_15_addr == addr) { return cpu.cache.ram_l1_15_val; } +else if (cpu.cache.ram_l1_31_addr == addr) { return cpu.cache.ram_l1_31_val; } +else if (cpu.cache.ram_l1_47_addr == addr) { return cpu.cache.ram_l1_47_val; } +else if (cpu.cache.ram_l1_63_addr == addr) { return cpu.cache.ram_l1_63_val; } +else if (cpu.cache.ram_l1_79_addr == addr) { return cpu.cache.ram_l1_79_val; } +break; + + } + + if (cpu.cache.ram_l1_last_addr == addr) { + return cpu.cache.ram_l1_last_val; + } + } + + uint idx = (addr >> 2) & 0x3; + addr >>= 4; + + uint4 raw = STATE_TEX[RAM_ADDR(addr)]; + return idx_uint4(raw, idx); +} + + +#ifdef PASS_COMMIT +uint4 commit(uint2 pos) { + if (pos.y < 128 && pos.x >= 128) { + return (uint4)0; + } + + // fallback is passthrough + uint4 ret = STATE_TEX[pos]; + + uint pos_id = pos.x | (pos.y << 16); + + // increment commits + if (!_Init && pos_id == 68) { + ++ret.b; + } + + // clear stall + if (pos_id == 68) { + [flatten] + switch (ret.r) { + case STALL_MEM_CACHE_L2: + ret.r = 0; + break; + case STALL_FENCE: + ret.r = 0; + break; + case STALL_MEMOP_COPY: // will be handled now, so we can unset + ret.r = 0; + break; + } + } + + uint s_lin = pos.x + pos.y * 128; + + // CSR area + if (s_lin >= 324 && s_lin < 1348) { + uint addr = s_lin - 324; + addr <<= 2; + if (cpu.cache.csr_cache_0_addr == addr + 0) { ret.x = cpu.cache.csr_cache_0_val; } + else if (cpu.cache.csr_cache_0_addr == addr + 1) { ret.y = cpu.cache.csr_cache_0_val; } + else if (cpu.cache.csr_cache_0_addr == addr + 2) { ret.z = cpu.cache.csr_cache_0_val; } + else if (cpu.cache.csr_cache_0_addr == addr + 3) { ret.w = cpu.cache.csr_cache_0_val; } + if (cpu.cache.csr_cache_1_addr == addr + 0) { ret.x = cpu.cache.csr_cache_1_val; } + else if (cpu.cache.csr_cache_1_addr == addr + 1) { ret.y = cpu.cache.csr_cache_1_val; } + else if (cpu.cache.csr_cache_1_addr == addr + 2) { ret.z = cpu.cache.csr_cache_1_val; } + else if (cpu.cache.csr_cache_1_addr == addr + 3) { ret.w = cpu.cache.csr_cache_1_val; } + if (cpu.cache.csr_cache_2_addr == addr + 0) { ret.x = cpu.cache.csr_cache_2_val; } + else if (cpu.cache.csr_cache_2_addr == addr + 1) { ret.y = cpu.cache.csr_cache_2_val; } + else if (cpu.cache.csr_cache_2_addr == addr + 2) { ret.z = cpu.cache.csr_cache_2_val; } + else if (cpu.cache.csr_cache_2_addr == addr + 3) { ret.w = cpu.cache.csr_cache_2_val; } + if (cpu.cache.csr_cache_3_addr == addr + 0) { ret.x = cpu.cache.csr_cache_3_val; } + else if (cpu.cache.csr_cache_3_addr == addr + 1) { ret.y = cpu.cache.csr_cache_3_val; } + else if (cpu.cache.csr_cache_3_addr == addr + 2) { ret.z = cpu.cache.csr_cache_3_val; } + else if (cpu.cache.csr_cache_3_addr == addr + 3) { ret.w = cpu.cache.csr_cache_3_val; } + if (cpu.cache.csr_cache_4_addr == addr + 0) { ret.x = cpu.cache.csr_cache_4_val; } + else if (cpu.cache.csr_cache_4_addr == addr + 1) { ret.y = cpu.cache.csr_cache_4_val; } + else if (cpu.cache.csr_cache_4_addr == addr + 2) { ret.z = cpu.cache.csr_cache_4_val; } + else if (cpu.cache.csr_cache_4_addr == addr + 3) { ret.w = cpu.cache.csr_cache_4_val; } + if (cpu.cache.csr_cache_5_addr == addr + 0) { ret.x = cpu.cache.csr_cache_5_val; } + else if (cpu.cache.csr_cache_5_addr == addr + 1) { ret.y = cpu.cache.csr_cache_5_val; } + else if (cpu.cache.csr_cache_5_addr == addr + 2) { ret.z = cpu.cache.csr_cache_5_val; } + else if (cpu.cache.csr_cache_5_addr == addr + 3) { ret.w = cpu.cache.csr_cache_5_val; } + if (cpu.cache.csr_cache_6_addr == addr + 0) { ret.x = cpu.cache.csr_cache_6_val; } + else if (cpu.cache.csr_cache_6_addr == addr + 1) { ret.y = cpu.cache.csr_cache_6_val; } + else if (cpu.cache.csr_cache_6_addr == addr + 2) { ret.z = cpu.cache.csr_cache_6_val; } + else if (cpu.cache.csr_cache_6_addr == addr + 3) { ret.w = cpu.cache.csr_cache_6_val; } + if (cpu.cache.csr_cache_7_addr == addr + 0) { ret.x = cpu.cache.csr_cache_7_val; } + else if (cpu.cache.csr_cache_7_addr == addr + 1) { ret.y = cpu.cache.csr_cache_7_val; } + else if (cpu.cache.csr_cache_7_addr == addr + 2) { ret.z = cpu.cache.csr_cache_7_val; } + else if (cpu.cache.csr_cache_7_addr == addr + 3) { ret.w = cpu.cache.csr_cache_7_val; } + if (cpu.cache.csr_cache_8_addr == addr + 0) { ret.x = cpu.cache.csr_cache_8_val; } + else if (cpu.cache.csr_cache_8_addr == addr + 1) { ret.y = cpu.cache.csr_cache_8_val; } + else if (cpu.cache.csr_cache_8_addr == addr + 2) { ret.z = cpu.cache.csr_cache_8_val; } + else if (cpu.cache.csr_cache_8_addr == addr + 3) { ret.w = cpu.cache.csr_cache_8_val; } + if (cpu.cache.csr_cache_9_addr == addr + 0) { ret.x = cpu.cache.csr_cache_9_val; } + else if (cpu.cache.csr_cache_9_addr == addr + 1) { ret.y = cpu.cache.csr_cache_9_val; } + else if (cpu.cache.csr_cache_9_addr == addr + 2) { ret.z = cpu.cache.csr_cache_9_val; } + else if (cpu.cache.csr_cache_9_addr == addr + 3) { ret.w = cpu.cache.csr_cache_9_val; } + if (cpu.cache.csr_cache_10_addr == addr + 0) { ret.x = cpu.cache.csr_cache_10_val; } + else if (cpu.cache.csr_cache_10_addr == addr + 1) { ret.y = cpu.cache.csr_cache_10_val; } + else if (cpu.cache.csr_cache_10_addr == addr + 2) { ret.z = cpu.cache.csr_cache_10_val; } + else if (cpu.cache.csr_cache_10_addr == addr + 3) { ret.w = cpu.cache.csr_cache_10_val; } + if (cpu.cache.csr_cache_11_addr == addr + 0) { ret.x = cpu.cache.csr_cache_11_val; } + else if (cpu.cache.csr_cache_11_addr == addr + 1) { ret.y = cpu.cache.csr_cache_11_val; } + else if (cpu.cache.csr_cache_11_addr == addr + 2) { ret.z = cpu.cache.csr_cache_11_val; } + else if (cpu.cache.csr_cache_11_addr == addr + 3) { ret.w = cpu.cache.csr_cache_11_val; } + if (cpu.cache.csr_cache_12_addr == addr + 0) { ret.x = cpu.cache.csr_cache_12_val; } + else if (cpu.cache.csr_cache_12_addr == addr + 1) { ret.y = cpu.cache.csr_cache_12_val; } + else if (cpu.cache.csr_cache_12_addr == addr + 2) { ret.z = cpu.cache.csr_cache_12_val; } + else if (cpu.cache.csr_cache_12_addr == addr + 3) { ret.w = cpu.cache.csr_cache_12_val; } + if (cpu.cache.csr_cache_13_addr == addr + 0) { ret.x = cpu.cache.csr_cache_13_val; } + else if (cpu.cache.csr_cache_13_addr == addr + 1) { ret.y = cpu.cache.csr_cache_13_val; } + else if (cpu.cache.csr_cache_13_addr == addr + 2) { ret.z = cpu.cache.csr_cache_13_val; } + else if (cpu.cache.csr_cache_13_addr == addr + 3) { ret.w = cpu.cache.csr_cache_13_val; } + if (cpu.cache.csr_cache_14_addr == addr + 0) { ret.x = cpu.cache.csr_cache_14_val; } + else if (cpu.cache.csr_cache_14_addr == addr + 1) { ret.y = cpu.cache.csr_cache_14_val; } + else if (cpu.cache.csr_cache_14_addr == addr + 2) { ret.z = cpu.cache.csr_cache_14_val; } + else if (cpu.cache.csr_cache_14_addr == addr + 3) { ret.w = cpu.cache.csr_cache_14_val; } + if (cpu.cache.csr_cache_15_addr == addr + 0) { ret.x = cpu.cache.csr_cache_15_val; } + else if (cpu.cache.csr_cache_15_addr == addr + 1) { ret.y = cpu.cache.csr_cache_15_val; } + else if (cpu.cache.csr_cache_15_addr == addr + 2) { ret.z = cpu.cache.csr_cache_15_val; } + else if (cpu.cache.csr_cache_15_addr == addr + 3) { ret.w = cpu.cache.csr_cache_15_val; } + + } + + // RAM + if (pos.y >= 128) { + uint2 pos_ram = uint2(pos.x, pos.y - 128); + uint lin = pos_ram.x + pos_ram.y * 2048; + + if (_Init) { + // init main memory from texture + uint2 ram_dim; + _Data_RAM_A.GetDimensions(ram_dim.x, ram_dim.y); + + // TODO: something feels off here... off by one, you might say... + uint2 pos2 = uint2(lin % ram_dim.x, lin / ram_dim.x); + pos2.y = ram_dim.y - pos2.y - 1; + + if (pos2.y >= ram_dim.y) { + // zero unset memory + ret = uint4(0, 0, 0, 0); + } else { + uint r = unpack_raw_float4(_Data_RAM_R[pos2]); + uint g = unpack_raw_float4(_Data_RAM_G[pos2]); + uint b = unpack_raw_float4(_Data_RAM_B[pos2]); + uint a = unpack_raw_float4(_Data_RAM_A[pos2]); + ret = uint4(r, g, b, a); + } + } else { + lin <<= 4; + + if (cpu.stall == STALL_MEMOP_COPY && + (lin + (3 << 2)) >= cpu.memop_dst_p && + lin < (cpu.memop_dst_p + cpu.memop_n)) + { + // we've found ourselves in a position for a memcpy, ignore cache and perform it + // (a memop is always the last instruction in a commit cycle, so we know we have + // higher priority than the L1 cache) + [loop] + for (uint icp = 0; icp < 4; icp++) { + uint lin_word = lin + (icp << 2); + if (lin_word >= cpu.memop_dst_p && + lin_word < (cpu.memop_dst_p + cpu.memop_n)) + { + uint offset = cpu.memop_dst_p - lin_word; + uint src = cpu.memop_src_p + offset; + uint transfer = mem_get_cached_or_tex(src); + switch (icp) { + case 0: + ret.r = transfer; + break; + case 1: + ret.g = transfer; + break; + case 2: + ret.b = transfer; + break; + case 3: + ret.a = transfer; + break; + } + } + } + } + else + { + // write back L1 cache + if (cpu.cache.ram_l1_0_addr == lin) { ret.r = cpu.cache.ram_l1_0_val; } + else if (cpu.cache.ram_l1_0_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_0_val; } + else if (cpu.cache.ram_l1_0_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_0_val; } + else if (cpu.cache.ram_l1_0_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_0_val; } + if (cpu.cache.ram_l1_16_addr == lin) { ret.r = cpu.cache.ram_l1_16_val; } + else if (cpu.cache.ram_l1_16_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_16_val; } + else if (cpu.cache.ram_l1_16_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_16_val; } + else if (cpu.cache.ram_l1_16_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_16_val; } + if (cpu.cache.ram_l1_32_addr == lin) { ret.r = cpu.cache.ram_l1_32_val; } + else if (cpu.cache.ram_l1_32_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_32_val; } + else if (cpu.cache.ram_l1_32_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_32_val; } + else if (cpu.cache.ram_l1_32_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_32_val; } + if (cpu.cache.ram_l1_48_addr == lin) { ret.r = cpu.cache.ram_l1_48_val; } + else if (cpu.cache.ram_l1_48_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_48_val; } + else if (cpu.cache.ram_l1_48_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_48_val; } + else if (cpu.cache.ram_l1_48_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_48_val; } + if (cpu.cache.ram_l1_64_addr == lin) { ret.r = cpu.cache.ram_l1_64_val; } + else if (cpu.cache.ram_l1_64_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_64_val; } + else if (cpu.cache.ram_l1_64_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_64_val; } + else if (cpu.cache.ram_l1_64_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_64_val; } + if (cpu.cache.ram_l1_1_addr == lin) { ret.r = cpu.cache.ram_l1_1_val; } + else if (cpu.cache.ram_l1_1_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_1_val; } + else if (cpu.cache.ram_l1_1_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_1_val; } + else if (cpu.cache.ram_l1_1_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_1_val; } + if (cpu.cache.ram_l1_17_addr == lin) { ret.r = cpu.cache.ram_l1_17_val; } + else if (cpu.cache.ram_l1_17_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_17_val; } + else if (cpu.cache.ram_l1_17_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_17_val; } + else if (cpu.cache.ram_l1_17_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_17_val; } + if (cpu.cache.ram_l1_33_addr == lin) { ret.r = cpu.cache.ram_l1_33_val; } + else if (cpu.cache.ram_l1_33_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_33_val; } + else if (cpu.cache.ram_l1_33_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_33_val; } + else if (cpu.cache.ram_l1_33_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_33_val; } + if (cpu.cache.ram_l1_49_addr == lin) { ret.r = cpu.cache.ram_l1_49_val; } + else if (cpu.cache.ram_l1_49_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_49_val; } + else if (cpu.cache.ram_l1_49_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_49_val; } + else if (cpu.cache.ram_l1_49_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_49_val; } + if (cpu.cache.ram_l1_65_addr == lin) { ret.r = cpu.cache.ram_l1_65_val; } + else if (cpu.cache.ram_l1_65_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_65_val; } + else if (cpu.cache.ram_l1_65_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_65_val; } + else if (cpu.cache.ram_l1_65_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_65_val; } + if (cpu.cache.ram_l1_2_addr == lin) { ret.r = cpu.cache.ram_l1_2_val; } + else if (cpu.cache.ram_l1_2_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_2_val; } + else if (cpu.cache.ram_l1_2_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_2_val; } + else if (cpu.cache.ram_l1_2_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_2_val; } + if (cpu.cache.ram_l1_18_addr == lin) { ret.r = cpu.cache.ram_l1_18_val; } + else if (cpu.cache.ram_l1_18_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_18_val; } + else if (cpu.cache.ram_l1_18_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_18_val; } + else if (cpu.cache.ram_l1_18_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_18_val; } + if (cpu.cache.ram_l1_34_addr == lin) { ret.r = cpu.cache.ram_l1_34_val; } + else if (cpu.cache.ram_l1_34_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_34_val; } + else if (cpu.cache.ram_l1_34_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_34_val; } + else if (cpu.cache.ram_l1_34_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_34_val; } + if (cpu.cache.ram_l1_50_addr == lin) { ret.r = cpu.cache.ram_l1_50_val; } + else if (cpu.cache.ram_l1_50_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_50_val; } + else if (cpu.cache.ram_l1_50_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_50_val; } + else if (cpu.cache.ram_l1_50_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_50_val; } + if (cpu.cache.ram_l1_66_addr == lin) { ret.r = cpu.cache.ram_l1_66_val; } + else if (cpu.cache.ram_l1_66_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_66_val; } + else if (cpu.cache.ram_l1_66_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_66_val; } + else if (cpu.cache.ram_l1_66_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_66_val; } + if (cpu.cache.ram_l1_3_addr == lin) { ret.r = cpu.cache.ram_l1_3_val; } + else if (cpu.cache.ram_l1_3_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_3_val; } + else if (cpu.cache.ram_l1_3_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_3_val; } + else if (cpu.cache.ram_l1_3_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_3_val; } + if (cpu.cache.ram_l1_19_addr == lin) { ret.r = cpu.cache.ram_l1_19_val; } + else if (cpu.cache.ram_l1_19_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_19_val; } + else if (cpu.cache.ram_l1_19_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_19_val; } + else if (cpu.cache.ram_l1_19_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_19_val; } + if (cpu.cache.ram_l1_35_addr == lin) { ret.r = cpu.cache.ram_l1_35_val; } + else if (cpu.cache.ram_l1_35_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_35_val; } + else if (cpu.cache.ram_l1_35_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_35_val; } + else if (cpu.cache.ram_l1_35_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_35_val; } + if (cpu.cache.ram_l1_51_addr == lin) { ret.r = cpu.cache.ram_l1_51_val; } + else if (cpu.cache.ram_l1_51_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_51_val; } + else if (cpu.cache.ram_l1_51_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_51_val; } + else if (cpu.cache.ram_l1_51_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_51_val; } + if (cpu.cache.ram_l1_67_addr == lin) { ret.r = cpu.cache.ram_l1_67_val; } + else if (cpu.cache.ram_l1_67_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_67_val; } + else if (cpu.cache.ram_l1_67_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_67_val; } + else if (cpu.cache.ram_l1_67_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_67_val; } + if (cpu.cache.ram_l1_4_addr == lin) { ret.r = cpu.cache.ram_l1_4_val; } + else if (cpu.cache.ram_l1_4_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_4_val; } + else if (cpu.cache.ram_l1_4_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_4_val; } + else if (cpu.cache.ram_l1_4_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_4_val; } + if (cpu.cache.ram_l1_20_addr == lin) { ret.r = cpu.cache.ram_l1_20_val; } + else if (cpu.cache.ram_l1_20_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_20_val; } + else if (cpu.cache.ram_l1_20_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_20_val; } + else if (cpu.cache.ram_l1_20_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_20_val; } + if (cpu.cache.ram_l1_36_addr == lin) { ret.r = cpu.cache.ram_l1_36_val; } + else if (cpu.cache.ram_l1_36_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_36_val; } + else if (cpu.cache.ram_l1_36_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_36_val; } + else if (cpu.cache.ram_l1_36_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_36_val; } + if (cpu.cache.ram_l1_52_addr == lin) { ret.r = cpu.cache.ram_l1_52_val; } + else if (cpu.cache.ram_l1_52_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_52_val; } + else if (cpu.cache.ram_l1_52_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_52_val; } + else if (cpu.cache.ram_l1_52_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_52_val; } + if (cpu.cache.ram_l1_68_addr == lin) { ret.r = cpu.cache.ram_l1_68_val; } + else if (cpu.cache.ram_l1_68_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_68_val; } + else if (cpu.cache.ram_l1_68_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_68_val; } + else if (cpu.cache.ram_l1_68_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_68_val; } + if (cpu.cache.ram_l1_5_addr == lin) { ret.r = cpu.cache.ram_l1_5_val; } + else if (cpu.cache.ram_l1_5_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_5_val; } + else if (cpu.cache.ram_l1_5_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_5_val; } + else if (cpu.cache.ram_l1_5_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_5_val; } + if (cpu.cache.ram_l1_21_addr == lin) { ret.r = cpu.cache.ram_l1_21_val; } + else if (cpu.cache.ram_l1_21_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_21_val; } + else if (cpu.cache.ram_l1_21_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_21_val; } + else if (cpu.cache.ram_l1_21_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_21_val; } + if (cpu.cache.ram_l1_37_addr == lin) { ret.r = cpu.cache.ram_l1_37_val; } + else if (cpu.cache.ram_l1_37_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_37_val; } + else if (cpu.cache.ram_l1_37_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_37_val; } + else if (cpu.cache.ram_l1_37_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_37_val; } + if (cpu.cache.ram_l1_53_addr == lin) { ret.r = cpu.cache.ram_l1_53_val; } + else if (cpu.cache.ram_l1_53_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_53_val; } + else if (cpu.cache.ram_l1_53_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_53_val; } + else if (cpu.cache.ram_l1_53_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_53_val; } + if (cpu.cache.ram_l1_69_addr == lin) { ret.r = cpu.cache.ram_l1_69_val; } + else if (cpu.cache.ram_l1_69_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_69_val; } + else if (cpu.cache.ram_l1_69_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_69_val; } + else if (cpu.cache.ram_l1_69_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_69_val; } + if (cpu.cache.ram_l1_6_addr == lin) { ret.r = cpu.cache.ram_l1_6_val; } + else if (cpu.cache.ram_l1_6_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_6_val; } + else if (cpu.cache.ram_l1_6_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_6_val; } + else if (cpu.cache.ram_l1_6_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_6_val; } + if (cpu.cache.ram_l1_22_addr == lin) { ret.r = cpu.cache.ram_l1_22_val; } + else if (cpu.cache.ram_l1_22_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_22_val; } + else if (cpu.cache.ram_l1_22_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_22_val; } + else if (cpu.cache.ram_l1_22_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_22_val; } + if (cpu.cache.ram_l1_38_addr == lin) { ret.r = cpu.cache.ram_l1_38_val; } + else if (cpu.cache.ram_l1_38_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_38_val; } + else if (cpu.cache.ram_l1_38_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_38_val; } + else if (cpu.cache.ram_l1_38_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_38_val; } + if (cpu.cache.ram_l1_54_addr == lin) { ret.r = cpu.cache.ram_l1_54_val; } + else if (cpu.cache.ram_l1_54_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_54_val; } + else if (cpu.cache.ram_l1_54_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_54_val; } + else if (cpu.cache.ram_l1_54_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_54_val; } + if (cpu.cache.ram_l1_70_addr == lin) { ret.r = cpu.cache.ram_l1_70_val; } + else if (cpu.cache.ram_l1_70_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_70_val; } + else if (cpu.cache.ram_l1_70_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_70_val; } + else if (cpu.cache.ram_l1_70_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_70_val; } + if (cpu.cache.ram_l1_7_addr == lin) { ret.r = cpu.cache.ram_l1_7_val; } + else if (cpu.cache.ram_l1_7_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_7_val; } + else if (cpu.cache.ram_l1_7_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_7_val; } + else if (cpu.cache.ram_l1_7_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_7_val; } + if (cpu.cache.ram_l1_23_addr == lin) { ret.r = cpu.cache.ram_l1_23_val; } + else if (cpu.cache.ram_l1_23_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_23_val; } + else if (cpu.cache.ram_l1_23_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_23_val; } + else if (cpu.cache.ram_l1_23_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_23_val; } + if (cpu.cache.ram_l1_39_addr == lin) { ret.r = cpu.cache.ram_l1_39_val; } + else if (cpu.cache.ram_l1_39_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_39_val; } + else if (cpu.cache.ram_l1_39_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_39_val; } + else if (cpu.cache.ram_l1_39_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_39_val; } + if (cpu.cache.ram_l1_55_addr == lin) { ret.r = cpu.cache.ram_l1_55_val; } + else if (cpu.cache.ram_l1_55_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_55_val; } + else if (cpu.cache.ram_l1_55_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_55_val; } + else if (cpu.cache.ram_l1_55_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_55_val; } + if (cpu.cache.ram_l1_71_addr == lin) { ret.r = cpu.cache.ram_l1_71_val; } + else if (cpu.cache.ram_l1_71_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_71_val; } + else if (cpu.cache.ram_l1_71_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_71_val; } + else if (cpu.cache.ram_l1_71_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_71_val; } + if (cpu.cache.ram_l1_8_addr == lin) { ret.r = cpu.cache.ram_l1_8_val; } + else if (cpu.cache.ram_l1_8_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_8_val; } + else if (cpu.cache.ram_l1_8_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_8_val; } + else if (cpu.cache.ram_l1_8_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_8_val; } + if (cpu.cache.ram_l1_24_addr == lin) { ret.r = cpu.cache.ram_l1_24_val; } + else if (cpu.cache.ram_l1_24_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_24_val; } + else if (cpu.cache.ram_l1_24_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_24_val; } + else if (cpu.cache.ram_l1_24_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_24_val; } + if (cpu.cache.ram_l1_40_addr == lin) { ret.r = cpu.cache.ram_l1_40_val; } + else if (cpu.cache.ram_l1_40_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_40_val; } + else if (cpu.cache.ram_l1_40_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_40_val; } + else if (cpu.cache.ram_l1_40_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_40_val; } + if (cpu.cache.ram_l1_56_addr == lin) { ret.r = cpu.cache.ram_l1_56_val; } + else if (cpu.cache.ram_l1_56_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_56_val; } + else if (cpu.cache.ram_l1_56_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_56_val; } + else if (cpu.cache.ram_l1_56_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_56_val; } + if (cpu.cache.ram_l1_72_addr == lin) { ret.r = cpu.cache.ram_l1_72_val; } + else if (cpu.cache.ram_l1_72_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_72_val; } + else if (cpu.cache.ram_l1_72_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_72_val; } + else if (cpu.cache.ram_l1_72_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_72_val; } + if (cpu.cache.ram_l1_9_addr == lin) { ret.r = cpu.cache.ram_l1_9_val; } + else if (cpu.cache.ram_l1_9_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_9_val; } + else if (cpu.cache.ram_l1_9_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_9_val; } + else if (cpu.cache.ram_l1_9_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_9_val; } + if (cpu.cache.ram_l1_25_addr == lin) { ret.r = cpu.cache.ram_l1_25_val; } + else if (cpu.cache.ram_l1_25_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_25_val; } + else if (cpu.cache.ram_l1_25_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_25_val; } + else if (cpu.cache.ram_l1_25_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_25_val; } + if (cpu.cache.ram_l1_41_addr == lin) { ret.r = cpu.cache.ram_l1_41_val; } + else if (cpu.cache.ram_l1_41_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_41_val; } + else if (cpu.cache.ram_l1_41_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_41_val; } + else if (cpu.cache.ram_l1_41_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_41_val; } + if (cpu.cache.ram_l1_57_addr == lin) { ret.r = cpu.cache.ram_l1_57_val; } + else if (cpu.cache.ram_l1_57_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_57_val; } + else if (cpu.cache.ram_l1_57_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_57_val; } + else if (cpu.cache.ram_l1_57_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_57_val; } + if (cpu.cache.ram_l1_73_addr == lin) { ret.r = cpu.cache.ram_l1_73_val; } + else if (cpu.cache.ram_l1_73_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_73_val; } + else if (cpu.cache.ram_l1_73_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_73_val; } + else if (cpu.cache.ram_l1_73_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_73_val; } + if (cpu.cache.ram_l1_10_addr == lin) { ret.r = cpu.cache.ram_l1_10_val; } + else if (cpu.cache.ram_l1_10_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_10_val; } + else if (cpu.cache.ram_l1_10_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_10_val; } + else if (cpu.cache.ram_l1_10_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_10_val; } + if (cpu.cache.ram_l1_26_addr == lin) { ret.r = cpu.cache.ram_l1_26_val; } + else if (cpu.cache.ram_l1_26_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_26_val; } + else if (cpu.cache.ram_l1_26_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_26_val; } + else if (cpu.cache.ram_l1_26_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_26_val; } + if (cpu.cache.ram_l1_42_addr == lin) { ret.r = cpu.cache.ram_l1_42_val; } + else if (cpu.cache.ram_l1_42_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_42_val; } + else if (cpu.cache.ram_l1_42_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_42_val; } + else if (cpu.cache.ram_l1_42_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_42_val; } + if (cpu.cache.ram_l1_58_addr == lin) { ret.r = cpu.cache.ram_l1_58_val; } + else if (cpu.cache.ram_l1_58_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_58_val; } + else if (cpu.cache.ram_l1_58_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_58_val; } + else if (cpu.cache.ram_l1_58_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_58_val; } + if (cpu.cache.ram_l1_74_addr == lin) { ret.r = cpu.cache.ram_l1_74_val; } + else if (cpu.cache.ram_l1_74_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_74_val; } + else if (cpu.cache.ram_l1_74_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_74_val; } + else if (cpu.cache.ram_l1_74_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_74_val; } + if (cpu.cache.ram_l1_11_addr == lin) { ret.r = cpu.cache.ram_l1_11_val; } + else if (cpu.cache.ram_l1_11_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_11_val; } + else if (cpu.cache.ram_l1_11_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_11_val; } + else if (cpu.cache.ram_l1_11_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_11_val; } + if (cpu.cache.ram_l1_27_addr == lin) { ret.r = cpu.cache.ram_l1_27_val; } + else if (cpu.cache.ram_l1_27_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_27_val; } + else if (cpu.cache.ram_l1_27_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_27_val; } + else if (cpu.cache.ram_l1_27_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_27_val; } + if (cpu.cache.ram_l1_43_addr == lin) { ret.r = cpu.cache.ram_l1_43_val; } + else if (cpu.cache.ram_l1_43_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_43_val; } + else if (cpu.cache.ram_l1_43_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_43_val; } + else if (cpu.cache.ram_l1_43_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_43_val; } + if (cpu.cache.ram_l1_59_addr == lin) { ret.r = cpu.cache.ram_l1_59_val; } + else if (cpu.cache.ram_l1_59_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_59_val; } + else if (cpu.cache.ram_l1_59_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_59_val; } + else if (cpu.cache.ram_l1_59_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_59_val; } + if (cpu.cache.ram_l1_75_addr == lin) { ret.r = cpu.cache.ram_l1_75_val; } + else if (cpu.cache.ram_l1_75_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_75_val; } + else if (cpu.cache.ram_l1_75_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_75_val; } + else if (cpu.cache.ram_l1_75_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_75_val; } + if (cpu.cache.ram_l1_12_addr == lin) { ret.r = cpu.cache.ram_l1_12_val; } + else if (cpu.cache.ram_l1_12_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_12_val; } + else if (cpu.cache.ram_l1_12_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_12_val; } + else if (cpu.cache.ram_l1_12_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_12_val; } + if (cpu.cache.ram_l1_28_addr == lin) { ret.r = cpu.cache.ram_l1_28_val; } + else if (cpu.cache.ram_l1_28_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_28_val; } + else if (cpu.cache.ram_l1_28_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_28_val; } + else if (cpu.cache.ram_l1_28_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_28_val; } + if (cpu.cache.ram_l1_44_addr == lin) { ret.r = cpu.cache.ram_l1_44_val; } + else if (cpu.cache.ram_l1_44_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_44_val; } + else if (cpu.cache.ram_l1_44_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_44_val; } + else if (cpu.cache.ram_l1_44_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_44_val; } + if (cpu.cache.ram_l1_60_addr == lin) { ret.r = cpu.cache.ram_l1_60_val; } + else if (cpu.cache.ram_l1_60_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_60_val; } + else if (cpu.cache.ram_l1_60_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_60_val; } + else if (cpu.cache.ram_l1_60_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_60_val; } + if (cpu.cache.ram_l1_76_addr == lin) { ret.r = cpu.cache.ram_l1_76_val; } + else if (cpu.cache.ram_l1_76_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_76_val; } + else if (cpu.cache.ram_l1_76_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_76_val; } + else if (cpu.cache.ram_l1_76_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_76_val; } + if (cpu.cache.ram_l1_13_addr == lin) { ret.r = cpu.cache.ram_l1_13_val; } + else if (cpu.cache.ram_l1_13_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_13_val; } + else if (cpu.cache.ram_l1_13_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_13_val; } + else if (cpu.cache.ram_l1_13_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_13_val; } + if (cpu.cache.ram_l1_29_addr == lin) { ret.r = cpu.cache.ram_l1_29_val; } + else if (cpu.cache.ram_l1_29_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_29_val; } + else if (cpu.cache.ram_l1_29_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_29_val; } + else if (cpu.cache.ram_l1_29_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_29_val; } + if (cpu.cache.ram_l1_45_addr == lin) { ret.r = cpu.cache.ram_l1_45_val; } + else if (cpu.cache.ram_l1_45_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_45_val; } + else if (cpu.cache.ram_l1_45_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_45_val; } + else if (cpu.cache.ram_l1_45_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_45_val; } + if (cpu.cache.ram_l1_61_addr == lin) { ret.r = cpu.cache.ram_l1_61_val; } + else if (cpu.cache.ram_l1_61_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_61_val; } + else if (cpu.cache.ram_l1_61_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_61_val; } + else if (cpu.cache.ram_l1_61_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_61_val; } + if (cpu.cache.ram_l1_77_addr == lin) { ret.r = cpu.cache.ram_l1_77_val; } + else if (cpu.cache.ram_l1_77_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_77_val; } + else if (cpu.cache.ram_l1_77_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_77_val; } + else if (cpu.cache.ram_l1_77_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_77_val; } + if (cpu.cache.ram_l1_14_addr == lin) { ret.r = cpu.cache.ram_l1_14_val; } + else if (cpu.cache.ram_l1_14_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_14_val; } + else if (cpu.cache.ram_l1_14_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_14_val; } + else if (cpu.cache.ram_l1_14_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_14_val; } + if (cpu.cache.ram_l1_30_addr == lin) { ret.r = cpu.cache.ram_l1_30_val; } + else if (cpu.cache.ram_l1_30_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_30_val; } + else if (cpu.cache.ram_l1_30_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_30_val; } + else if (cpu.cache.ram_l1_30_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_30_val; } + if (cpu.cache.ram_l1_46_addr == lin) { ret.r = cpu.cache.ram_l1_46_val; } + else if (cpu.cache.ram_l1_46_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_46_val; } + else if (cpu.cache.ram_l1_46_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_46_val; } + else if (cpu.cache.ram_l1_46_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_46_val; } + if (cpu.cache.ram_l1_62_addr == lin) { ret.r = cpu.cache.ram_l1_62_val; } + else if (cpu.cache.ram_l1_62_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_62_val; } + else if (cpu.cache.ram_l1_62_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_62_val; } + else if (cpu.cache.ram_l1_62_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_62_val; } + if (cpu.cache.ram_l1_78_addr == lin) { ret.r = cpu.cache.ram_l1_78_val; } + else if (cpu.cache.ram_l1_78_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_78_val; } + else if (cpu.cache.ram_l1_78_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_78_val; } + else if (cpu.cache.ram_l1_78_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_78_val; } + if (cpu.cache.ram_l1_15_addr == lin) { ret.r = cpu.cache.ram_l1_15_val; } + else if (cpu.cache.ram_l1_15_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_15_val; } + else if (cpu.cache.ram_l1_15_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_15_val; } + else if (cpu.cache.ram_l1_15_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_15_val; } + if (cpu.cache.ram_l1_31_addr == lin) { ret.r = cpu.cache.ram_l1_31_val; } + else if (cpu.cache.ram_l1_31_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_31_val; } + else if (cpu.cache.ram_l1_31_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_31_val; } + else if (cpu.cache.ram_l1_31_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_31_val; } + if (cpu.cache.ram_l1_47_addr == lin) { ret.r = cpu.cache.ram_l1_47_val; } + else if (cpu.cache.ram_l1_47_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_47_val; } + else if (cpu.cache.ram_l1_47_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_47_val; } + else if (cpu.cache.ram_l1_47_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_47_val; } + if (cpu.cache.ram_l1_63_addr == lin) { ret.r = cpu.cache.ram_l1_63_val; } + else if (cpu.cache.ram_l1_63_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_63_val; } + else if (cpu.cache.ram_l1_63_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_63_val; } + else if (cpu.cache.ram_l1_63_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_63_val; } + if (cpu.cache.ram_l1_79_addr == lin) { ret.r = cpu.cache.ram_l1_79_val; } + else if (cpu.cache.ram_l1_79_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_79_val; } + else if (cpu.cache.ram_l1_79_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_79_val; } + else if (cpu.cache.ram_l1_79_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_79_val; } + + + if (cpu.cache.ram_l1_last_addr == lin ) { ret.r = cpu.cache.ram_l1_last_val; } + else if (cpu.cache.ram_l1_last_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_last_val; } + else if (cpu.cache.ram_l1_last_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_last_val; } + else if (cpu.cache.ram_l1_last_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_last_val; } + } + } + } + + return ret; +} +#endif + +#endif + +/* + +C# layout: + + #region LOAD + private const int UART_BUFFER_SIZE = 64; + private int[] addr_lin(int lin) { + int[] ret = new int[3]; + ret[2] = lin & 0x3; // c + lin = lin >> 2; + ret[0] = lin % 128; // x + ret[1] = lin / 128; // y + return ret; + } + private uint load_csr__privilege() { return decodePackedData(48, 0, 2); } + private uint load_uart__rbr_thr_ier_iir() { return decodePackedData(48, 0, 3); } + private uint load_uart__lcr_mcr_lsr_scr() { return decodePackedData(49, 0, 0); } + private uint load_uart__thre_ip() { return decodePackedData(49, 0, 1); } + private uint load_uart__interrupting() { return decodePackedData(49, 0, 2); } + private uint load_uart__input_tag() { return decodePackedData(49, 0, 3); } + private uint load_clint__msip() { return decodePackedData(50, 0, 0); } + private uint load_clint__mtimecmp_lo() { return decodePackedData(50, 0, 1); } + private uint load_clint__mtimecmp_hi() { return decodePackedData(50, 0, 2); } + private uint load_clint__mtime_lo() { return decodePackedData(50, 0, 3); } + private uint load_clint__mtime_hi() { return decodePackedData(51, 0, 0); } + private uint load_uart_buffer__ptr() { return decodePackedData(51, 0, 1); } + private uint load_mmu__mode() { return decodePackedData(67, 0, 2); } + private uint load_mmu__ppn() { return decodePackedData(67, 0, 3); } + private uint load_stall() { return decodePackedData(68, 0, 0); } + private uint load_clock() { return decodePackedData(68, 0, 1); } + private uint load_commits() { return decodePackedData(68, 0, 2); } + private uint load_xreg0() { return decodePackedData(68, 0, 3); } + private uint load_xreg1() { return decodePackedData(69, 0, 0); } + private uint load_xreg2() { return decodePackedData(69, 0, 1); } + private uint load_xreg3() { return decodePackedData(69, 0, 2); } + private uint load_xreg4() { return decodePackedData(69, 0, 3); } + private uint load_xreg5() { return decodePackedData(70, 0, 0); } + private uint load_xreg6() { return decodePackedData(70, 0, 1); } + private uint load_xreg7() { return decodePackedData(70, 0, 2); } + private uint load_xreg8() { return decodePackedData(70, 0, 3); } + private uint load_xreg9() { return decodePackedData(71, 0, 0); } + private uint load_xreg10() { return decodePackedData(71, 0, 1); } + private uint load_xreg11() { return decodePackedData(71, 0, 2); } + private uint load_xreg12() { return decodePackedData(71, 0, 3); } + private uint load_xreg13() { return decodePackedData(72, 0, 0); } + private uint load_xreg14() { return decodePackedData(72, 0, 1); } + private uint load_xreg15() { return decodePackedData(72, 0, 2); } + private uint load_xreg16() { return decodePackedData(72, 0, 3); } + private uint load_xreg17() { return decodePackedData(73, 0, 0); } + private uint load_xreg18() { return decodePackedData(73, 0, 1); } + private uint load_xreg19() { return decodePackedData(73, 0, 2); } + private uint load_xreg20() { return decodePackedData(73, 0, 3); } + private uint load_xreg21() { return decodePackedData(74, 0, 0); } + private uint load_xreg22() { return decodePackedData(74, 0, 1); } + private uint load_xreg23() { return decodePackedData(74, 0, 2); } + private uint load_xreg24() { return decodePackedData(74, 0, 3); } + private uint load_xreg25() { return decodePackedData(75, 0, 0); } + private uint load_xreg26() { return decodePackedData(75, 0, 1); } + private uint load_xreg27() { return decodePackedData(75, 0, 2); } + private uint load_xreg28() { return decodePackedData(75, 0, 3); } + private uint load_xreg29() { return decodePackedData(76, 0, 0); } + private uint load_xreg30() { return decodePackedData(76, 0, 1); } + private uint load_xreg31() { return decodePackedData(76, 0, 2); } + private uint load_pc() { return decodePackedData(76, 0, 3); } + private uint load_reservation_en() { return decodePackedData(77, 0, 0); } + private uint load_reservation_addr() { return decodePackedData(77, 0, 1); } + private uint load_memop_src_v() { return decodePackedData(77, 0, 2); } + private uint load_memop_dst_v() { return decodePackedData(77, 0, 3); } + private uint load_memop_src_p() { return decodePackedData(78, 0, 0); } + private uint load_memop_dst_p() { return decodePackedData(78, 0, 1); } + private uint load_memop_n() { return decodePackedData(78, 0, 2); } + private uint load_stall_count() { return decodePackedData(78, 0, 3); } + private uint load_trap_count() { return decodePackedData(79, 0, 0); } + private uint load_debug_do_tick() { return decodePackedData(79, 0, 1); } + private uint load_debug_last_ins() { return decodePackedData(79, 0, 2); } + private uint load_debug_last_stall() { return decodePackedData(79, 0, 3); } + private uint load_debug_arb_0() { return decodePackedData(80, 0, 0); } + private uint load_csr(int addr) { + int lin = (addr >> 2) + 324; + return decodePackedData(lin % 128, lin / 128, addr & 0x3); + } + private uint getUartBuffer(int idx) { + + int lin = idx + 206; + int[] acc = addr_lin(lin); + return decodePackedData(acc[0], acc[1], acc[2]); + } + #endregion + +*/ diff --git a/_Nix/rvc/src/types.h.meta b/_Nix/rvc/src/types.h.meta new file mode 100755 index 00000000..f53a2346 --- /dev/null +++ b/_Nix/rvc/src/types.h.meta @@ -0,0 +1,27 @@ +fileFormatVersion: 2 +guid: eb7fff8ba52d5004685e3b9bea5b8f3b +PluginImporter: + externalObjects: {} + serializedVersion: 2 + iconMap: {} + executionOrder: {} + defineConstraints: [] + isPreloaded: 0 + isOverridable: 0 + isExplicitlyReferenced: 0 + validateReferences: 1 + platformData: + - first: + Any: + second: + enabled: 1 + settings: {} + - first: + Editor: Editor + second: + enabled: 0 + settings: + DefaultValueInitialized: true + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/types.h.pp b/_Nix/rvc/src/types.h.pp new file mode 100755 index 00000000..999ce4f3 --- /dev/null +++ b/_Nix/rvc/src/types.h.pp @@ -0,0 +1,564 @@ +#ifndef TYPES_H +#define TYPES_H + + + +#define STALL_EXIT_CALL 1 +#define STALL_CSR_CACHE 2 +#define STALL_MEM_CACHE_L1 3 +#define STALL_MEM_CACHE_L2 4 +#define STALL_ILLEGAL_ENTRY_POINT 5 +#define STALL_UART 6 +#define STALL_FENCE 7 +#define STALL_MEMOP_COPY 8 + +{$name} = { + name => $name, + type => $type, + addr => $addr, + def => $def, + }; + $addr++; + if ($name =~ m/.*\.(.*)$/) { + print "$type $1;"; + } else { + print "$type $name;"; + } +}; + +my $d = sub { + if (0) { # enable for DEBUG + $s->(@_); + } +}; + +?> + +// STRUCT TYPES +typedef struct { + ("uint", "cache.csr_cache_${i}_addr", 0xffffffff); + print " "; + $s->("uint", "cache.csr_cache_${i}_val", 0xdeadc7de); + print "\n "; + } + + for my $i (0..$ram_l1_set_max) { + for my $j (0..$ram_l1_line_max) { + my $ci = $i + $j * ($ram_l1_set_max + 1); + $s->("uint", "cache.ram_l1_${ci}_addr", 0xffffffff); + print " "; + $s->("uint", "cache.ram_l1_${ci}_val", 0xdeadc8de); + print "\n "; + } + } + + $s->("uint", "cache.ram_l1_last_addr", 0xffffffff); + $s->("uint", "cache.ram_l1_last_val", 0xdeadc9de); + ?> +} cache_t; + +typedef struct { + ("uint", "csr.privilege"); ?> +} csr_state; + +typedef struct { + ("uint", "uart.rbr_thr_ier_iir"); ?> + ("uint", "uart.lcr_mcr_lsr_scr"); ?> + ("bool", "uart.thre_ip"); ?> + ("bool", "uart.interrupting"); ?> + ("uint", "uart.input_tag"); ?> +} uart_state; + +typedef struct { + ("bool", "clint.msip"); ?> + ("uint", "clint.mtimecmp_lo"); ?> + ("uint", "clint.mtimecmp_hi"); ?> + ("uint", "clint.mtime_lo"); ?> + ("uint", "clint.mtime_hi"); ?> +} clint_state; + +typedef struct { + ("uint", "uart_buffer.ptr"); ?> + ("uint", "uart_buffer.buf${i}"); + print "\n "; + } + ?> +} uart_buffer; + +typedef struct { + ("uint", "mmu.mode"); ?> + ("uint", "mmu.ppn"); ?> +} mmu_state; + +typedef struct { + ("uint", "stall"); ?> + ("uint", "clock"); ?> + ("uint", "commits"); ?> + ("uint", "xreg$i"); + print "\n "; + } ?> + ("uint", "pc"); ?> + csr_state csr; + clint_state clint; + uart_state uart; + uart_buffer uart_buffer; + mmu_state mmu; + + ("bool", "reservation_en"); ?> + ("uint", "reservation_addr"); ?> + + ("uint", "memop_src_v"); ?> + ("uint", "memop_dst_v"); ?> + ("uint", "memop_src_p"); ?> + ("uint", "memop_dst_p"); ?> + ("uint", "memop_n"); ?> + + ("uint", "stall_count"); ?> + ("uint", "trap_count"); ?> + + ("uint", "debug_do_tick"); ?> + ("uint", "debug_last_ins"); ?> + ("uint", "debug_last_stall"); ?> + ("uint", "debug_csr_val"); ?> + ("uint", "debug_mem_val"); ?> + + ("uint", "debug_arb_0"); ?> + ("uint", "debug_arb_1"); ?> + ("uint", "debug_arb_2"); ?> + ("uint", "debug_arb_3"); ?> + ("uint", "debug_arb_4"); ?> + ("uint", "debug_arb_5"); ?> + ("uint", "debug_arb_6"); ?> + ("uint", "debug_arb_7"); ?> + + cache_t cache; +} cpu_t; + +typedef struct { + bool en; + bool irq; + uint type; + uint value; +} trap; + +typedef struct { + uint write_reg; + uint write_val; + uint pc_val; + uint csr_write; + uint csr_val; + uint mem_wr_addr; + uint mem_wr_value; + uint mem_wr_size; + trap trap; +} ins_ret; + +// GLOBAL STATICS +static cpu_t cpu; + +// TYPE HELPERS +ins_ret ins_ret_noop() { + ins_ret ret = (ins_ret)0; + ret.pc_val = cpu.pc + 4; + return ret; +} + +uint sign_extend(uint x, uint b) { + uint m = ((uint)1) << (b - 1); + return (x ^ m) - m; +} + +uint xreg(uint i) { + #define C(x) case x: return cpu.xreg##x; + if (i < 16) { + [flatten] + switch (i) { + C(0) C(1) C(2) C(3) + C(4) C(5) C(6) C(7) + C(8) C(9) C(10) C(11) + C(12) C(13) C(14) C(15) + } + } else { + [flatten] + switch (i) { + C(16) C(17) C(18) C(19) + C(20) C(21) C(22) C(23) + C(24) C(25) C(26) C(27) + C(28) C(29) C(30) C(31) + } + } + return 0xdeadc0de; + #undef C +} + +// ENCODE/DECODE LOGIC (state serialization into self texture) + +> 2; + return { + x => $lin % $width, + y => int($lin / $width), + c => $col, + }; +}; + +my $addr_id = sub { + my ($lin) = @_; + my $a = $addr_lin->($lin); + return $a->{x} | ($a->{y} << 16); +}; + +my $rev = {}; +for my $prop (keys %$state) { + my $aid = $addr_id->($state->{$prop}->{addr}); + $rev->{$aid}->{$prop} = $state->{$prop}; +} + +?> + +void decode(uint udonUartPtr) { + cpu = (cpu_t)0; + +{$a}->{addr} <=> $state->{$b}->{addr} } keys %$state) { + my $n = $state->{$prop}->{name}; + my $a = $addr_lin->($state->{$prop}->{addr}); + my $t = $state->{$prop}->{type}; + + if (defined($state->{$prop}->{def})) { + print " cpu.$n = $t($state->{$prop}->{def});\n"; + } else { + print " cpu.$n = $t(idx_uint4(STATE_TEX[uint2($a->{x}, $a->{y})], $a->{c}));\n"; + } + } +?> + + if (cpu.stall == STALL_UART && udonUartPtr == cpu.uart_buffer.ptr) { + cpu.stall = 0; + } +} + +#ifdef PASS_COMMIT +void decode_for_commit() { + cpu = (cpu_t)0; + +{$a}->{addr} <=> $state->{$b}->{addr} } keys %$state) { + my $n = $state->{$prop}->{name}; + my $a = $addr_lin->($state->{$prop}->{addr}); + my $t = $state->{$prop}->{type}; + + # for committing only the L1 RAM and CSR caches are important + # (not anymore?) + # next if !($prop =~ m/cache\.ram/ || $prop =~ m/cache\.csr/); + + print " cpu.$n = $t(idx_uint4(STATE_TEX[uint2($a->{x}, $a->{y})], $a->{c}));\n"; + } +?> +} +#endif + +bool pixel_has_state(uint2 pos) { + ($addr); + ?> + return pos.y < {y} ?> || (pos.y == {y} ?> && pos.x <= {x} ?>); +} + + + +/* void set_debug_arb() { */ +/* */ +/* cpu.debug_arb_ = cpu.xreg ^ */ +/* cpu.xreg ^ */ +/* cpu.xreg ^ */ +/* cpu.xreg; */ +/* */ +/* } */ + +uint4 encode(uint2 pos) { + // fallback is passthrough + uint4 ret = STATE_TEX[pos]; + + uint pos_id = pos.x | (pos.y << 16); + + switch (pos_id) { +{$aid}}) { + my $p = $rev->{$aid}->{$prop}; + my $c = $addr_lin->($p->{addr})->{c}; + $c = ("r", "g", "b", "a")[$c]; + if ($prop eq "stall") { + print " ret.$c = uint(cpu.$p->{name} == STALL_CSR_CACHE ? 0 : (cpu.$p->{name} == STALL_MEM_CACHE_L1 ? 0 : cpu.$p->{name}));\n"; + } elsif ($prop eq "debug_last_stall") { + print " ret.$c = uint(cpu.stall);\n"; + } else { + print " ret.$c = uint(cpu.$p->{name});\n"; + } + } + print " return ret;\n"; + } +?> + } + + return ret; +} + +uint tex_get_csr(uint addr) { + uint lin = (addr >> 2) + ; + uint idx = addr & 0x3; + return idx_uint4(STATE_TEX[uint2(lin % , lin / )], idx); +} + + + +// Memory operations (should be in mem.h but cyclic dependencies...) + +// Basic bloom filter to slightly optimize memory caching +#ifdef PASS_TICK +static uint mem_cache_bloom = 0; +#else +static uint mem_cache_bloom = 0xffffffff; +#endif + +[noinline] // I'm pretty sure this does nothing, but see it as a prayer to the compiler gods +uint mem_get_cached_or_tex(uint addr) { + // query L1 cache + if ((addr & mem_cache_bloom) != addr) { /* not cached */ } + else { + [forcecase] + switch (RAM_L1_TAG(addr)) { + + } + + if (cpu.cache.ram_l1_last_addr == addr) { + return cpu.cache.ram_l1_last_val; + } + } + + uint idx = (addr >> 2) & 0x3; + addr >>= 4; + + uint4 raw = STATE_TEX[RAM_ADDR(addr)]; + return idx_uint4(raw, idx); +} + + +#ifdef PASS_COMMIT +uint4 commit(uint2 pos) { + if (pos.y < && pos.x >= ) { + return (uint4)0; + } + + // fallback is passthrough + uint4 ret = STATE_TEX[pos]; + + uint pos_id = pos.x | (pos.y << 16); + + // increment commits + if (!_Init && pos_id == ($state->{commits}->{addr}) ?>) { + ++ret.($state->{commits}->{addr})->{c}; $c = ("r", "g", "b", "a")[$c]; print $c; ?>; + } + + // clear stall + if (pos_id == ($state->{stall}->{addr}) ?>) { + [flatten] + switch (ret.($state->{stall}->{addr})->{c}; $c2 = ("r", "g", "b", "a")[$c2]; print $c2; ?>) { + case STALL_MEM_CACHE_L2: + ret. = 0; + break; + case STALL_FENCE: + ret. = 0; + break; + case STALL_MEMOP_COPY: // will be handled now, so we can unset + ret. = 0; + break; + } + } + + uint s_lin = pos.x + pos.y * ; + + // CSR area + if (s_lin >= && s_lin < ) { + uint addr = s_lin - ; + addr <<= 2; + + } + + // RAM + if (pos.y >= ) { + uint2 pos_ram = uint2(pos.x, pos.y - ); + uint lin = pos_ram.x + pos_ram.y * ; + + if (_Init) { + // init main memory from texture + uint2 ram_dim; + _Data_RAM_A.GetDimensions(ram_dim.x, ram_dim.y); + + // TODO: something feels off here... off by one, you might say... + uint2 pos2 = uint2(lin % ram_dim.x, lin / ram_dim.x); + pos2.y = ram_dim.y - pos2.y - 1; + + if (pos2.y >= ram_dim.y) { + // zero unset memory + ret = uint4(0, 0, 0, 0); + } else { + uint r = unpack_raw_float4(_Data_RAM_R[pos2]); + uint g = unpack_raw_float4(_Data_RAM_G[pos2]); + uint b = unpack_raw_float4(_Data_RAM_B[pos2]); + uint a = unpack_raw_float4(_Data_RAM_A[pos2]); + ret = uint4(r, g, b, a); + } + } else { + lin <<= 4; + + if (cpu.stall == STALL_MEMOP_COPY && + (lin + (3 << 2)) >= cpu.memop_dst_p && + lin < (cpu.memop_dst_p + cpu.memop_n)) + { + // we've found ourselves in a position for a memcpy, ignore cache and perform it + // (a memop is always the last instruction in a commit cycle, so we know we have + // higher priority than the L1 cache) + [loop] + for (uint icp = 0; icp < 4; icp++) { + uint lin_word = lin + (icp << 2); + if (lin_word >= cpu.memop_dst_p && + lin_word < (cpu.memop_dst_p + cpu.memop_n)) + { + uint offset = cpu.memop_dst_p - lin_word; + uint src = cpu.memop_src_p + offset; + uint transfer = mem_get_cached_or_tex(src); + switch (icp) { + case 0: + ret.r = transfer; + break; + case 1: + ret.g = transfer; + break; + case 2: + ret.b = transfer; + break; + case 3: + ret.a = transfer; + break; + } + } + } + } + else + { + // write back L1 cache + + + if (cpu.cache.ram_l1_last_addr == lin ) { ret.r = cpu.cache.ram_l1_last_val; } + else if (cpu.cache.ram_l1_last_addr == lin + (1 << 2)) { ret.g = cpu.cache.ram_l1_last_val; } + else if (cpu.cache.ram_l1_last_addr == lin + (2 << 2)) { ret.b = cpu.cache.ram_l1_last_val; } + else if (cpu.cache.ram_l1_last_addr == lin + (3 << 2)) { ret.a = cpu.cache.ram_l1_last_val; } + } + } + } + + return ret; +} +#endif + +#endif + +/* + +C# layout: + + #region LOAD + private const int UART_BUFFER_SIZE = ; + private int[] addr_lin(int lin) { + int[] ret = new int[3]; + ret[2] = lin & 0x3; // c + lin = lin >> 2; + ret[0] = lin % ; // x + ret[1] = lin / ; // y + return ret; + } +{$a}->{addr} <=> $state->{$b}->{addr} } keys %$state) { + my $n = $state->{$prop}->{name}; + my $a = $addr_lin->($state->{$prop}->{addr}); + my $t = $state->{$prop}->{type}; + + if (!defined($state->{$prop}->{def})) { + my $fname = $prop; + next if $prop =~ m/uart_buffer\.buf/; + $fname =~ s/\./__/; + print " private uint load_$fname() { return decodePackedData($a->{x}, $a->{y}, $a->{c}); }\n"; + } +} +?> private uint load_csr(int addr) { + int lin = (addr >> 2) + ; + return decodePackedData(lin % , lin / , addr & 0x3); + } + private uint getUartBuffer(int idx) { + {"uart_buffer.buf0"}->{addr}; + my $uart_a = $addr_lin->($uart_start); + ?> + int lin = idx + ; + int[] acc = addr_lin(lin); + return decodePackedData(acc[0], acc[1], acc[2]); + } + #endregion + +*/ diff --git a/_Nix/rvc/src/types.h.pp.meta b/_Nix/rvc/src/types.h.pp.meta new file mode 100755 index 00000000..5a9fa260 --- /dev/null +++ b/_Nix/rvc/src/types.h.pp.meta @@ -0,0 +1,7 @@ +fileFormatVersion: 2 +guid: f53fce459266a0748beb81930fbf3351 +DefaultImporter: + externalObjects: {} + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/uart.h b/_Nix/rvc/src/uart.h new file mode 100755 index 00000000..d0c2c138 --- /dev/null +++ b/_Nix/rvc/src/uart.h @@ -0,0 +1,160 @@ +#ifndef UART_H +#define UART_H + + + +/* must match set/line count above, shift by two to ignore byte offset */ +#define RAM_L1_TAG(a) ((a >> 2) & 0xf) + + +#define SHIFT_RBR 0 +#define SHIFT_THR 8 +#define SHIFT_IER 16 +#define SHIFT_IIR 24 +#define SHIFT_LCR 0 +#define SHIFT_MCR 8 +#define SHIFT_LSR 16 +#define SHIFT_SCR 24 + +#define UART_GET1(x) ((cpu.uart.rbr_thr_ier_iir >> SHIFT_##x) & 0xff) +#define UART_GET2(x) ((cpu.uart.lcr_mcr_lsr_scr >> SHIFT_##x) & 0xff) + +#define UART_SET1(x, val) cpu.uart.rbr_thr_ier_iir = (cpu.uart.rbr_thr_ier_iir & (~(0xff << SHIFT_##x))) | (val << SHIFT_##x) +#define UART_SET2(x, val) cpu.uart.lcr_mcr_lsr_scr = (cpu.uart.lcr_mcr_lsr_scr & (~(0xff << SHIFT_##x))) | (val << SHIFT_##x) + +#define IER_RXINT_BIT 0x1 +#define IER_THREINT_BIT 0x2 + +#define IIR_THR_EMPTY 0x2 +#define IIR_RD_AVAILABLE 0x4 +#define IIR_NO_INTERRUPT 0x7 + +#define LSR_DATA_AVAILABLE 0x1 +#define LSR_THR_EMPTY 0x20 + +void uart_update_iir() { + bool rx_ip = (UART_GET1(IER) & IER_RXINT_BIT) != 0 && UART_GET1(RBR) != 0; + bool thre_ip = (UART_GET1(IER) & IER_THREINT_BIT) != 0 && UART_GET1(THR) == 0; + UART_SET1(IIR, (rx_ip ? IIR_RD_AVAILABLE : (thre_ip ? IIR_THR_EMPTY : IIR_NO_INTERRUPT))); +} + +void put_char_to_udon(uint c) { + cpu.uart_buffer.ptr++; + if (cpu.uart_buffer.ptr == 64) { + cpu.uart_buffer.ptr = 0; + } + [branch] + switch (cpu.uart_buffer.ptr) { +case 0: cpu.uart_buffer.buf0 = c; break; +case 1: cpu.uart_buffer.buf1 = c; break; +case 2: cpu.uart_buffer.buf2 = c; break; +case 3: cpu.uart_buffer.buf3 = c; break; +case 4: cpu.uart_buffer.buf4 = c; break; +case 5: cpu.uart_buffer.buf5 = c; break; +case 6: cpu.uart_buffer.buf6 = c; break; +case 7: cpu.uart_buffer.buf7 = c; break; +case 8: cpu.uart_buffer.buf8 = c; break; +case 9: cpu.uart_buffer.buf9 = c; break; +case 10: cpu.uart_buffer.buf10 = c; break; +case 11: cpu.uart_buffer.buf11 = c; break; +case 12: cpu.uart_buffer.buf12 = c; break; +case 13: cpu.uart_buffer.buf13 = c; break; +case 14: cpu.uart_buffer.buf14 = c; break; +case 15: cpu.uart_buffer.buf15 = c; break; +case 16: cpu.uart_buffer.buf16 = c; break; +case 17: cpu.uart_buffer.buf17 = c; break; +case 18: cpu.uart_buffer.buf18 = c; break; +case 19: cpu.uart_buffer.buf19 = c; break; +case 20: cpu.uart_buffer.buf20 = c; break; +case 21: cpu.uart_buffer.buf21 = c; break; +case 22: cpu.uart_buffer.buf22 = c; break; +case 23: cpu.uart_buffer.buf23 = c; break; +case 24: cpu.uart_buffer.buf24 = c; break; +case 25: cpu.uart_buffer.buf25 = c; break; +case 26: cpu.uart_buffer.buf26 = c; break; +case 27: cpu.uart_buffer.buf27 = c; break; +case 28: cpu.uart_buffer.buf28 = c; break; +case 29: cpu.uart_buffer.buf29 = c; break; +case 30: cpu.uart_buffer.buf30 = c; break; +case 31: cpu.uart_buffer.buf31 = c; break; +case 32: cpu.uart_buffer.buf32 = c; break; +case 33: cpu.uart_buffer.buf33 = c; break; +case 34: cpu.uart_buffer.buf34 = c; break; +case 35: cpu.uart_buffer.buf35 = c; break; +case 36: cpu.uart_buffer.buf36 = c; break; +case 37: cpu.uart_buffer.buf37 = c; break; +case 38: cpu.uart_buffer.buf38 = c; break; +case 39: cpu.uart_buffer.buf39 = c; break; +case 40: cpu.uart_buffer.buf40 = c; break; +case 41: cpu.uart_buffer.buf41 = c; break; +case 42: cpu.uart_buffer.buf42 = c; break; +case 43: cpu.uart_buffer.buf43 = c; break; +case 44: cpu.uart_buffer.buf44 = c; break; +case 45: cpu.uart_buffer.buf45 = c; break; +case 46: cpu.uart_buffer.buf46 = c; break; +case 47: cpu.uart_buffer.buf47 = c; break; +case 48: cpu.uart_buffer.buf48 = c; break; +case 49: cpu.uart_buffer.buf49 = c; break; +case 50: cpu.uart_buffer.buf50 = c; break; +case 51: cpu.uart_buffer.buf51 = c; break; +case 52: cpu.uart_buffer.buf52 = c; break; +case 53: cpu.uart_buffer.buf53 = c; break; +case 54: cpu.uart_buffer.buf54 = c; break; +case 55: cpu.uart_buffer.buf55 = c; break; +case 56: cpu.uart_buffer.buf56 = c; break; +case 57: cpu.uart_buffer.buf57 = c; break; +case 58: cpu.uart_buffer.buf58 = c; break; +case 59: cpu.uart_buffer.buf59 = c; break; +case 60: cpu.uart_buffer.buf60 = c; break; +case 61: cpu.uart_buffer.buf61 = c; break; +case 62: cpu.uart_buffer.buf62 = c; break; +case 63: cpu.uart_buffer.buf63 = c; break; + + } + + // check for overflow on Udon side, stall if necessary + if (cpu.uart_buffer.ptr == _UdonUARTPtr - 1 || + (cpu.uart_buffer.ptr == 63 && _UdonUARTPtr == 0)) + { + cpu.stall = STALL_UART; + } +} + +void uart_tick() { + bool rx_ip = false; + + if ((cpu.clock % 128) == 0) { + if (cpu.uart.input_tag != _UdonUARTInTag && UART_GET1(RBR) == 0) { + cpu.uart.input_tag = _UdonUARTInTag; + if (_UdonUARTInChar != 0) { + UART_SET1(RBR, _UdonUARTInChar); + cpu.debug_arb_0 = _UdonUARTInChar; + UART_SET2(LSR, (UART_GET2(LSR) | LSR_DATA_AVAILABLE)); + uart_update_iir(); + if ((UART_GET1(IER) & IER_RXINT_BIT) != 0) { + rx_ip = true; + } + } + } + } + + uint thr = UART_GET1(THR); + if ((cpu.clock % 16) == 0 && thr != 0) { + put_char_to_udon(thr); + UART_SET1(THR, 0); + UART_SET2(LSR, (UART_GET2(LSR) | LSR_THR_EMPTY)); + uart_update_iir(); + if ((UART_GET1(IER) & IER_THREINT_BIT) != 0) { + cpu.uart.thre_ip = true; + } + } + + if (!cpu.uart.interrupting && (cpu.uart.thre_ip || rx_ip)) { + cpu.uart.interrupting = true; + cpu.uart.thre_ip = false; + } else { + cpu.uart.interrupting = false; + } +} + +#endif diff --git a/_Nix/rvc/src/uart.h.meta b/_Nix/rvc/src/uart.h.meta new file mode 100755 index 00000000..2cc9a88c --- /dev/null +++ b/_Nix/rvc/src/uart.h.meta @@ -0,0 +1,27 @@ +fileFormatVersion: 2 +guid: 725abf4d6e615cd45932270ed221b0bf +PluginImporter: + externalObjects: {} + serializedVersion: 2 + iconMap: {} + executionOrder: {} + defineConstraints: [] + isPreloaded: 0 + isOverridable: 0 + isExplicitlyReferenced: 0 + validateReferences: 1 + platformData: + - first: + Any: + second: + enabled: 1 + settings: {} + - first: + Editor: Editor + second: + enabled: 0 + settings: + DefaultValueInitialized: true + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/rvc/src/uart.h.pp b/_Nix/rvc/src/uart.h.pp new file mode 100755 index 00000000..d1e9d51c --- /dev/null +++ b/_Nix/rvc/src/uart.h.pp @@ -0,0 +1,92 @@ +#ifndef UART_H +#define UART_H + + + +#define SHIFT_RBR 0 +#define SHIFT_THR 8 +#define SHIFT_IER 16 +#define SHIFT_IIR 24 +#define SHIFT_LCR 0 +#define SHIFT_MCR 8 +#define SHIFT_LSR 16 +#define SHIFT_SCR 24 + +#define UART_GET1(x) ((cpu.uart.rbr_thr_ier_iir >> SHIFT_##x) & 0xff) +#define UART_GET2(x) ((cpu.uart.lcr_mcr_lsr_scr >> SHIFT_##x) & 0xff) + +#define UART_SET1(x, val) cpu.uart.rbr_thr_ier_iir = (cpu.uart.rbr_thr_ier_iir & (~(0xff << SHIFT_##x))) | (val << SHIFT_##x) +#define UART_SET2(x, val) cpu.uart.lcr_mcr_lsr_scr = (cpu.uart.lcr_mcr_lsr_scr & (~(0xff << SHIFT_##x))) | (val << SHIFT_##x) + +#define IER_RXINT_BIT 0x1 +#define IER_THREINT_BIT 0x2 + +#define IIR_THR_EMPTY 0x2 +#define IIR_RD_AVAILABLE 0x4 +#define IIR_NO_INTERRUPT 0x7 + +#define LSR_DATA_AVAILABLE 0x1 +#define LSR_THR_EMPTY 0x20 + +void uart_update_iir() { + bool rx_ip = (UART_GET1(IER) & IER_RXINT_BIT) != 0 && UART_GET1(RBR) != 0; + bool thre_ip = (UART_GET1(IER) & IER_THREINT_BIT) != 0 && UART_GET1(THR) == 0; + UART_SET1(IIR, (rx_ip ? IIR_RD_AVAILABLE : (thre_ip ? IIR_THR_EMPTY : IIR_NO_INTERRUPT))); +} + +void put_char_to_udon(uint c) { + cpu.uart_buffer.ptr++; + if (cpu.uart_buffer.ptr == ) { + cpu.uart_buffer.ptr = 0; + } + [branch] + switch (cpu.uart_buffer.ptr) { + + } + + // check for overflow on Udon side, stall if necessary + if (cpu.uart_buffer.ptr == _UdonUARTPtr - 1 || + (cpu.uart_buffer.ptr == && _UdonUARTPtr == 0)) + { + cpu.stall = STALL_UART; + } +} + +void uart_tick() { + bool rx_ip = false; + + if ((cpu.clock % 128) == 0) { + if (cpu.uart.input_tag != _UdonUARTInTag && UART_GET1(RBR) == 0) { + cpu.uart.input_tag = _UdonUARTInTag; + if (_UdonUARTInChar != 0) { + UART_SET1(RBR, _UdonUARTInChar); + cpu.debug_arb_0 = _UdonUARTInChar; + UART_SET2(LSR, (UART_GET2(LSR) | LSR_DATA_AVAILABLE)); + uart_update_iir(); + if ((UART_GET1(IER) & IER_RXINT_BIT) != 0) { + rx_ip = true; + } + } + } + } + + uint thr = UART_GET1(THR); + if ((cpu.clock % 16) == 0 && thr != 0) { + put_char_to_udon(thr); + UART_SET1(THR, 0); + UART_SET2(LSR, (UART_GET2(LSR) | LSR_THR_EMPTY)); + uart_update_iir(); + if ((UART_GET1(IER) & IER_THREINT_BIT) != 0) { + cpu.uart.thre_ip = true; + } + } + + if (!cpu.uart.interrupting && (cpu.uart.thre_ip || rx_ip)) { + cpu.uart.interrupting = true; + cpu.uart.thre_ip = false; + } else { + cpu.uart.interrupting = false; + } +} + +#endif diff --git a/_Nix/rvc/src/uart.h.pp.meta b/_Nix/rvc/src/uart.h.pp.meta new file mode 100755 index 00000000..8529418c --- /dev/null +++ b/_Nix/rvc/src/uart.h.pp.meta @@ -0,0 +1,7 @@ +fileFormatVersion: 2 +guid: 917039853697cb845a4209412ad8aa80 +DefaultImporter: + externalObjects: {} + userData: + assetBundleName: + assetBundleVariant: diff --git a/_Nix/vm_mat.mat b/_Nix/vm_mat.mat new file mode 100755 index 00000000..074efe9e --- /dev/null +++ b/_Nix/vm_mat.mat @@ -0,0 +1,157 @@ +%YAML 1.1 +%TAG !u! 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