rvc/.gitignore

compile_commands.json
.ccls-cache
elfy/.ccls-cache
rvc
*.o
elfy/target
elfy/Cargo.lock
rust_payload/target
rust_payload/Cargo.lock
fw_payload.*
*.dtb
*.bmp
*.bin
*.elf
*.img
initial commit passes all RV32IM tests (run './test.sh all') instructions.txt is extracted from takahirox/riscv-rust 2021-05-28 13:08:21 +00:00			`compile_commands.json`
			`.ccls-cache`
			`elfy/.ccls-cache`
			`rvc`
			`*.o`
			`elfy/target`
			`elfy/Cargo.lock`
Add rust_payload and fixes to allow running it as supervisor Note that the 'riscv32ima-unknown-none-elf' target is not available by default in rustc, you need a patched version. I'm also pretty sure just converting the ELF binary to raw using objdump messes with stack and heap addresses, but it seems to work fine for now. 2021-06-09 16:38:46 +00:00			`rust_payload/target`
			`rust_payload/Cargo.lock`
implement UART, CLINT, device tree, opensbi build ...plus some comfort improvements, more testing. This now successfully boots OpenSBI when built like specified in the Makefile! 2021-06-03 20:42:59 +00:00			`fw_payload.*`
			`*.dtb`
add bare-metal test image and update .gitignore 2021-08-17 07:37:49 +00:00			`*.bmp`
			`*.bin`
			`*.elf`
			`*.img`