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fff7fb0b2d
The binary GCD algorithm is based on the following facts:
1. If a and b are all evens, then gcd(a,b) = 2 * gcd(a/2, b/2)
2. If a is even and b is odd, then gcd(a,b) = gcd(a/2, b)
3. If a and b are all odds, then gcd(a,b) = gcd((a-b)/2, b) = gcd((a+b)/2, b)
Even on x86 machines with reasonable division hardware, the binary
algorithm runs about 25% faster (80% the execution time) than the
division-based Euclidian algorithm.
On platforms like Alpha and ARMv6 where division is a function call to
emulation code, it's even more significant.
There are two variants of the code here, depending on whether a fast
__ffs (find least significant set bit) instruction is available. This
allows the unpredictable branches in the bit-at-a-time shifting loop to
be eliminated.
If fast __ffs is not available, the "even/odd" GCD variant is used.
I use the following code to benchmark:
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
#define swap(a, b) \
do { \
a ^= b; \
b ^= a; \
a ^= b; \
} while (0)
unsigned long gcd0(unsigned long a, unsigned long b)
{
unsigned long r;
if (a < b) {
swap(a, b);
}
if (b == 0)
return a;
while ((r = a % b) != 0) {
a = b;
b = r;
}
return b;
}
unsigned long gcd1(unsigned long a, unsigned long b)
{
unsigned long r = a | b;
if (!a || !b)
return r;
b >>= __builtin_ctzl(b);
for (;;) {
a >>= __builtin_ctzl(a);
if (a == b)
return a << __builtin_ctzl(r);
if (a < b)
swap(a, b);
a -= b;
}
}
unsigned long gcd2(unsigned long a, unsigned long b)
{
unsigned long r = a | b;
if (!a || !b)
return r;
r &= -r;
while (!(b & r))
b >>= 1;
for (;;) {
while (!(a & r))
a >>= 1;
if (a == b)
return a;
if (a < b)
swap(a, b);
a -= b;
a >>= 1;
if (a & r)
a += b;
a >>= 1;
}
}
unsigned long gcd3(unsigned long a, unsigned long b)
{
unsigned long r = a | b;
if (!a || !b)
return r;
b >>= __builtin_ctzl(b);
if (b == 1)
return r & -r;
for (;;) {
a >>= __builtin_ctzl(a);
if (a == 1)
return r & -r;
if (a == b)
return a << __builtin_ctzl(r);
if (a < b)
swap(a, b);
a -= b;
}
}
unsigned long gcd4(unsigned long a, unsigned long b)
{
unsigned long r = a | b;
if (!a || !b)
return r;
r &= -r;
while (!(b & r))
b >>= 1;
if (b == r)
return r;
for (;;) {
while (!(a & r))
a >>= 1;
if (a == r)
return r;
if (a == b)
return a;
if (a < b)
swap(a, b);
a -= b;
a >>= 1;
if (a & r)
a += b;
a >>= 1;
}
}
static unsigned long (*gcd_func[])(unsigned long a, unsigned long b) = {
gcd0, gcd1, gcd2, gcd3, gcd4,
};
#define TEST_ENTRIES (sizeof(gcd_func) / sizeof(gcd_func[0]))
#if defined(__x86_64__)
#define rdtscll(val) do { \
unsigned long __a,__d; \
__asm__ __volatile__("rdtsc" : "=a" (__a), "=d" (__d)); \
(val) = ((unsigned long long)__a) | (((unsigned long long)__d)<<32); \
} while(0)
static unsigned long long benchmark_gcd_func(unsigned long (*gcd)(unsigned long, unsigned long),
unsigned long a, unsigned long b, unsigned long *res)
{
unsigned long long start, end;
unsigned long long ret;
unsigned long gcd_res;
rdtscll(start);
gcd_res = gcd(a, b);
rdtscll(end);
if (end >= start)
ret = end - start;
else
ret = ~0ULL - start + 1 + end;
*res = gcd_res;
return ret;
}
#else
static inline struct timespec read_time(void)
{
struct timespec time;
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &time);
return time;
}
static inline unsigned long long diff_time(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec - start.tv_nsec) < 0) {
temp.tv_sec = end.tv_sec - start.tv_sec - 1;
temp.tv_nsec = 1000000000ULL + end.tv_nsec - start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec - start.tv_sec;
temp.tv_nsec = end.tv_nsec - start.tv_nsec;
}
return temp.tv_sec * 1000000000ULL + temp.tv_nsec;
}
static unsigned long long benchmark_gcd_func(unsigned long (*gcd)(unsigned long, unsigned long),
unsigned long a, unsigned long b, unsigned long *res)
{
struct timespec start, end;
unsigned long gcd_res;
start = read_time();
gcd_res = gcd(a, b);
end = read_time();
*res = gcd_res;
return diff_time(start, end);
}
#endif
static inline unsigned long get_rand()
{
if (sizeof(long) == 8)
return (unsigned long)rand() << 32 | rand();
else
return rand();
}
int main(int argc, char **argv)
{
unsigned int seed = time(0);
int loops = 100;
int repeats = 1000;
unsigned long (*res)[TEST_ENTRIES];
unsigned long long elapsed[TEST_ENTRIES];
int i, j, k;
for (;;) {
int opt = getopt(argc, argv, "n:r:s:");
/* End condition always first */
if (opt == -1)
break;
switch (opt) {
case 'n':
loops = atoi(optarg);
break;
case 'r':
repeats = atoi(optarg);
break;
case 's':
seed = strtoul(optarg, NULL, 10);
break;
default:
/* You won't actually get here. */
break;
}
}
res = malloc(sizeof(unsigned long) * TEST_ENTRIES * loops);
memset(elapsed, 0, sizeof(elapsed));
srand(seed);
for (j = 0; j < loops; j++) {
unsigned long a = get_rand();
/* Do we have args? */
unsigned long b = argc > optind ? strtoul(argv[optind], NULL, 10) : get_rand();
unsigned long long min_elapsed[TEST_ENTRIES];
for (k = 0; k < repeats; k++) {
for (i = 0; i < TEST_ENTRIES; i++) {
unsigned long long tmp = benchmark_gcd_func(gcd_func[i], a, b, &res[j][i]);
if (k == 0 || min_elapsed[i] > tmp)
min_elapsed[i] = tmp;
}
}
for (i = 0; i < TEST_ENTRIES; i++)
elapsed[i] += min_elapsed[i];
}
for (i = 0; i < TEST_ENTRIES; i++)
printf("gcd%d: elapsed %llu\n", i, elapsed[i]);
k = 0;
srand(seed);
for (j = 0; j < loops; j++) {
unsigned long a = get_rand();
unsigned long b = argc > optind ? strtoul(argv[optind], NULL, 10) : get_rand();
for (i = 1; i < TEST_ENTRIES; i++) {
if (res[j][i] != res[j][0])
break;
}
if (i < TEST_ENTRIES) {
if (k == 0) {
k = 1;
fprintf(stderr, "Error:\n");
}
fprintf(stderr, "gcd(%lu, %lu): ", a, b);
for (i = 0; i < TEST_ENTRIES; i++)
fprintf(stderr, "%ld%s", res[j][i], i < TEST_ENTRIES - 1 ? ", " : "\n");
}
}
if (k == 0)
fprintf(stderr, "PASS\n");
free(res);
return 0;
}
Compiled with "-O2", on "VirtualBox 4.4.0-22-generic #38-Ubuntu x86_64" got:
zhaoxiuzeng@zhaoxiuzeng-VirtualBox:~/develop$ ./gcd -r 500000 -n 10
gcd0: elapsed 10174
gcd1: elapsed 2120
gcd2: elapsed 2902
gcd3: elapsed 2039
gcd4: elapsed 2812
PASS
zhaoxiuzeng@zhaoxiuzeng-VirtualBox:~/develop$ ./gcd -r 500000 -n 10
gcd0: elapsed 9309
gcd1: elapsed 2280
gcd2: elapsed 2822
gcd3: elapsed 2217
gcd4: elapsed 2710
PASS
zhaoxiuzeng@zhaoxiuzeng-VirtualBox:~/develop$ ./gcd -r 500000 -n 10
gcd0: elapsed 9589
gcd1: elapsed 2098
gcd2: elapsed 2815
gcd3: elapsed 2030
gcd4: elapsed 2718
PASS
zhaoxiuzeng@zhaoxiuzeng-VirtualBox:~/develop$ ./gcd -r 500000 -n 10
gcd0: elapsed 9914
gcd1: elapsed 2309
gcd2: elapsed 2779
gcd3: elapsed 2228
gcd4: elapsed 2709
PASS
[akpm@linux-foundation.org: avoid #defining a CONFIG_ variable]
Signed-off-by: Zhaoxiu Zeng <zhaoxiu.zeng@gmail.com>
Signed-off-by: George Spelvin <linux@horizon.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
500 lines
12 KiB
Plaintext
500 lines
12 KiB
Plaintext
comment "Processor Type"
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choice
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prompt "CPU family support"
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default M68KCLASSIC if MMU
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default COLDFIRE if !MMU
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help
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The Freescale (was Motorola) M68K family of processors implements
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the full 68000 processor instruction set.
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The Freescale ColdFire family of processors is a modern derivative
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of the 68000 processor family. They are mainly targeted at embedded
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applications, and are all System-On-Chip (SOC) devices, as opposed
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to stand alone CPUs. They implement a subset of the original 68000
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processor instruction set.
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If you anticipate running this kernel on a computer with a classic
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MC68xxx processor, select M68KCLASSIC.
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If you anticipate running this kernel on a computer with a ColdFire
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processor, select COLDFIRE.
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config M68KCLASSIC
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bool "Classic M68K CPU family support"
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config COLDFIRE
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bool "Coldfire CPU family support"
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select ARCH_HAVE_CUSTOM_GPIO_H
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select CPU_HAS_NO_BITFIELDS
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select CPU_HAS_NO_MULDIV64
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select GENERIC_CSUM
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select GPIOLIB
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select HAVE_CLK
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endchoice
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if M68KCLASSIC
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config M68000
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bool "MC68000"
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depends on !MMU
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select CPU_HAS_NO_BITFIELDS
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select CPU_HAS_NO_MULDIV64
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select CPU_HAS_NO_UNALIGNED
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select GENERIC_CSUM
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select CPU_NO_EFFICIENT_FFS
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help
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The Freescale (was Motorola) 68000 CPU is the first generation of
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the well known M68K family of processors. The CPU core as well as
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being available as a stand alone CPU was also used in many
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System-On-Chip devices (eg 68328, 68302, etc). It does not contain
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a paging MMU.
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config MCPU32
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bool
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select CPU_HAS_NO_BITFIELDS
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select CPU_HAS_NO_UNALIGNED
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select CPU_NO_EFFICIENT_FFS
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help
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The Freescale (was then Motorola) CPU32 is a CPU core that is
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based on the 68020 processor. For the most part it is used in
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System-On-Chip parts, and does not contain a paging MMU.
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config M68020
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bool "68020 support"
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depends on MMU
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select CPU_HAS_ADDRESS_SPACES
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help
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If you anticipate running this kernel on a computer with a MC68020
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processor, say Y. Otherwise, say N. Note that the 68020 requires a
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68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
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Sun 3, which provides its own version.
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config M68030
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bool "68030 support"
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depends on MMU && !MMU_SUN3
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select CPU_HAS_ADDRESS_SPACES
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help
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If you anticipate running this kernel on a computer with a MC68030
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processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
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work, as it does not include an MMU (Memory Management Unit).
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config M68040
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bool "68040 support"
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depends on MMU && !MMU_SUN3
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select CPU_HAS_ADDRESS_SPACES
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help
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If you anticipate running this kernel on a computer with a MC68LC040
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or MC68040 processor, say Y. Otherwise, say N. Note that an
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MC68EC040 will not work, as it does not include an MMU (Memory
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Management Unit).
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config M68060
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bool "68060 support"
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depends on MMU && !MMU_SUN3
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select CPU_HAS_ADDRESS_SPACES
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help
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If you anticipate running this kernel on a computer with a MC68060
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processor, say Y. Otherwise, say N.
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config M68328
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bool "MC68328"
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depends on !MMU
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select M68000
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help
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Motorola 68328 processor support.
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config M68EZ328
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bool "MC68EZ328"
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depends on !MMU
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select M68000
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help
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Motorola 68EX328 processor support.
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config M68VZ328
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bool "MC68VZ328"
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depends on !MMU
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select M68000
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help
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Motorola 68VZ328 processor support.
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endif # M68KCLASSIC
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if COLDFIRE
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choice
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prompt "ColdFire SoC type"
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default M520x
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help
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Select the type of ColdFire System-on-Chip (SoC) that you want
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to build for.
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config M5206
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bool "MCF5206"
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depends on !MMU
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select COLDFIRE_SW_A7
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select HAVE_MBAR
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select CPU_NO_EFFICIENT_FFS
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help
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Motorola ColdFire 5206 processor support.
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config M5206e
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bool "MCF5206e"
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depends on !MMU
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select COLDFIRE_SW_A7
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select HAVE_MBAR
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select CPU_NO_EFFICIENT_FFS
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help
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Motorola ColdFire 5206e processor support.
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config M520x
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bool "MCF520x"
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depends on !MMU
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select GENERIC_CLOCKEVENTS
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select HAVE_CACHE_SPLIT
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help
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Freescale Coldfire 5207/5208 processor support.
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config M523x
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bool "MCF523x"
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depends on !MMU
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select GENERIC_CLOCKEVENTS
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select HAVE_CACHE_SPLIT
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select HAVE_IPSBAR
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help
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Freescale Coldfire 5230/1/2/4/5 processor support
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config M5249
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bool "MCF5249"
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depends on !MMU
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select COLDFIRE_SW_A7
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select HAVE_MBAR
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select CPU_NO_EFFICIENT_FFS
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help
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Motorola ColdFire 5249 processor support.
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config M525x
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bool "MCF525x"
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depends on !MMU
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select COLDFIRE_SW_A7
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select HAVE_MBAR
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select CPU_NO_EFFICIENT_FFS
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help
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Freescale (Motorola) Coldfire 5251/5253 processor support.
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config M5271
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bool "MCF5271"
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depends on !MMU
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select M527x
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select HAVE_CACHE_SPLIT
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select HAVE_IPSBAR
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select GENERIC_CLOCKEVENTS
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help
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Freescale (Motorola) ColdFire 5270/5271 processor support.
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config M5272
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bool "MCF5272"
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depends on !MMU
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select COLDFIRE_SW_A7
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select HAVE_MBAR
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select CPU_NO_EFFICIENT_FFS
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help
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Motorola ColdFire 5272 processor support.
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config M5275
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bool "MCF5275"
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depends on !MMU
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select M527x
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select HAVE_CACHE_SPLIT
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select HAVE_IPSBAR
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select GENERIC_CLOCKEVENTS
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help
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Freescale (Motorola) ColdFire 5274/5275 processor support.
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config M528x
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bool "MCF528x"
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depends on !MMU
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select GENERIC_CLOCKEVENTS
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select HAVE_CACHE_SPLIT
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select HAVE_IPSBAR
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help
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Motorola ColdFire 5280/5282 processor support.
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config M5307
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bool "MCF5307"
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depends on !MMU
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select COLDFIRE_SW_A7
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select HAVE_CACHE_CB
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select HAVE_MBAR
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select CPU_NO_EFFICIENT_FFS
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help
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Motorola ColdFire 5307 processor support.
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config M532x
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bool "MCF532x"
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depends on !MMU
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select M53xx
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select HAVE_CACHE_CB
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help
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Freescale (Motorola) ColdFire 532x processor support.
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config M537x
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bool "MCF537x"
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depends on !MMU
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select M53xx
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select HAVE_CACHE_CB
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help
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Freescale ColdFire 537x processor support.
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config M5407
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bool "MCF5407"
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depends on !MMU
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select COLDFIRE_SW_A7
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select HAVE_CACHE_CB
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select HAVE_MBAR
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select CPU_NO_EFFICIENT_FFS
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help
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Motorola ColdFire 5407 processor support.
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config M547x
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bool "MCF547x"
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select M54xx
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select MMU_COLDFIRE if MMU
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select HAVE_CACHE_CB
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select HAVE_MBAR
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select CPU_NO_EFFICIENT_FFS
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help
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Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
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config M548x
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bool "MCF548x"
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select MMU_COLDFIRE if MMU
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select M54xx
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select HAVE_CACHE_CB
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select HAVE_MBAR
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select CPU_NO_EFFICIENT_FFS
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help
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Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
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config M5441x
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bool "MCF5441x"
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depends on !MMU
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select GENERIC_CLOCKEVENTS
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select HAVE_CACHE_CB
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help
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Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
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endchoice
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config M527x
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bool
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config M53xx
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bool
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config M54xx
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bool
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endif # COLDFIRE
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comment "Processor Specific Options"
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config M68KFPU_EMU
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bool "Math emulation support"
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depends on MMU
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help
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At some point in the future, this will cause floating-point math
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instructions to be emulated by the kernel on machines that lack a
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floating-point math coprocessor. Thrill-seekers and chronically
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sleep-deprived psychotic hacker types can say Y now, everyone else
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should probably wait a while.
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config M68KFPU_EMU_EXTRAPREC
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bool "Math emulation extra precision"
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depends on M68KFPU_EMU
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help
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The fpu uses normally a few bit more during calculations for
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correct rounding, the emulator can (often) do the same but this
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extra calculation can cost quite some time, so you can disable
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it here. The emulator will then "only" calculate with a 64 bit
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mantissa and round slightly incorrect, what is more than enough
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for normal usage.
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config M68KFPU_EMU_ONLY
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bool "Math emulation only kernel"
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depends on M68KFPU_EMU
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help
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This option prevents any floating-point instructions from being
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compiled into the kernel, thereby the kernel doesn't save any
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floating point context anymore during task switches, so this
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kernel will only be usable on machines without a floating-point
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math coprocessor. This makes the kernel a bit faster as no tests
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needs to be executed whether a floating-point instruction in the
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kernel should be executed or not.
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config ADVANCED
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bool "Advanced configuration options"
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depends on MMU
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---help---
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This gives you access to some advanced options for the CPU. The
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defaults should be fine for most users, but these options may make
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it possible for you to improve performance somewhat if you know what
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you are doing.
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Note that the answer to this question won't directly affect the
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kernel: saying N will just cause the configurator to skip all
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the questions about these options.
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|
|
Most users should say N to this question.
|
|
|
|
config RMW_INSNS
|
|
bool "Use read-modify-write instructions"
|
|
depends on ADVANCED
|
|
---help---
|
|
This allows to use certain instructions that work with indivisible
|
|
read-modify-write bus cycles. While this is faster than the
|
|
workaround of disabling interrupts, it can conflict with DMA
|
|
( = direct memory access) on many Amiga systems, and it is also said
|
|
to destabilize other machines. It is very likely that this will
|
|
cause serious problems on any Amiga or Atari Medusa if set. The only
|
|
configuration where it should work are 68030-based Ataris, where it
|
|
apparently improves performance. But you've been warned! Unless you
|
|
really know what you are doing, say N. Try Y only if you're quite
|
|
adventurous.
|
|
|
|
config SINGLE_MEMORY_CHUNK
|
|
bool "Use one physical chunk of memory only" if ADVANCED && !SUN3
|
|
depends on MMU
|
|
default y if SUN3
|
|
select NEED_MULTIPLE_NODES
|
|
help
|
|
Ignore all but the first contiguous chunk of physical memory for VM
|
|
purposes. This will save a few bytes kernel size and may speed up
|
|
some operations. Say N if not sure.
|
|
|
|
config ARCH_DISCONTIGMEM_ENABLE
|
|
def_bool MMU && !SINGLE_MEMORY_CHUNK
|
|
|
|
config 060_WRITETHROUGH
|
|
bool "Use write-through caching for 68060 supervisor accesses"
|
|
depends on ADVANCED && M68060
|
|
---help---
|
|
The 68060 generally uses copyback caching of recently accessed data.
|
|
Copyback caching means that memory writes will be held in an on-chip
|
|
cache and only written back to memory some time later. Saying Y
|
|
here will force supervisor (kernel) accesses to use writethrough
|
|
caching. Writethrough caching means that data is written to memory
|
|
straight away, so that cache and memory data always agree.
|
|
Writethrough caching is less efficient, but is needed for some
|
|
drivers on 68060 based systems where the 68060 bus snooping signal
|
|
is hardwired on. The 53c710 SCSI driver is known to suffer from
|
|
this problem.
|
|
|
|
config M68K_L2_CACHE
|
|
bool
|
|
depends on MAC
|
|
default y
|
|
|
|
config NODES_SHIFT
|
|
int
|
|
default "3"
|
|
depends on !SINGLE_MEMORY_CHUNK
|
|
|
|
config CPU_HAS_NO_BITFIELDS
|
|
bool
|
|
|
|
config CPU_HAS_NO_MULDIV64
|
|
bool
|
|
|
|
config CPU_HAS_NO_UNALIGNED
|
|
bool
|
|
|
|
config CPU_HAS_ADDRESS_SPACES
|
|
bool
|
|
|
|
config FPU
|
|
bool
|
|
|
|
config COLDFIRE_SW_A7
|
|
bool
|
|
|
|
config HAVE_CACHE_SPLIT
|
|
bool
|
|
|
|
config HAVE_CACHE_CB
|
|
bool
|
|
|
|
config HAVE_MBAR
|
|
bool
|
|
|
|
config HAVE_IPSBAR
|
|
bool
|
|
|
|
config CLOCK_FREQ
|
|
int "Set the core clock frequency"
|
|
default "25000000" if M5206
|
|
default "54000000" if M5206e
|
|
default "166666666" if M520x
|
|
default "140000000" if M5249
|
|
default "150000000" if M527x || M523x
|
|
default "90000000" if M5307
|
|
default "50000000" if M5407
|
|
default "266000000" if M54xx
|
|
default "66666666"
|
|
depends on COLDFIRE
|
|
help
|
|
Define the CPU clock frequency in use. This is the core clock
|
|
frequency, it may or may not be the same as the external clock
|
|
crystal fitted to your board. Some processors have an internal
|
|
PLL and can have their frequency programmed at run time, others
|
|
use internal dividers. In general the kernel won't setup a PLL
|
|
if it is fitted (there are some exceptions). This value will be
|
|
specific to the exact CPU that you are using.
|
|
|
|
config OLDMASK
|
|
bool "Old mask 5307 (1H55J) silicon"
|
|
depends on M5307
|
|
help
|
|
Build support for the older revision ColdFire 5307 silicon.
|
|
Specifically this is the 1H55J mask revision.
|
|
|
|
if HAVE_CACHE_SPLIT
|
|
choice
|
|
prompt "Split Cache Configuration"
|
|
default CACHE_I
|
|
|
|
config CACHE_I
|
|
bool "Instruction"
|
|
help
|
|
Use all of the ColdFire CPU cache memory as an instruction cache.
|
|
|
|
config CACHE_D
|
|
bool "Data"
|
|
help
|
|
Use all of the ColdFire CPU cache memory as a data cache.
|
|
|
|
config CACHE_BOTH
|
|
bool "Both"
|
|
help
|
|
Split the ColdFire CPU cache, and use half as an instruction cache
|
|
and half as a data cache.
|
|
endchoice
|
|
endif
|
|
|
|
if HAVE_CACHE_CB
|
|
choice
|
|
prompt "Data cache mode"
|
|
default CACHE_WRITETHRU
|
|
|
|
config CACHE_WRITETHRU
|
|
bool "Write-through"
|
|
help
|
|
The ColdFire CPU cache is set into Write-through mode.
|
|
|
|
config CACHE_COPYBACK
|
|
bool "Copy-back"
|
|
help
|
|
The ColdFire CPU cache is set into Copy-back mode.
|
|
endchoice
|
|
endif
|
|
|