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https://github.com/torvalds/linux.git
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6d4cc40fb5
Kprobes allows you to trap at almost any kernel address and execute a callback function, this commit adds kprobes support for LoongArch. Tested-by: Jeff Xie <xiehuan09@gmail.com> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
815 lines
19 KiB
C
815 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Author: Huacai Chen <chenhuacai@loongson.cn>
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/compiler.h>
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#include <linux/context_tracking.h>
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#include <linux/entry-common.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/kexec.h>
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#include <linux/module.h>
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#include <linux/extable.h>
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#include <linux/mm.h>
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#include <linux/sched/mm.h>
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#include <linux/sched/debug.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/kallsyms.h>
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#include <linux/memblock.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <linux/kgdb.h>
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#include <linux/kdebug.h>
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#include <linux/kprobes.h>
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#include <linux/notifier.h>
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#include <linux/irq.h>
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#include <linux/perf_event.h>
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#include <asm/addrspace.h>
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#include <asm/bootinfo.h>
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#include <asm/branch.h>
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#include <asm/break.h>
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#include <asm/cpu.h>
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#include <asm/fpu.h>
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#include <asm/loongarch.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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#include <asm/sections.h>
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#include <asm/siginfo.h>
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#include <asm/stacktrace.h>
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#include <asm/tlb.h>
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#include <asm/types.h>
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#include <asm/unwind.h>
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#include "access-helper.h"
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extern asmlinkage void handle_ade(void);
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extern asmlinkage void handle_ale(void);
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extern asmlinkage void handle_sys(void);
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extern asmlinkage void handle_bp(void);
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extern asmlinkage void handle_ri(void);
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extern asmlinkage void handle_fpu(void);
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extern asmlinkage void handle_fpe(void);
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extern asmlinkage void handle_lbt(void);
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extern asmlinkage void handle_lsx(void);
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extern asmlinkage void handle_lasx(void);
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extern asmlinkage void handle_reserved(void);
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extern asmlinkage void handle_watch(void);
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extern asmlinkage void handle_vint(void);
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static void show_backtrace(struct task_struct *task, const struct pt_regs *regs,
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const char *loglvl, bool user)
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{
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unsigned long addr;
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struct unwind_state state;
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struct pt_regs *pregs = (struct pt_regs *)regs;
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if (!task)
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task = current;
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printk("%sCall Trace:", loglvl);
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for (unwind_start(&state, task, pregs);
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!unwind_done(&state); unwind_next_frame(&state)) {
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addr = unwind_get_return_address(&state);
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print_ip_sym(loglvl, addr);
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}
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printk("%s\n", loglvl);
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}
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static void show_stacktrace(struct task_struct *task,
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const struct pt_regs *regs, const char *loglvl, bool user)
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{
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int i;
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const int field = 2 * sizeof(unsigned long);
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unsigned long stackdata;
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unsigned long *sp = (unsigned long *)regs->regs[3];
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printk("%sStack :", loglvl);
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i = 0;
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while ((unsigned long) sp & (PAGE_SIZE - 1)) {
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if (i && ((i % (64 / field)) == 0)) {
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pr_cont("\n");
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printk("%s ", loglvl);
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}
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if (i > 39) {
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pr_cont(" ...");
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break;
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}
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if (__get_addr(&stackdata, sp++, user)) {
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pr_cont(" (Bad stack address)");
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break;
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}
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pr_cont(" %0*lx", field, stackdata);
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i++;
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}
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pr_cont("\n");
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show_backtrace(task, regs, loglvl, user);
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}
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void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl)
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{
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struct pt_regs regs;
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regs.csr_crmd = 0;
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if (sp) {
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regs.csr_era = 0;
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regs.regs[1] = 0;
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regs.regs[3] = (unsigned long)sp;
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} else {
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if (!task || task == current)
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prepare_frametrace(®s);
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else {
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regs.csr_era = task->thread.reg01;
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regs.regs[1] = 0;
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regs.regs[3] = task->thread.reg03;
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regs.regs[22] = task->thread.reg22;
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}
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}
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show_stacktrace(task, ®s, loglvl, false);
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}
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static void show_code(unsigned int *pc, bool user)
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{
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long i;
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unsigned int insn;
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printk("Code:");
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for(i = -3 ; i < 6 ; i++) {
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if (__get_inst(&insn, pc + i, user)) {
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pr_cont(" (Bad address in era)\n");
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break;
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}
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pr_cont("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
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}
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pr_cont("\n");
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}
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static void __show_regs(const struct pt_regs *regs)
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{
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const int field = 2 * sizeof(unsigned long);
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unsigned int excsubcode;
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unsigned int exccode;
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int i;
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show_regs_print_info(KERN_DEFAULT);
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/*
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* Saved main processor registers
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*/
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for (i = 0; i < 32; ) {
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if ((i % 4) == 0)
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printk("$%2d :", i);
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pr_cont(" %0*lx", field, regs->regs[i]);
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i++;
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if ((i % 4) == 0)
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pr_cont("\n");
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}
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/*
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* Saved csr registers
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*/
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printk("era : %0*lx %pS\n", field, regs->csr_era,
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(void *) regs->csr_era);
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printk("ra : %0*lx %pS\n", field, regs->regs[1],
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(void *) regs->regs[1]);
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printk("CSR crmd: %08lx ", regs->csr_crmd);
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printk("CSR prmd: %08lx ", regs->csr_prmd);
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printk("CSR euen: %08lx ", regs->csr_euen);
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printk("CSR ecfg: %08lx ", regs->csr_ecfg);
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printk("CSR estat: %08lx ", regs->csr_estat);
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pr_cont("\n");
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exccode = ((regs->csr_estat) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
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excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT;
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printk("ExcCode : %x (SubCode %x)\n", exccode, excsubcode);
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if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE)
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printk("BadVA : %0*lx\n", field, regs->csr_badvaddr);
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printk("PrId : %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
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cpu_family_string());
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}
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void show_regs(struct pt_regs *regs)
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{
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__show_regs((struct pt_regs *)regs);
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dump_stack();
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}
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void show_registers(struct pt_regs *regs)
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{
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__show_regs(regs);
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print_modules();
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printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
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current->comm, current->pid, current_thread_info(), current);
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show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs));
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show_code((void *)regs->csr_era, user_mode(regs));
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printk("\n");
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}
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static DEFINE_RAW_SPINLOCK(die_lock);
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void __noreturn die(const char *str, struct pt_regs *regs)
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{
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static int die_counter;
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int sig = SIGSEGV;
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oops_enter();
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if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
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SIGSEGV) == NOTIFY_STOP)
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sig = 0;
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console_verbose();
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raw_spin_lock_irq(&die_lock);
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bust_spinlocks(1);
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printk("%s[#%d]:\n", str, ++die_counter);
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show_registers(regs);
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add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
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raw_spin_unlock_irq(&die_lock);
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oops_exit();
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if (regs && kexec_should_crash(current))
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crash_kexec(regs);
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if (in_interrupt())
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panic("Fatal exception in interrupt");
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if (panic_on_oops)
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panic("Fatal exception");
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make_task_dead(sig);
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}
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static inline void setup_vint_size(unsigned int size)
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{
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unsigned int vs;
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vs = ilog2(size/4);
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if (vs == 0 || vs > 7)
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panic("vint_size %d Not support yet", vs);
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csr_xchg32(vs<<CSR_ECFG_VS_SHIFT, CSR_ECFG_VS, LOONGARCH_CSR_ECFG);
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}
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/*
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* Send SIGFPE according to FCSR Cause bits, which must have already
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* been masked against Enable bits. This is impotant as Inexact can
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* happen together with Overflow or Underflow, and `ptrace' can set
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* any bits.
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*/
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void force_fcsr_sig(unsigned long fcsr, void __user *fault_addr,
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struct task_struct *tsk)
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{
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int si_code = FPE_FLTUNK;
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if (fcsr & FPU_CSR_INV_X)
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si_code = FPE_FLTINV;
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else if (fcsr & FPU_CSR_DIV_X)
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si_code = FPE_FLTDIV;
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else if (fcsr & FPU_CSR_OVF_X)
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si_code = FPE_FLTOVF;
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else if (fcsr & FPU_CSR_UDF_X)
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si_code = FPE_FLTUND;
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else if (fcsr & FPU_CSR_INE_X)
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si_code = FPE_FLTRES;
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force_sig_fault(SIGFPE, si_code, fault_addr);
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}
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int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcsr)
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{
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int si_code;
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switch (sig) {
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case 0:
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return 0;
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case SIGFPE:
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force_fcsr_sig(fcsr, fault_addr, current);
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return 1;
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case SIGBUS:
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force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr);
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return 1;
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case SIGSEGV:
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mmap_read_lock(current->mm);
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if (vma_lookup(current->mm, (unsigned long)fault_addr))
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si_code = SEGV_ACCERR;
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else
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si_code = SEGV_MAPERR;
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mmap_read_unlock(current->mm);
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force_sig_fault(SIGSEGV, si_code, fault_addr);
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return 1;
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default:
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force_sig(sig);
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return 1;
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}
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}
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/*
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* Delayed fp exceptions when doing a lazy ctx switch
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*/
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asmlinkage void noinstr do_fpe(struct pt_regs *regs, unsigned long fcsr)
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{
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int sig;
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void __user *fault_addr;
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irqentry_state_t state = irqentry_enter(regs);
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if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
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SIGFPE) == NOTIFY_STOP)
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goto out;
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/* Clear FCSR.Cause before enabling interrupts */
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write_fcsr(LOONGARCH_FCSR0, fcsr & ~mask_fcsr_x(fcsr));
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local_irq_enable();
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die_if_kernel("FP exception in kernel code", regs);
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sig = SIGFPE;
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fault_addr = (void __user *) regs->csr_era;
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/* Send a signal if required. */
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process_fpemu_return(sig, fault_addr, fcsr);
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out:
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local_irq_disable();
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irqentry_exit(regs, state);
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}
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asmlinkage void noinstr do_ade(struct pt_regs *regs)
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{
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irqentry_state_t state = irqentry_enter(regs);
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die_if_kernel("Kernel ade access", regs);
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force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)regs->csr_badvaddr);
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irqentry_exit(regs, state);
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}
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/* sysctl hooks */
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int unaligned_enabled __read_mostly = 1; /* Enabled by default */
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int no_unaligned_warning __read_mostly = 1; /* Only 1 warning by default */
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asmlinkage void noinstr do_ale(struct pt_regs *regs)
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{
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irqentry_state_t state = irqentry_enter(regs);
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#ifndef CONFIG_ARCH_STRICT_ALIGN
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die_if_kernel("Kernel ale access", regs);
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force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr);
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#else
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unsigned int *pc;
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perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->csr_badvaddr);
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/*
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* Did we catch a fault trying to load an instruction?
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*/
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if (regs->csr_badvaddr == regs->csr_era)
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goto sigbus;
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if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
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goto sigbus;
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if (!unaligned_enabled)
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goto sigbus;
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if (!no_unaligned_warning)
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show_registers(regs);
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pc = (unsigned int *)exception_era(regs);
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emulate_load_store_insn(regs, (void __user *)regs->csr_badvaddr, pc);
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goto out;
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sigbus:
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die_if_kernel("Kernel ale access", regs);
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force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr);
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out:
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#endif
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irqentry_exit(regs, state);
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}
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#ifdef CONFIG_GENERIC_BUG
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int is_valid_bugaddr(unsigned long addr)
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{
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return 1;
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}
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#endif /* CONFIG_GENERIC_BUG */
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static void bug_handler(struct pt_regs *regs)
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{
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switch (report_bug(regs->csr_era, regs)) {
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case BUG_TRAP_TYPE_BUG:
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case BUG_TRAP_TYPE_NONE:
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die_if_kernel("Oops - BUG", regs);
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force_sig(SIGTRAP);
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break;
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case BUG_TRAP_TYPE_WARN:
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/* Skip the BUG instruction and continue */
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regs->csr_era += LOONGARCH_INSN_SIZE;
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break;
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}
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}
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asmlinkage void noinstr do_bp(struct pt_regs *regs)
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{
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bool user = user_mode(regs);
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unsigned int opcode, bcode;
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unsigned long era = exception_era(regs);
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irqentry_state_t state = irqentry_enter(regs);
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if (regs->csr_prmd & CSR_PRMD_PIE)
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local_irq_enable();
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current->thread.trap_nr = read_csr_excode();
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if (__get_inst(&opcode, (u32 *)era, user))
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goto out_sigsegv;
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bcode = (opcode & 0x7fff);
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/*
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* notify the kprobe handlers, if instruction is likely to
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* pertain to them.
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*/
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switch (bcode) {
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case BRK_KPROBE_BP:
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if (kprobe_breakpoint_handler(regs))
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goto out;
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else
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break;
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case BRK_KPROBE_SSTEPBP:
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if (kprobe_singlestep_handler(regs))
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goto out;
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else
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break;
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case BRK_UPROBE_BP:
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if (notify_die(DIE_UPROBE, "Uprobe", regs, bcode,
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current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
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goto out;
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else
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break;
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case BRK_UPROBE_XOLBP:
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if (notify_die(DIE_UPROBE_XOL, "Uprobe_XOL", regs, bcode,
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current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
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goto out;
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else
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break;
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default:
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if (notify_die(DIE_TRAP, "Break", regs, bcode,
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current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
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goto out;
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else
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break;
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}
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switch (bcode) {
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case BRK_BUG:
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bug_handler(regs);
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break;
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case BRK_DIVZERO:
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die_if_kernel("Break instruction in kernel code", regs);
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force_sig_fault(SIGFPE, FPE_INTDIV, (void __user *)regs->csr_era);
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break;
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case BRK_OVERFLOW:
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die_if_kernel("Break instruction in kernel code", regs);
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force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->csr_era);
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break;
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default:
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die_if_kernel("Break instruction in kernel code", regs);
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force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->csr_era);
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break;
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}
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out:
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if (regs->csr_prmd & CSR_PRMD_PIE)
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local_irq_disable();
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|
|
irqentry_exit(regs, state);
|
|
return;
|
|
|
|
out_sigsegv:
|
|
force_sig(SIGSEGV);
|
|
goto out;
|
|
}
|
|
|
|
asmlinkage void noinstr do_watch(struct pt_regs *regs)
|
|
{
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
#ifndef CONFIG_HAVE_HW_BREAKPOINT
|
|
pr_warn("Hardware watch point handler not implemented!\n");
|
|
#else
|
|
if (test_tsk_thread_flag(current, TIF_SINGLESTEP)) {
|
|
int llbit = (csr_read32(LOONGARCH_CSR_LLBCTL) & 0x1);
|
|
unsigned long pc = instruction_pointer(regs);
|
|
union loongarch_instruction *ip = (union loongarch_instruction *)pc;
|
|
|
|
if (llbit) {
|
|
/*
|
|
* When the ll-sc combo is encountered, it is regarded as an single
|
|
* instruction. So don't clear llbit and reset CSR.FWPS.Skip until
|
|
* the llsc execution is completed.
|
|
*/
|
|
csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS);
|
|
csr_write32(CSR_LLBCTL_KLO, LOONGARCH_CSR_LLBCTL);
|
|
goto out;
|
|
}
|
|
|
|
if (pc == current->thread.single_step) {
|
|
/*
|
|
* Certain insns are occasionally not skipped when CSR.FWPS.Skip is
|
|
* set, such as fld.d/fst.d. So singlestep needs to compare whether
|
|
* the csr_era is equal to the value of singlestep which last time set.
|
|
*/
|
|
if (!is_self_loop_ins(ip, regs)) {
|
|
/*
|
|
* Check if the given instruction the target pc is equal to the
|
|
* current pc, If yes, then we should not set the CSR.FWPS.SKIP
|
|
* bit to break the original instruction stream.
|
|
*/
|
|
csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS);
|
|
goto out;
|
|
}
|
|
}
|
|
} else {
|
|
breakpoint_handler(regs);
|
|
watchpoint_handler(regs);
|
|
}
|
|
|
|
force_sig(SIGTRAP);
|
|
out:
|
|
#endif
|
|
irqentry_exit(regs, state);
|
|
}
|
|
|
|
asmlinkage void noinstr do_ri(struct pt_regs *regs)
|
|
{
|
|
int status = SIGILL;
|
|
unsigned int opcode = 0;
|
|
unsigned int __user *era = (unsigned int __user *)exception_era(regs);
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
local_irq_enable();
|
|
current->thread.trap_nr = read_csr_excode();
|
|
|
|
if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
|
|
SIGILL) == NOTIFY_STOP)
|
|
goto out;
|
|
|
|
die_if_kernel("Reserved instruction in kernel code", regs);
|
|
|
|
if (unlikely(get_user(opcode, era) < 0)) {
|
|
status = SIGSEGV;
|
|
current->thread.error_code = 1;
|
|
}
|
|
|
|
force_sig(status);
|
|
|
|
out:
|
|
local_irq_disable();
|
|
irqentry_exit(regs, state);
|
|
}
|
|
|
|
static void init_restore_fp(void)
|
|
{
|
|
if (!used_math()) {
|
|
/* First time FP context user. */
|
|
init_fpu();
|
|
} else {
|
|
/* This task has formerly used the FP context */
|
|
if (!is_fpu_owner())
|
|
own_fpu_inatomic(1);
|
|
}
|
|
|
|
BUG_ON(!is_fp_enabled());
|
|
}
|
|
|
|
asmlinkage void noinstr do_fpu(struct pt_regs *regs)
|
|
{
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
local_irq_enable();
|
|
die_if_kernel("do_fpu invoked from kernel context!", regs);
|
|
|
|
preempt_disable();
|
|
init_restore_fp();
|
|
preempt_enable();
|
|
|
|
local_irq_disable();
|
|
irqentry_exit(regs, state);
|
|
}
|
|
|
|
asmlinkage void noinstr do_lsx(struct pt_regs *regs)
|
|
{
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
local_irq_enable();
|
|
force_sig(SIGILL);
|
|
local_irq_disable();
|
|
|
|
irqentry_exit(regs, state);
|
|
}
|
|
|
|
asmlinkage void noinstr do_lasx(struct pt_regs *regs)
|
|
{
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
local_irq_enable();
|
|
force_sig(SIGILL);
|
|
local_irq_disable();
|
|
|
|
irqentry_exit(regs, state);
|
|
}
|
|
|
|
asmlinkage void noinstr do_lbt(struct pt_regs *regs)
|
|
{
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
local_irq_enable();
|
|
force_sig(SIGILL);
|
|
local_irq_disable();
|
|
|
|
irqentry_exit(regs, state);
|
|
}
|
|
|
|
asmlinkage void noinstr do_reserved(struct pt_regs *regs)
|
|
{
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
local_irq_enable();
|
|
/*
|
|
* Game over - no way to handle this if it ever occurs. Most probably
|
|
* caused by a fatal error after another hardware/software error.
|
|
*/
|
|
pr_err("Caught reserved exception %u on pid:%d [%s] - should not happen\n",
|
|
read_csr_excode(), current->pid, current->comm);
|
|
die_if_kernel("do_reserved exception", regs);
|
|
force_sig(SIGUNUSED);
|
|
|
|
local_irq_disable();
|
|
|
|
irqentry_exit(regs, state);
|
|
}
|
|
|
|
asmlinkage void cache_parity_error(void)
|
|
{
|
|
/* For the moment, report the problem and hang. */
|
|
pr_err("Cache error exception:\n");
|
|
pr_err("csr_merrctl == %08x\n", csr_read32(LOONGARCH_CSR_MERRCTL));
|
|
pr_err("csr_merrera == %016llx\n", csr_read64(LOONGARCH_CSR_MERRERA));
|
|
panic("Can't handle the cache error!");
|
|
}
|
|
|
|
asmlinkage void noinstr handle_loongarch_irq(struct pt_regs *regs)
|
|
{
|
|
struct pt_regs *old_regs;
|
|
|
|
irq_enter_rcu();
|
|
old_regs = set_irq_regs(regs);
|
|
handle_arch_irq(regs);
|
|
set_irq_regs(old_regs);
|
|
irq_exit_rcu();
|
|
}
|
|
|
|
asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp)
|
|
{
|
|
register int cpu;
|
|
register unsigned long stack;
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
cpu = smp_processor_id();
|
|
|
|
if (on_irq_stack(cpu, sp))
|
|
handle_loongarch_irq(regs);
|
|
else {
|
|
stack = per_cpu(irq_stack, cpu) + IRQ_STACK_START;
|
|
|
|
/* Save task's sp on IRQ stack for unwinding */
|
|
*(unsigned long *)stack = sp;
|
|
|
|
__asm__ __volatile__(
|
|
"move $s0, $sp \n" /* Preserve sp */
|
|
"move $sp, %[stk] \n" /* Switch stack */
|
|
"move $a0, %[regs] \n"
|
|
"bl handle_loongarch_irq \n"
|
|
"move $sp, $s0 \n" /* Restore sp */
|
|
: /* No outputs */
|
|
: [stk] "r" (stack), [regs] "r" (regs)
|
|
: "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", "$s0",
|
|
"$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8",
|
|
"memory");
|
|
}
|
|
|
|
irqentry_exit(regs, state);
|
|
}
|
|
|
|
unsigned long eentry;
|
|
unsigned long tlbrentry;
|
|
|
|
long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K);
|
|
|
|
static void configure_exception_vector(void)
|
|
{
|
|
eentry = (unsigned long)exception_handlers;
|
|
tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE;
|
|
|
|
csr_write64(eentry, LOONGARCH_CSR_EENTRY);
|
|
csr_write64(eentry, LOONGARCH_CSR_MERRENTRY);
|
|
csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY);
|
|
}
|
|
|
|
void per_cpu_trap_init(int cpu)
|
|
{
|
|
unsigned int i;
|
|
|
|
setup_vint_size(VECSIZE);
|
|
|
|
configure_exception_vector();
|
|
|
|
if (!cpu_data[cpu].asid_cache)
|
|
cpu_data[cpu].asid_cache = asid_first_version(cpu);
|
|
|
|
mmgrab(&init_mm);
|
|
current->active_mm = &init_mm;
|
|
BUG_ON(current->mm);
|
|
enter_lazy_tlb(&init_mm, current);
|
|
|
|
/* Initialise exception handlers */
|
|
if (cpu == 0)
|
|
for (i = 0; i < 64; i++)
|
|
set_handler(i * VECSIZE, handle_reserved, VECSIZE);
|
|
|
|
tlb_init(cpu);
|
|
cpu_cache_init();
|
|
}
|
|
|
|
/* Install CPU exception handler */
|
|
void set_handler(unsigned long offset, void *addr, unsigned long size)
|
|
{
|
|
memcpy((void *)(eentry + offset), addr, size);
|
|
local_flush_icache_range(eentry + offset, eentry + offset + size);
|
|
}
|
|
|
|
static const char panic_null_cerr[] =
|
|
"Trying to set NULL cache error exception handler\n";
|
|
|
|
/*
|
|
* Install uncached CPU exception handler.
|
|
* This is suitable only for the cache error exception which is the only
|
|
* exception handler that is being run uncached.
|
|
*/
|
|
void set_merr_handler(unsigned long offset, void *addr, unsigned long size)
|
|
{
|
|
unsigned long uncached_eentry = TO_UNCACHE(__pa(eentry));
|
|
|
|
if (!addr)
|
|
panic(panic_null_cerr);
|
|
|
|
memcpy((void *)(uncached_eentry + offset), addr, size);
|
|
}
|
|
|
|
void __init trap_init(void)
|
|
{
|
|
long i;
|
|
|
|
/* Set interrupt vector handler */
|
|
for (i = EXCCODE_INT_START; i < EXCCODE_INT_END; i++)
|
|
set_handler(i * VECSIZE, handle_vint, VECSIZE);
|
|
|
|
set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE);
|
|
set_handler(EXCCODE_ALE * VECSIZE, handle_ale, VECSIZE);
|
|
set_handler(EXCCODE_SYS * VECSIZE, handle_sys, VECSIZE);
|
|
set_handler(EXCCODE_BP * VECSIZE, handle_bp, VECSIZE);
|
|
set_handler(EXCCODE_INE * VECSIZE, handle_ri, VECSIZE);
|
|
set_handler(EXCCODE_IPE * VECSIZE, handle_ri, VECSIZE);
|
|
set_handler(EXCCODE_FPDIS * VECSIZE, handle_fpu, VECSIZE);
|
|
set_handler(EXCCODE_LSXDIS * VECSIZE, handle_lsx, VECSIZE);
|
|
set_handler(EXCCODE_LASXDIS * VECSIZE, handle_lasx, VECSIZE);
|
|
set_handler(EXCCODE_FPE * VECSIZE, handle_fpe, VECSIZE);
|
|
set_handler(EXCCODE_BTDIS * VECSIZE, handle_lbt, VECSIZE);
|
|
set_handler(EXCCODE_WATCH * VECSIZE, handle_watch, VECSIZE);
|
|
|
|
cache_error_setup();
|
|
|
|
local_flush_icache_range(eentry, eentry + 0x400);
|
|
}
|