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1219715de7
Some Feroceon-based SoCs have an MBUS bridge interrupt controller that requires writing a one instead of a zero to clear edge interrupt sources such as timer expiry. This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> |
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debug-macro.S | ||
dma.h | ||
entry-macro.S | ||
gpio.h | ||
hardware.h | ||
io.h | ||
irqs.h | ||
memory.h | ||
orion5x.h | ||
system.h | ||
timex.h | ||
uncompress.h | ||
vmalloc.h |