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b61a40afca
Current cache probe and flush methods have some drawbacks: 1, Assume there are 3 cache levels and only 3 levels; 2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive. However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are all valid. So, refactor the cache probe and flush methods to adapt more types of cache hierarchy. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
101 lines
2.3 KiB
C
101 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/acpi.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/vgaarb.h>
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#include <asm/cacheflush.h>
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#include <asm/loongson.h>
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#define PCI_DEVICE_ID_LOONGSON_HOST 0x7a00
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#define PCI_DEVICE_ID_LOONGSON_DC1 0x7a06
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#define PCI_DEVICE_ID_LOONGSON_DC2 0x7a36
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int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 *val)
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{
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struct pci_bus *bus_tmp = pci_find_bus(domain, bus);
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if (bus_tmp)
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return bus_tmp->ops->read(bus_tmp, devfn, reg, len, val);
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return -EINVAL;
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}
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int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 val)
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{
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struct pci_bus *bus_tmp = pci_find_bus(domain, bus);
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if (bus_tmp)
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return bus_tmp->ops->write(bus_tmp, devfn, reg, len, val);
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return -EINVAL;
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}
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phys_addr_t mcfg_addr_init(int node)
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{
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return (((u64)node << 44) | MCFG_EXT_PCICFG_BASE);
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}
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static int __init pcibios_init(void)
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{
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unsigned int lsize;
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/*
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* Set PCI cacheline size to that of the last level in the
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* cache hierarchy.
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*/
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lsize = cpu_last_level_cache_line_size();
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BUG_ON(!lsize);
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pci_dfl_cache_line_size = lsize >> 2;
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pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
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return 0;
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}
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subsys_initcall(pcibios_init);
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int pcibios_device_add(struct pci_dev *dev)
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{
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int id;
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struct irq_domain *dom;
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id = pci_domain_nr(dev->bus);
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dom = irq_find_matching_fwnode(get_pch_msi_handle(id), DOMAIN_BUS_PCI_MSI);
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dev_set_msi_domain(&dev->dev, dom);
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return 0;
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}
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int pcibios_alloc_irq(struct pci_dev *dev)
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{
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if (acpi_disabled)
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return 0;
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if (pci_dev_msi_enabled(dev))
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return 0;
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return acpi_pci_irq_enable(dev);
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}
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static void pci_fixup_vgadev(struct pci_dev *pdev)
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{
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struct pci_dev *devp = NULL;
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while ((devp = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, devp))) {
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if (devp->vendor != PCI_VENDOR_ID_LOONGSON) {
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vga_set_default_device(devp);
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dev_info(&pdev->dev,
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"Overriding boot device as %X:%X\n",
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devp->vendor, devp->device);
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}
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DC1, pci_fixup_vgadev);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DC2, pci_fixup_vgadev);
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