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Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
23 lines
621 B
C
23 lines
621 B
C
/*
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* Copyright 2000 Deep Blue Solutions Ltd
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* Copyright 2004 ARM Limited
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* Copyright 2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#ifndef __CNS3XXX_CORE_H
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#define __CNS3XXX_CORE_H
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extern struct sys_timer cns3xxx_timer;
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void __init cns3xxx_map_io(void);
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void __init cns3xxx_init_irq(void);
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void cns3xxx_power_off(void);
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void cns3xxx_pwr_power_up(unsigned int block);
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void cns3xxx_pwr_power_down(unsigned int block);
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#endif /* __CNS3XXX_CORE_H */
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