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6ff9cb53da
Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's
Manual.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
40 lines
1.0 KiB
C
40 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a7744 CPG Core Clocks */
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#define R8A7744_CLK_Z 0
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#define R8A7744_CLK_ZG 1
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#define R8A7744_CLK_ZTR 2
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#define R8A7744_CLK_ZTRD2 3
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#define R8A7744_CLK_ZT 4
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#define R8A7744_CLK_ZX 5
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#define R8A7744_CLK_ZS 6
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#define R8A7744_CLK_HP 7
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#define R8A7744_CLK_B 9
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#define R8A7744_CLK_LB 10
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#define R8A7744_CLK_P 11
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#define R8A7744_CLK_CL 12
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#define R8A7744_CLK_M2 13
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#define R8A7744_CLK_ZB3 15
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#define R8A7744_CLK_ZB3D2 16
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#define R8A7744_CLK_DDR 17
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#define R8A7744_CLK_SDH 18
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#define R8A7744_CLK_SD0 19
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#define R8A7744_CLK_SD2 20
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#define R8A7744_CLK_SD3 21
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#define R8A7744_CLK_MMC0 22
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#define R8A7744_CLK_MP 23
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#define R8A7744_CLK_QSPI 26
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#define R8A7744_CLK_CP 27
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#define R8A7744_CLK_RCAN 28
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#define R8A7744_CLK_R 29
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#define R8A7744_CLK_OSC 30
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#endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ */
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