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fab957c11e
This contains all the code that directly interfaces with the RISC-V memory model. While this code corforms to the current RISC-V ISA specifications (user 2.2 and priv 1.10), the memory model is somewhat underspecified in those documents. There is a working group that hopes to produce a formal memory model by the end of the year, but my understanding is that the basic definitions we're relying on here won't change significantly. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
/*
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* Based on arch/arm/include/asm/barrier.h
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*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2013 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _ASM_RISCV_BARRIER_H
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#define _ASM_RISCV_BARRIER_H
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#ifndef __ASSEMBLY__
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#define nop() __asm__ __volatile__ ("nop")
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#define RISCV_FENCE(p, s) \
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__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
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/* These barriers need to enforce ordering on both devices or memory. */
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#define mb() RISCV_FENCE(iorw,iorw)
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#define rmb() RISCV_FENCE(ir,ir)
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#define wmb() RISCV_FENCE(ow,ow)
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/* These barriers do not need to enforce ordering on devices, just memory. */
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#define smp_mb() RISCV_FENCE(rw,rw)
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#define smp_rmb() RISCV_FENCE(r,r)
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#define smp_wmb() RISCV_FENCE(w,w)
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/*
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* These fences exist to enforce ordering around the relaxed AMOs. The
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* documentation defines that
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* "
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* atomic_fetch_add();
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* is equivalent to:
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* smp_mb__before_atomic();
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* atomic_fetch_add_relaxed();
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* smp_mb__after_atomic();
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* "
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* So we emit full fences on both sides.
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*/
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#define __smb_mb__before_atomic() smp_mb()
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#define __smb_mb__after_atomic() smp_mb()
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/*
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* These barriers prevent accesses performed outside a spinlock from being moved
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* inside a spinlock. Since RISC-V sets the aq/rl bits on our spinlock only
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* enforce release consistency, we need full fences here.
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*/
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#define smb_mb__before_spinlock() smp_mb()
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#define smb_mb__after_spinlock() smp_mb()
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#include <asm-generic/barrier.h>
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_BARRIER_H */
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