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fdef72e02e
Skip reading this register as it is not relevant in the new devices. Signed-off-by: Koby Elbaz <kelbaz@habana.ai> Reviewed-by: Ofir Bitton <obitton@habana.ai> Reviewed-by: Moti Haimovski <mhaimovski@habana.ai> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
578 lines
15 KiB
C
578 lines
15 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2021-2023 Intel Corporation
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*/
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#include <linux/minmax.h>
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#include "xe_mmio.h"
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#include <drm/drm_managed.h>
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#include <drm/xe_drm.h>
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#include "regs/xe_engine_regs.h"
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#include "regs/xe_gt_regs.h"
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#include "regs/xe_regs.h"
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#include "xe_bo.h"
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#include "xe_device.h"
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#include "xe_gt.h"
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#include "xe_gt_mcr.h"
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#include "xe_macros.h"
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#include "xe_module.h"
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#define XEHP_MTCFG_ADDR XE_REG(0x101800)
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#define TILE_COUNT REG_GENMASK(15, 8)
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#define BAR_SIZE_SHIFT 20
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static int xe_set_dma_info(struct xe_device *xe)
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{
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unsigned int mask_size = xe->info.dma_mask_size;
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int err;
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dma_set_max_seg_size(xe->drm.dev, xe_sg_segment_size(xe->drm.dev));
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err = dma_set_mask(xe->drm.dev, DMA_BIT_MASK(mask_size));
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if (err)
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goto mask_err;
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err = dma_set_coherent_mask(xe->drm.dev, DMA_BIT_MASK(mask_size));
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if (err)
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goto mask_err;
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return 0;
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mask_err:
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drm_err(&xe->drm, "Can't set DMA mask/consistent mask (%d)\n", err);
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return err;
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}
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static void
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_resize_bar(struct xe_device *xe, int resno, resource_size_t size)
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{
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struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
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int bar_size = pci_rebar_bytes_to_size(size);
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int ret;
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if (pci_resource_len(pdev, resno))
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pci_release_resource(pdev, resno);
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ret = pci_resize_resource(pdev, resno, bar_size);
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if (ret) {
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drm_info(&xe->drm, "Failed to resize BAR%d to %dM (%pe). Consider enabling 'Resizable BAR' support in your BIOS\n",
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resno, 1 << bar_size, ERR_PTR(ret));
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return;
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}
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drm_info(&xe->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
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}
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/*
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* if force_vram_bar_size is set, attempt to set to the requested size
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* else set to maximum possible size
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*/
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static void xe_resize_vram_bar(struct xe_device *xe)
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{
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u64 force_vram_bar_size = xe_force_vram_bar_size;
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struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
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struct pci_bus *root = pdev->bus;
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resource_size_t current_size;
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resource_size_t rebar_size;
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struct resource *root_res;
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u32 bar_size_mask;
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u32 pci_cmd;
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int i;
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/* gather some relevant info */
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current_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
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bar_size_mask = pci_rebar_get_possible_sizes(pdev, GEN12_LMEM_BAR);
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if (!bar_size_mask)
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return;
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/* set to a specific size? */
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if (force_vram_bar_size) {
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u32 bar_size_bit;
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rebar_size = force_vram_bar_size * (resource_size_t)SZ_1M;
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bar_size_bit = bar_size_mask & BIT(pci_rebar_bytes_to_size(rebar_size));
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if (!bar_size_bit) {
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drm_info(&xe->drm,
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"Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leaving default: %lluMiB\n",
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(u64)rebar_size >> 20, bar_size_mask, (u64)current_size >> 20);
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return;
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}
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rebar_size = 1ULL << (__fls(bar_size_bit) + BAR_SIZE_SHIFT);
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if (rebar_size == current_size)
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return;
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} else {
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rebar_size = 1ULL << (__fls(bar_size_mask) + BAR_SIZE_SHIFT);
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/* only resize if larger than current */
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if (rebar_size <= current_size)
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return;
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}
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drm_info(&xe->drm, "Attempting to resize bar from %lluMiB -> %lluMiB\n",
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(u64)current_size >> 20, (u64)rebar_size >> 20);
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while (root->parent)
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root = root->parent;
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pci_bus_for_each_resource(root, root_res, i) {
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if (root_res && root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
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root_res->start > 0x100000000ull)
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break;
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}
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if (!root_res) {
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drm_info(&xe->drm, "Can't resize VRAM BAR - platform support is missing. Consider enabling 'Resizable BAR' support in your BIOS\n");
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return;
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}
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pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
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pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd & ~PCI_COMMAND_MEMORY);
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_resize_bar(xe, GEN12_LMEM_BAR, rebar_size);
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pci_assign_unassigned_bus_resources(pdev->bus);
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pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
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}
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static bool xe_pci_resource_valid(struct pci_dev *pdev, int bar)
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{
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if (!pci_resource_flags(pdev, bar))
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return false;
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if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)
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return false;
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if (!pci_resource_len(pdev, bar))
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return false;
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return true;
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}
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static int xe_determine_lmem_bar_size(struct xe_device *xe)
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{
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struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
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if (!xe_pci_resource_valid(pdev, GEN12_LMEM_BAR)) {
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drm_err(&xe->drm, "pci resource is not valid\n");
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return -ENXIO;
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}
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xe_resize_vram_bar(xe);
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xe->mem.vram.io_start = pci_resource_start(pdev, GEN12_LMEM_BAR);
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xe->mem.vram.io_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
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if (!xe->mem.vram.io_size)
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return -EIO;
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/* XXX: Need to change when xe link code is ready */
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xe->mem.vram.dpa_base = 0;
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/* set up a map to the total memory area. */
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xe->mem.vram.mapping = ioremap_wc(xe->mem.vram.io_start, xe->mem.vram.io_size);
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return 0;
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}
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/**
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* xe_mmio_tile_vram_size() - Collect vram size and offset information
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* @tile: tile to get info for
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* @vram_size: available vram (size - device reserved portions)
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* @tile_size: actual vram size
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* @tile_offset: physical start point in the vram address space
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*
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* There are 4 places for size information:
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* - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1)
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* - TILEx size (actual vram size)
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* - GSMBASE offset (TILEx - "stolen")
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* - CSSBASE offset (TILEx - CSS space necessary)
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*
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* CSSBASE is always a lower/smaller offset then GSMBASE.
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*
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* The actual available size of memory is to the CCS or GSM base.
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* NOTE: multi-tile bases will include the tile offset.
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*
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*/
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int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size, u64 *tile_size, u64 *tile_offset)
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{
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struct xe_device *xe = tile_to_xe(tile);
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struct xe_gt *gt = tile->primary_gt;
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u64 offset;
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int err;
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u32 reg;
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err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
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if (err)
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return err;
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/* actual size */
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if (unlikely(xe->info.platform == XE_DG1)) {
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*tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), GEN12_LMEM_BAR);
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*tile_offset = 0;
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} else {
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reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE_ADDR_RANGE(gt->info.id));
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*tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
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*tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;
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}
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/* minus device usage */
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if (xe->info.has_flat_ccs) {
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reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
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offset = (u64)REG_FIELD_GET(GENMASK(31, 8), reg) * SZ_64K;
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} else {
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offset = xe_mmio_read64_2x32(gt, GSMBASE);
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}
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/* remove the tile offset so we have just the available size */
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*vram_size = offset - *tile_offset;
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return xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
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}
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int xe_mmio_probe_vram(struct xe_device *xe)
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{
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struct xe_tile *tile;
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resource_size_t io_size;
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u64 available_size = 0;
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u64 total_size = 0;
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u64 tile_offset;
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u64 tile_size;
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u64 vram_size;
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int err;
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u8 id;
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if (!IS_DGFX(xe))
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return 0;
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/* Get the size of the root tile's vram for later accessibility comparison */
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tile = xe_device_get_root_tile(xe);
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err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
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if (err)
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return err;
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err = xe_determine_lmem_bar_size(xe);
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if (err)
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return err;
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drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
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&xe->mem.vram.io_size);
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io_size = xe->mem.vram.io_size;
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/* tile specific ranges */
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for_each_tile(tile, xe, id) {
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err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
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if (err)
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return err;
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tile->mem.vram.actual_physical_size = tile_size;
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tile->mem.vram.io_start = xe->mem.vram.io_start + tile_offset;
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tile->mem.vram.io_size = min_t(u64, vram_size, io_size);
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if (!tile->mem.vram.io_size) {
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drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n");
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return -ENODEV;
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}
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tile->mem.vram.dpa_base = xe->mem.vram.dpa_base + tile_offset;
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tile->mem.vram.usable_size = vram_size;
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tile->mem.vram.mapping = xe->mem.vram.mapping + tile_offset;
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if (tile->mem.vram.io_size < tile->mem.vram.usable_size)
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drm_info(&xe->drm, "Small BAR device\n");
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drm_info(&xe->drm, "VRAM[%u, %u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", id,
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tile->id, &tile->mem.vram.actual_physical_size, &tile->mem.vram.usable_size, &tile->mem.vram.io_size);
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drm_info(&xe->drm, "VRAM[%u, %u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", id, tile->id,
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&tile->mem.vram.dpa_base, tile->mem.vram.dpa_base + tile->mem.vram.actual_physical_size,
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&tile->mem.vram.io_start, tile->mem.vram.io_start + tile->mem.vram.io_size);
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/* calculate total size using tile size to get the correct HW sizing */
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total_size += tile_size;
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available_size += vram_size;
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if (total_size > xe->mem.vram.io_size) {
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drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n",
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&total_size, &xe->mem.vram.io_size);
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}
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io_size -= min_t(u64, tile_size, io_size);
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}
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xe->mem.vram.actual_physical_size = total_size;
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drm_info(&xe->drm, "Total VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
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&xe->mem.vram.actual_physical_size);
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drm_info(&xe->drm, "Available VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
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&available_size);
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return 0;
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}
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static void xe_mmio_probe_tiles(struct xe_device *xe)
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{
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u8 adj_tile_count = xe->info.tile_count;
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struct xe_gt *gt = xe_root_mmio_gt(xe);
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u32 mtcfg;
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u8 id;
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if (xe->info.tile_count == 1)
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return;
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if (!xe->info.bypass_mtcfg) {
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mtcfg = xe_mmio_read64_2x32(gt, XEHP_MTCFG_ADDR);
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adj_tile_count = xe->info.tile_count =
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REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
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/*
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* FIXME: Needs some work for standalone media, but should be impossible
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* with multi-tile for now.
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*/
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xe->info.gt_count = xe->info.tile_count;
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drm_info(&xe->drm, "tile_count: %d, adj_tile_count %d\n",
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xe->info.tile_count, adj_tile_count);
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}
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if (xe->info.tile_count > 1) {
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const int mmio_bar = 0;
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struct xe_tile *tile;
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size_t size;
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void *regs;
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if (adj_tile_count > 1) {
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pci_iounmap(to_pci_dev(xe->drm.dev), xe->mmio.regs);
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xe->mmio.size = SZ_16M * adj_tile_count;
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xe->mmio.regs = pci_iomap(to_pci_dev(xe->drm.dev),
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mmio_bar, xe->mmio.size);
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}
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size = xe->mmio.size / adj_tile_count;
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regs = xe->mmio.regs;
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for_each_tile(tile, xe, id) {
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tile->mmio.size = size;
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tile->mmio.regs = regs;
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regs += size;
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}
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}
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}
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static void mmio_fini(struct drm_device *drm, void *arg)
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{
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struct xe_device *xe = arg;
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pci_iounmap(to_pci_dev(xe->drm.dev), xe->mmio.regs);
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if (xe->mem.vram.mapping)
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iounmap(xe->mem.vram.mapping);
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}
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int xe_mmio_init(struct xe_device *xe)
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{
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struct xe_tile *root_tile = xe_device_get_root_tile(xe);
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struct xe_gt *gt = xe_root_mmio_gt(xe);
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const int mmio_bar = 0;
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int err;
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/*
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* Map the first 16MB of th BAR, which includes the registers (0-4MB),
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* reserved space (4MB-8MB), and GGTT (8MB-16MB) for a single tile.
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* This will get remapped later if we determine that we're running
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* on a multi-tile system.
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*/
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xe->mmio.size = SZ_16M;
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xe->mmio.regs = pci_iomap(to_pci_dev(xe->drm.dev), mmio_bar,
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xe->mmio.size);
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if (xe->mmio.regs == NULL) {
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drm_err(&xe->drm, "failed to map registers\n");
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return -EIO;
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}
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err = drmm_add_action_or_reset(&xe->drm, mmio_fini, xe);
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if (err)
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return err;
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/* Setup first tile; other tiles (if present) will be setup later. */
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root_tile->mmio.size = xe->mmio.size;
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root_tile->mmio.regs = xe->mmio.regs;
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/*
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* The boot firmware initializes local memory and assesses its health.
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* If memory training fails, the punit will have been instructed to
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* keep the GT powered down; we won't be able to communicate with it
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* and we should not continue with driver initialization.
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*/
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if (IS_DGFX(xe) && !(xe_mmio_read32(gt, GU_CNTL) & LMEM_INIT)) {
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drm_err(&xe->drm, "VRAM not initialized by firmware\n");
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return -ENODEV;
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}
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err = xe_set_dma_info(xe);
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if (err)
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return err;
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xe_mmio_probe_tiles(xe);
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return 0;
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}
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#define VALID_MMIO_FLAGS (\
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DRM_XE_MMIO_BITS_MASK |\
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DRM_XE_MMIO_READ |\
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DRM_XE_MMIO_WRITE)
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static const struct xe_reg mmio_read_whitelist[] = {
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RING_TIMESTAMP(RENDER_RING_BASE),
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};
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int xe_mmio_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct xe_device *xe = to_xe_device(dev);
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struct xe_gt *gt = xe_root_mmio_gt(xe);
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struct drm_xe_mmio *args = data;
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unsigned int bits_flag, bytes;
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struct xe_reg reg;
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bool allowed;
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int ret = 0;
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if (XE_IOCTL_DBG(xe, args->extensions) ||
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XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
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return -EINVAL;
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if (XE_IOCTL_DBG(xe, args->flags & ~VALID_MMIO_FLAGS))
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return -EINVAL;
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if (XE_IOCTL_DBG(xe, !(args->flags & DRM_XE_MMIO_WRITE) && args->value))
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return -EINVAL;
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allowed = capable(CAP_SYS_ADMIN);
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if (!allowed && ((args->flags & ~DRM_XE_MMIO_BITS_MASK) == DRM_XE_MMIO_READ)) {
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(mmio_read_whitelist); i++) {
|
|
if (mmio_read_whitelist[i].addr == args->addr) {
|
|
allowed = true;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (XE_IOCTL_DBG(xe, !allowed))
|
|
return -EPERM;
|
|
|
|
bits_flag = args->flags & DRM_XE_MMIO_BITS_MASK;
|
|
bytes = 1 << bits_flag;
|
|
if (XE_IOCTL_DBG(xe, args->addr + bytes > xe->mmio.size))
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* TODO: migrate to xe_gt_mcr to lookup the mmio range and handle
|
|
* multicast registers. Steering would need uapi extension.
|
|
*/
|
|
reg = XE_REG(args->addr);
|
|
|
|
xe_device_mem_access_get(xe);
|
|
xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
|
|
|
|
if (args->flags & DRM_XE_MMIO_WRITE) {
|
|
switch (bits_flag) {
|
|
case DRM_XE_MMIO_32BIT:
|
|
if (XE_IOCTL_DBG(xe, args->value > U32_MAX)) {
|
|
ret = -EINVAL;
|
|
goto exit;
|
|
}
|
|
xe_mmio_write32(gt, reg, args->value);
|
|
break;
|
|
default:
|
|
drm_dbg(&xe->drm, "Invalid MMIO bit size");
|
|
fallthrough;
|
|
case DRM_XE_MMIO_8BIT: /* TODO */
|
|
case DRM_XE_MMIO_16BIT: /* TODO */
|
|
ret = -EOPNOTSUPP;
|
|
goto exit;
|
|
}
|
|
}
|
|
|
|
if (args->flags & DRM_XE_MMIO_READ) {
|
|
switch (bits_flag) {
|
|
case DRM_XE_MMIO_32BIT:
|
|
args->value = xe_mmio_read32(gt, reg);
|
|
break;
|
|
case DRM_XE_MMIO_64BIT:
|
|
args->value = xe_mmio_read64_2x32(gt, reg);
|
|
break;
|
|
default:
|
|
drm_dbg(&xe->drm, "Invalid MMIO bit size");
|
|
fallthrough;
|
|
case DRM_XE_MMIO_8BIT: /* TODO */
|
|
case DRM_XE_MMIO_16BIT: /* TODO */
|
|
ret = -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
exit:
|
|
xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);
|
|
xe_device_mem_access_put(xe);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* xe_mmio_read64_2x32() - Read a 64-bit register as two 32-bit reads
|
|
* @gt: MMIO target GT
|
|
* @reg: register to read value from
|
|
*
|
|
* Although Intel GPUs have some 64-bit registers, the hardware officially
|
|
* only supports GTTMMADR register reads of 32 bits or smaller. Even if
|
|
* a readq operation may return a reasonable value, that violation of the
|
|
* spec shouldn't be relied upon and all 64-bit register reads should be
|
|
* performed as two 32-bit reads of the upper and lower dwords.
|
|
*
|
|
* When reading registers that may be changing (such as
|
|
* counters), a rollover of the lower dword between the two 32-bit reads
|
|
* can be problematic. This function attempts to ensure the upper dword has
|
|
* stabilized before returning the 64-bit value.
|
|
*
|
|
* Note that because this function may re-read the register multiple times
|
|
* while waiting for the value to stabilize it should not be used to read
|
|
* any registers where read operations have side effects.
|
|
*
|
|
* Returns the value of the 64-bit register.
|
|
*/
|
|
u64 xe_mmio_read64_2x32(struct xe_gt *gt, struct xe_reg reg)
|
|
{
|
|
struct xe_reg reg_udw = { .addr = reg.addr + 0x4 };
|
|
u32 ldw, udw, oldudw, retries;
|
|
|
|
if (reg.addr < gt->mmio.adj_limit) {
|
|
reg.addr += gt->mmio.adj_offset;
|
|
reg_udw.addr += gt->mmio.adj_offset;
|
|
}
|
|
|
|
oldudw = xe_mmio_read32(gt, reg_udw);
|
|
for (retries = 5; retries; --retries) {
|
|
ldw = xe_mmio_read32(gt, reg);
|
|
udw = xe_mmio_read32(gt, reg_udw);
|
|
|
|
if (udw == oldudw)
|
|
break;
|
|
|
|
oldudw = udw;
|
|
}
|
|
|
|
xe_gt_WARN(gt, retries == 0,
|
|
"64-bit read of %#x did not stabilize\n", reg.addr);
|
|
|
|
return (u64)udw << 32 | ldw;
|
|
}
|
|
|