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ebb945a94b
This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
23 lines
458 B
C
23 lines
458 B
C
#include "nouveau_revcompat.h"
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#include "nouveau_drv.h"
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#include "nv50_display.h"
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struct nouveau_drm *
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nouveau_newpriv(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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return dev_priv->newpriv;
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}
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struct nouveau_bo *
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nv50sema(struct drm_device *dev, int crtc)
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{
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return nv50_display(dev)->crtc[crtc].sem.bo;
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}
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struct nouveau_bo *
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nvd0sema(struct drm_device *dev, int crtc)
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{
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return nvd0_display_crtc_sema(dev, crtc);
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}
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