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3989efb770
The empty_zero_page[] export is required for ZERO_PAGE() module references. The #includes are due to changes in implicit inclusion, and should of course have been in the sources from the beginning. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
253 lines
6.9 KiB
C
253 lines
6.9 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#include <linux/mm.h>
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#include <linux/dma-mapping.h>
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#include <linux/vmalloc.h>
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#include <linux/export.h>
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#include <asm/tlbflush.h>
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#include <asm/homecache.h>
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/* Generic DMA mapping functions: */
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/*
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* Allocate what Linux calls "coherent" memory, which for us just
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* means uncached.
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*/
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void *dma_alloc_coherent(struct device *dev,
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size_t size,
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dma_addr_t *dma_handle,
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gfp_t gfp)
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{
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u64 dma_mask = dev->coherent_dma_mask ?: DMA_BIT_MASK(32);
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int node = dev_to_node(dev);
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int order = get_order(size);
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struct page *pg;
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dma_addr_t addr;
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gfp |= __GFP_ZERO;
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/*
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* By forcing NUMA node 0 for 32-bit masks we ensure that the
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* high 32 bits of the resulting PA will be zero. If the mask
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* size is, e.g., 24, we may still not be able to guarantee a
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* suitable memory address, in which case we will return NULL.
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* But such devices are uncommon.
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*/
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if (dma_mask <= DMA_BIT_MASK(32))
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node = 0;
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pg = homecache_alloc_pages_node(node, gfp, order, PAGE_HOME_UNCACHED);
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if (pg == NULL)
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return NULL;
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addr = page_to_phys(pg);
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if (addr + size > dma_mask) {
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homecache_free_pages(addr, order);
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return NULL;
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}
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*dma_handle = addr;
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return page_address(pg);
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}
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EXPORT_SYMBOL(dma_alloc_coherent);
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/*
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* Free memory that was allocated with dma_alloc_coherent.
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*/
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void dma_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle)
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{
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homecache_free_pages((unsigned long)vaddr, get_order(size));
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}
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EXPORT_SYMBOL(dma_free_coherent);
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/*
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* The map routines "map" the specified address range for DMA
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* accesses. The memory belongs to the device after this call is
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* issued, until it is unmapped with dma_unmap_single.
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*
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* We don't need to do any mapping, we just flush the address range
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* out of the cache and return a DMA address.
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*
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* The unmap routines do whatever is necessary before the processor
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* accesses the memory again, and must be called before the driver
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* touches the memory. We can get away with a cache invalidate if we
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* can count on nothing having been touched.
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*/
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/* Flush a PA range from cache page by page. */
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static void __dma_map_pa_range(dma_addr_t dma_addr, size_t size)
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{
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struct page *page = pfn_to_page(PFN_DOWN(dma_addr));
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size_t bytesleft = PAGE_SIZE - (dma_addr & (PAGE_SIZE - 1));
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while ((ssize_t)size > 0) {
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/* Flush the page. */
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homecache_flush_cache(page++, 0);
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/* Figure out if we need to continue on the next page. */
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size -= bytesleft;
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bytesleft = PAGE_SIZE;
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}
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}
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/*
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* dma_map_single can be passed any memory address, and there appear
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* to be no alignment constraints.
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*
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* There is a chance that the start of the buffer will share a cache
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* line with some other data that has been touched in the meantime.
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*/
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dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
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enum dma_data_direction direction)
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{
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dma_addr_t dma_addr = __pa(ptr);
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(size == 0);
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__dma_map_pa_range(dma_addr, size);
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return dma_addr;
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}
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EXPORT_SYMBOL(dma_map_single);
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void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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}
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EXPORT_SYMBOL(dma_unmap_single);
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int dma_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
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enum dma_data_direction direction)
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{
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struct scatterlist *sg;
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int i;
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(nents == 0 || sglist->length == 0);
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for_each_sg(sglist, sg, nents, i) {
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sg->dma_address = sg_phys(sg);
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__dma_map_pa_range(sg->dma_address, sg->length);
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}
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return nents;
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}
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EXPORT_SYMBOL(dma_map_sg);
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void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
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enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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}
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EXPORT_SYMBOL(dma_unmap_sg);
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dma_addr_t dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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BUG_ON(offset + size > PAGE_SIZE);
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homecache_flush_cache(page, 0);
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return page_to_pa(page) + offset;
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}
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EXPORT_SYMBOL(dma_map_page);
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void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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}
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EXPORT_SYMBOL(dma_unmap_page);
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void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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}
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EXPORT_SYMBOL(dma_sync_single_for_cpu);
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void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction direction)
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{
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unsigned long start = PFN_DOWN(dma_handle);
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unsigned long end = PFN_DOWN(dma_handle + size - 1);
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unsigned long i;
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BUG_ON(!valid_dma_direction(direction));
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for (i = start; i <= end; ++i)
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homecache_flush_cache(pfn_to_page(i), 0);
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}
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EXPORT_SYMBOL(dma_sync_single_for_device);
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void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(nelems == 0 || sg[0].length == 0);
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}
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EXPORT_SYMBOL(dma_sync_sg_for_cpu);
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/*
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* Flush and invalidate cache for scatterlist.
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*/
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void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction)
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{
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struct scatterlist *sg;
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int i;
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(nelems == 0 || sglist->length == 0);
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for_each_sg(sglist, sg, nelems, i) {
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dma_sync_single_for_device(dev, sg->dma_address,
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sg_dma_len(sg), direction);
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}
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}
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EXPORT_SYMBOL(dma_sync_sg_for_device);
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void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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dma_sync_single_for_cpu(dev, dma_handle + offset, size, direction);
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}
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EXPORT_SYMBOL(dma_sync_single_range_for_cpu);
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void dma_sync_single_range_for_device(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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dma_sync_single_for_device(dev, dma_handle + offset, size, direction);
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}
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EXPORT_SYMBOL(dma_sync_single_range_for_device);
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/*
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* dma_alloc_noncoherent() returns non-cacheable memory, so there's no
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* need to do any flushing here.
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*/
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void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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}
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EXPORT_SYMBOL(dma_cache_sync);
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