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a1d0d98daf
Add a platform for the Wire Speed Processor, based on the PPC A2. This includes code for the ICS & OPB interrupt controllers, as well as a SCOM backend, and SCOM based cpu bringup. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Jack Miller <jack@codezen.org> Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
21 lines
559 B
C
21 lines
559 B
C
/*
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* Copyright 2009 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef __ICS_H
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#define __ICS_H
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#define XIVE_ADDR_MASK 0x7FFULL
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extern void wsp_init_irq(void);
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extern int wsp_ics_alloc_irq(struct device_node *dn, int num);
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extern void wsp_ics_free_irq(struct device_node *dn, unsigned int irq);
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#endif /* __ICS_H */
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