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11b897cf84
On Alchemy the PCMCIA area lies at the end of the chips 36bit system bus area. Currently, addresses at the far end of the 32bit area are assumed to belong to the PCMCIA area and fixed up to the real 36bit address before being passed to ioremap(). A previous commit enabled 64 bit physical size for the resource datatype on Alchemy and this allows to use the correct 36bit addresses when registering the PCMCIA sockets. This patch removes the 32-to-36bit address fixup and registers the Alchemy demo board pcmcia socket with the correct 36bit physical addresses. Tested on DB1200, with a CF card (ide-cs driver) and a 3c589 PCMCIA ethernet card. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Manuel Lauss <manuel.lauss@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/994/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
43 lines
1.0 KiB
C
43 lines
1.0 KiB
C
/*
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* include/asm-mips/mach-au1x00/ioremap.h
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef __ASM_MACH_AU1X00_IOREMAP_H
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#define __ASM_MACH_AU1X00_IOREMAP_H
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#include <linux/types.h>
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI)
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extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
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#else
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static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
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{
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return phys_addr;
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}
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#endif
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/*
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* Allow physical addresses to be fixed up to help 36-bit peripherals.
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*/
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static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
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{
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return __fixup_bigphys_addr(phys_addr, size);
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}
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static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
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unsigned long flags)
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{
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return NULL;
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}
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static inline int plat_iounmap(const volatile void __iomem *addr)
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{
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return 0;
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}
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#endif /* __ASM_MACH_AU1X00_IOREMAP_H */
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