mirror of
https://github.com/torvalds/linux.git
synced 2024-12-25 12:21:37 +00:00
39f0fb6a34
The older simple ColdFire interrupt controller has no one-to-one mapping of interrupt numbers to bits in the interrupt mask register. Create a mapping array that each ColdFire CPU type can populate with its available interrupts and the bits that each use in the interrupt mask register. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
122 lines
3.2 KiB
C
122 lines
3.2 KiB
C
/***************************************************************************/
|
|
|
|
/*
|
|
* linux/arch/m68knommu/platform/5206/config.c
|
|
*
|
|
* Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
|
|
* Copyright (C) 2000-2001, Lineo Inc. (www.lineo.com)
|
|
*/
|
|
|
|
/***************************************************************************/
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/param.h>
|
|
#include <linux/init.h>
|
|
#include <linux/io.h>
|
|
#include <asm/machdep.h>
|
|
#include <asm/coldfire.h>
|
|
#include <asm/mcfsim.h>
|
|
#include <asm/mcfuart.h>
|
|
|
|
/***************************************************************************/
|
|
|
|
static struct mcf_platform_uart m5206_uart_platform[] = {
|
|
{
|
|
.mapbase = MCF_MBAR + MCFUART_BASE1,
|
|
.irq = 73,
|
|
},
|
|
{
|
|
.mapbase = MCF_MBAR + MCFUART_BASE2,
|
|
.irq = 74,
|
|
},
|
|
{ },
|
|
};
|
|
|
|
static struct platform_device m5206_uart = {
|
|
.name = "mcfuart",
|
|
.id = 0,
|
|
.dev.platform_data = m5206_uart_platform,
|
|
};
|
|
|
|
static struct platform_device *m5206_devices[] __initdata = {
|
|
&m5206_uart,
|
|
};
|
|
|
|
/***************************************************************************/
|
|
|
|
static void __init m5206_uart_init_line(int line, int irq)
|
|
{
|
|
if (line == 0) {
|
|
writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
|
|
writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
|
|
mcf_mapirq2imr(irq, MCFINTC_UART0);
|
|
} else if (line == 1) {
|
|
writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
|
|
writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
|
|
mcf_mapirq2imr(irq, MCFINTC_UART1);
|
|
}
|
|
}
|
|
|
|
static void __init m5206_uarts_init(void)
|
|
{
|
|
const int nrlines = ARRAY_SIZE(m5206_uart_platform);
|
|
int line;
|
|
|
|
for (line = 0; (line < nrlines); line++)
|
|
m5206_uart_init_line(line, m5206_uart_platform[line].irq);
|
|
}
|
|
|
|
/***************************************************************************/
|
|
|
|
static void __init m5206_timers_init(void)
|
|
{
|
|
/* Timer1 is always used as system timer */
|
|
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
|
|
MCF_MBAR + MCFSIM_TIMER1ICR);
|
|
mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
|
|
|
|
#ifdef CONFIG_HIGHPROFILE
|
|
/* Timer2 is to be used as a high speed profile timer */
|
|
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
|
|
MCF_MBAR + MCFSIM_TIMER2ICR);
|
|
mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
|
|
#endif
|
|
}
|
|
|
|
/***************************************************************************/
|
|
|
|
void m5206_cpu_reset(void)
|
|
{
|
|
local_irq_disable();
|
|
/* Set watchdog to soft reset, and enabled */
|
|
__raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
|
|
for (;;)
|
|
/* wait for watchdog to timeout */;
|
|
}
|
|
|
|
/***************************************************************************/
|
|
|
|
void __init config_BSP(char *commandp, int size)
|
|
{
|
|
mach_reset = m5206_cpu_reset;
|
|
m5206_timers_init();
|
|
m5206_uarts_init();
|
|
|
|
/* Only support the external interrupts on their primary level */
|
|
mcf_mapirq2imr(25, MCFINTC_EINT1);
|
|
mcf_mapirq2imr(28, MCFINTC_EINT4);
|
|
mcf_mapirq2imr(31, MCFINTC_EINT7);
|
|
}
|
|
|
|
/***************************************************************************/
|
|
|
|
static int __init init_BSP(void)
|
|
{
|
|
platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices));
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(init_BSP);
|
|
|
|
/***************************************************************************/
|