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57a6566799
The current arm64 __cmpxchg_double{_mb} implementations carry out the
compare exchange by first comparing the old values passed in to the
values read from the pointer provided and by stashing the cumulative
bitwise difference in a 64-bit register.
By comparing the register content against 0, it is possible to detect if
the values read differ from the old values passed in, so that the compare
exchange detects whether it has to bail out or carry on completing the
operation with the exchange.
Given the current implementation, to detect the cmpxchg operation
status, the __cmpxchg_double{_mb} functions should return the 64-bit
stashed bitwise difference so that the caller can detect cmpxchg failure
by comparing the return value content against 0. The current implementation
declares the return value as an int, which means that the 64-bit
value stashing the bitwise difference is truncated before being
returned to the __cmpxchg_double{_mb} callers, which means that
any bitwise difference present in the top 32 bits goes undetected,
triggering false positives and subsequent kernel failures.
This patch fixes the issue by declaring the arm64 __cmpxchg_double{_mb}
return values as a long, so that the bitwise difference is
properly propagated on failure, restoring the expected behaviour.
Fixes: e9a4b79565 ("arm64: cmpxchg_dbl: patch in lse instructions when supported by the CPU")
Cc: <stable@vger.kernel.org> # 4.3+
Cc: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
431 lines
11 KiB
C
431 lines
11 KiB
C
/*
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* Based on arch/arm/include/asm/atomic.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2002 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ATOMIC_LSE_H
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#define __ASM_ATOMIC_LSE_H
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#ifndef __ARM64_IN_ATOMIC_IMPL
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#error "please don't include this file directly"
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#endif
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#define __LL_SC_ATOMIC(op) __LL_SC_CALL(atomic_##op)
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static inline void atomic_andnot(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(andnot),
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" stclr %w[i], %[v]\n")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline void atomic_or(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(or),
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" stset %w[i], %[v]\n")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline void atomic_xor(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(xor),
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" steor %w[i], %[v]\n")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline void atomic_add(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(add),
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" stadd %w[i], %[v]\n")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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#define ATOMIC_OP_ADD_RETURN(name, mb, cl...) \
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static inline int atomic_add_return##name(int i, atomic_t *v) \
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{ \
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register int w0 asm ("w0") = i; \
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register atomic_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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" nop\n" \
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__LL_SC_ATOMIC(add_return##name), \
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/* LSE atomics */ \
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" ldadd" #mb " %w[i], w30, %[v]\n" \
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" add %w[i], %w[i], w30") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: "x30" , ##cl); \
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\
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return w0; \
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}
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ATOMIC_OP_ADD_RETURN(_relaxed, )
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ATOMIC_OP_ADD_RETURN(_acquire, a, "memory")
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ATOMIC_OP_ADD_RETURN(_release, l, "memory")
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ATOMIC_OP_ADD_RETURN( , al, "memory")
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#undef ATOMIC_OP_ADD_RETURN
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static inline void atomic_and(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC(and),
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/* LSE atomics */
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" mvn %w[i], %w[i]\n"
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" stclr %w[i], %[v]")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC(sub),
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/* LSE atomics */
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" neg %w[i], %w[i]\n"
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" stadd %w[i], %[v]")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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#define ATOMIC_OP_SUB_RETURN(name, mb, cl...) \
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static inline int atomic_sub_return##name(int i, atomic_t *v) \
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{ \
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register int w0 asm ("w0") = i; \
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register atomic_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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" nop\n" \
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__LL_SC_ATOMIC(sub_return##name) \
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" nop", \
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/* LSE atomics */ \
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" neg %w[i], %w[i]\n" \
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" ldadd" #mb " %w[i], w30, %[v]\n" \
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" add %w[i], %w[i], w30") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: "x30" , ##cl); \
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\
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return w0; \
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}
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ATOMIC_OP_SUB_RETURN(_relaxed, )
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ATOMIC_OP_SUB_RETURN(_acquire, a, "memory")
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ATOMIC_OP_SUB_RETURN(_release, l, "memory")
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ATOMIC_OP_SUB_RETURN( , al, "memory")
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#undef ATOMIC_OP_SUB_RETURN
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#undef __LL_SC_ATOMIC
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#define __LL_SC_ATOMIC64(op) __LL_SC_CALL(atomic64_##op)
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static inline void atomic64_andnot(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(andnot),
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" stclr %[i], %[v]\n")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline void atomic64_or(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(or),
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" stset %[i], %[v]\n")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline void atomic64_xor(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(xor),
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" steor %[i], %[v]\n")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline void atomic64_add(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(add),
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" stadd %[i], %[v]\n")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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#define ATOMIC64_OP_ADD_RETURN(name, mb, cl...) \
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static inline long atomic64_add_return##name(long i, atomic64_t *v) \
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{ \
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register long x0 asm ("x0") = i; \
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register atomic64_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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" nop\n" \
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__LL_SC_ATOMIC64(add_return##name), \
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/* LSE atomics */ \
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" ldadd" #mb " %[i], x30, %[v]\n" \
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" add %[i], %[i], x30") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: "x30" , ##cl); \
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\
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return x0; \
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}
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ATOMIC64_OP_ADD_RETURN(_relaxed, )
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ATOMIC64_OP_ADD_RETURN(_acquire, a, "memory")
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ATOMIC64_OP_ADD_RETURN(_release, l, "memory")
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ATOMIC64_OP_ADD_RETURN( , al, "memory")
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#undef ATOMIC64_OP_ADD_RETURN
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static inline void atomic64_and(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC64(and),
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/* LSE atomics */
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" mvn %[i], %[i]\n"
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" stclr %[i], %[v]")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline void atomic64_sub(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC64(sub),
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/* LSE atomics */
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" neg %[i], %[i]\n"
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" stadd %[i], %[v]")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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#define ATOMIC64_OP_SUB_RETURN(name, mb, cl...) \
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static inline long atomic64_sub_return##name(long i, atomic64_t *v) \
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{ \
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register long x0 asm ("x0") = i; \
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register atomic64_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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" nop\n" \
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__LL_SC_ATOMIC64(sub_return##name) \
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" nop", \
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/* LSE atomics */ \
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" neg %[i], %[i]\n" \
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" ldadd" #mb " %[i], x30, %[v]\n" \
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" add %[i], %[i], x30") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: "x30" , ##cl); \
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\
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return x0; \
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}
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ATOMIC64_OP_SUB_RETURN(_relaxed, )
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ATOMIC64_OP_SUB_RETURN(_acquire, a, "memory")
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ATOMIC64_OP_SUB_RETURN(_release, l, "memory")
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ATOMIC64_OP_SUB_RETURN( , al, "memory")
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#undef ATOMIC64_OP_SUB_RETURN
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static inline long atomic64_dec_if_positive(atomic64_t *v)
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{
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register long x0 asm ("x0") = (long)v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC64(dec_if_positive)
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" nop\n"
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" nop\n"
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" nop\n"
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" nop\n"
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" nop",
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/* LSE atomics */
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"1: ldr x30, %[v]\n"
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" subs %[ret], x30, #1\n"
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" b.lt 2f\n"
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" casal x30, %[ret], %[v]\n"
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" sub x30, x30, #1\n"
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" sub x30, x30, %[ret]\n"
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" cbnz x30, 1b\n"
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"2:")
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: [ret] "+&r" (x0), [v] "+Q" (v->counter)
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:
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: "x30", "cc", "memory");
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return x0;
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}
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#undef __LL_SC_ATOMIC64
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#define __LL_SC_CMPXCHG(op) __LL_SC_CALL(__cmpxchg_case_##op)
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#define __CMPXCHG_CASE(w, sz, name, mb, cl...) \
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static inline unsigned long __cmpxchg_case_##name(volatile void *ptr, \
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unsigned long old, \
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unsigned long new) \
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{ \
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register unsigned long x0 asm ("x0") = (unsigned long)ptr; \
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register unsigned long x1 asm ("x1") = old; \
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register unsigned long x2 asm ("x2") = new; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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" nop\n" \
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__LL_SC_CMPXCHG(name) \
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" nop", \
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/* LSE atomics */ \
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" mov " #w "30, %" #w "[old]\n" \
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" cas" #mb #sz "\t" #w "30, %" #w "[new], %[v]\n" \
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" mov %" #w "[ret], " #w "30") \
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: [ret] "+r" (x0), [v] "+Q" (*(unsigned long *)ptr) \
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: [old] "r" (x1), [new] "r" (x2) \
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: "x30" , ##cl); \
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\
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return x0; \
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}
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__CMPXCHG_CASE(w, b, 1, )
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__CMPXCHG_CASE(w, h, 2, )
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__CMPXCHG_CASE(w, , 4, )
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__CMPXCHG_CASE(x, , 8, )
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__CMPXCHG_CASE(w, b, acq_1, a, "memory")
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__CMPXCHG_CASE(w, h, acq_2, a, "memory")
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__CMPXCHG_CASE(w, , acq_4, a, "memory")
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__CMPXCHG_CASE(x, , acq_8, a, "memory")
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__CMPXCHG_CASE(w, b, rel_1, l, "memory")
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__CMPXCHG_CASE(w, h, rel_2, l, "memory")
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__CMPXCHG_CASE(w, , rel_4, l, "memory")
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__CMPXCHG_CASE(x, , rel_8, l, "memory")
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__CMPXCHG_CASE(w, b, mb_1, al, "memory")
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__CMPXCHG_CASE(w, h, mb_2, al, "memory")
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__CMPXCHG_CASE(w, , mb_4, al, "memory")
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__CMPXCHG_CASE(x, , mb_8, al, "memory")
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#undef __LL_SC_CMPXCHG
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#undef __CMPXCHG_CASE
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#define __LL_SC_CMPXCHG_DBL(op) __LL_SC_CALL(__cmpxchg_double##op)
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#define __CMPXCHG_DBL(name, mb, cl...) \
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static inline long __cmpxchg_double##name(unsigned long old1, \
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unsigned long old2, \
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unsigned long new1, \
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unsigned long new2, \
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volatile void *ptr) \
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{ \
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unsigned long oldval1 = old1; \
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unsigned long oldval2 = old2; \
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register unsigned long x0 asm ("x0") = old1; \
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register unsigned long x1 asm ("x1") = old2; \
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register unsigned long x2 asm ("x2") = new1; \
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register unsigned long x3 asm ("x3") = new2; \
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register unsigned long x4 asm ("x4") = (unsigned long)ptr; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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" nop\n" \
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" nop\n" \
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" nop\n" \
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__LL_SC_CMPXCHG_DBL(name), \
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/* LSE atomics */ \
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" casp" #mb "\t%[old1], %[old2], %[new1], %[new2], %[v]\n"\
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" eor %[old1], %[old1], %[oldval1]\n" \
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" eor %[old2], %[old2], %[oldval2]\n" \
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" orr %[old1], %[old1], %[old2]") \
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: [old1] "+r" (x0), [old2] "+r" (x1), \
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[v] "+Q" (*(unsigned long *)ptr) \
|
|
: [new1] "r" (x2), [new2] "r" (x3), [ptr] "r" (x4), \
|
|
[oldval1] "r" (oldval1), [oldval2] "r" (oldval2) \
|
|
: "x30" , ##cl); \
|
|
\
|
|
return x0; \
|
|
}
|
|
|
|
__CMPXCHG_DBL( , )
|
|
__CMPXCHG_DBL(_mb, al, "memory")
|
|
|
|
#undef __LL_SC_CMPXCHG_DBL
|
|
#undef __CMPXCHG_DBL
|
|
|
|
#endif /* __ASM_ATOMIC_LSE_H */
|