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This lets the s3c64xx-spi driver know the specifics of the controller- variant and also setups the gpios and the misccr bit. This setup is valid for all S3C24XX SoCs containing a HSSPI controller (i.e. S3C2416/2450 and S3C2443) Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
40 lines
924 B
C
40 lines
924 B
C
/*
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* HS-SPI device setup for S3C2443/S3C2416
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*
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* Copyright (C) 2011 Samsung Electronics Ltd.
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <plat/gpio-cfg.h>
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#include <plat/s3c64xx-spi.h>
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#include <mach/hardware.h>
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#include <mach/regs-gpio.h>
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#ifdef CONFIG_S3C64XX_DEV_SPI0
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struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 13,
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.tx_st_done = 21,
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.high_speed = 1,
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};
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int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
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{
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/* enable hsspi bit in misccr */
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s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);
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s3c_gpio_cfgall_range(S3C2410_GPE(11), 3,
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S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
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return 0;
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}
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#endif
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