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c5a48ffb52
I typoed the pin header name when copying it from my notes on paper.
Fixes: 9da1c0327d ("arm64: dts: rockchip: Add basic support for QNAP TS-433")
Signed-off-by: Uwe Kleine-König <ukleinek@debian.org>
Link: https://lore.kernel.org/r/20240301163201.559787-2-ukleinek@debian.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
87 lines
1.6 KiB
Plaintext
87 lines
1.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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* Copyright (c) 2024 Uwe Kleine-König
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "rk3568.dtsi"
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/ {
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model = "Qnap TS-433-4G NAS System 4-Bay";
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compatible = "qnap,ts433", "rockchip,rk3568";
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};
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&gmac0 {
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assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
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assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
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assigned-clock-rates = <0>, <125000000>;
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clock_in_out = "output";
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phy-handle = <&rgmii_phy0>;
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phy-mode = "rgmii";
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pinctrl-names = "default";
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pinctrl-0 = <&gmac0_miim
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&gmac0_tx_bus2
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&gmac0_rx_bus2
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&gmac0_rgmii_clk
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&gmac0_rgmii_bus>;
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rx_delay = <0x2f>;
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tx_delay = <0x3c>;
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status = "okay";
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};
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&i2c0 {
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pmic@20 {
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compatible = "rockchip,rk809";
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reg = <0x20>;
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interrupt-parent = <&gpio0>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&i2c1 {
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status = "okay";
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rtc@51 {
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compatible = "microcrystal,rv8263";
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reg = <0x51>;
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wakeup-source;
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};
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};
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&mdio0 {
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rgmii_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x0>;
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};
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};
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&pcie30phy {
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status = "okay";
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};
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&pcie3x1 {
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/* The downstream dts has: rockchip,bifurcation, XXX: find out what this is about */
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reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&sdhci {
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bus-width = <8>;
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max-frequency = <200000000>;
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non-removable;
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status = "okay";
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};
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/*
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* Pins available on CN3 connector at TTL voltage level (3V3).
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* ,_ _.
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* |1234| 1=TX 2=VCC
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* `----' 3=RX 4=GND
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*/
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&uart2 {
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status = "okay";
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};
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